ArmPkg/ArmLib: Renamed Cp15CacheInfo into ArmCacheInfo

CTR (Cache Type Register) has the same format on ARMv7 and AArch64.
Renaming Cp15CacheInfo() into ArmCacheInfo() makes this function
architecture independent.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15381 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 7a0467130d5e8ee3de9005914a15551e95f4bd0f..b0ce6c7cc623670ef10d53d0ae3506dc8a3b1b6e 100644 (file)
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -212,9 +212,9 @@ ArmReadIdPfr1 (
   VOID\r
   );\r
 \r
-UINT32\r
+UINTN\r
 EFIAPI\r
-Cp15CacheInfo (\r
+ArmCacheInfo (\r
   VOID\r
   );\r
 \r

diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c b/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c
index 6180a47de7e6855a3a5e78823534c37352b5ab7c..19da4db25864386ecff95b95a5969d4f1ef67e13 100644 (file)
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c
+++ b/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c
@@ -1,7 +1,8 @@
 /** @file\r
 \r
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-  \r
+  Copyright (c) 2014, ARM Limited. All rights reserved.\r
+\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -21,7 +22,7 @@ ArmCacheType (
   VOID\r
   )\r
 {\r
-  switch (CACHE_TYPE(Cp15CacheInfo()))\r
+  switch (CACHE_TYPE (ArmCacheInfo ()))\r
   {\r
     case CACHE_TYPE_WRITE_BACK: return ARM_CACHE_TYPE_WRITE_BACK;\r
     default:                    return ARM_CACHE_TYPE_UNKNOWN;\r
@@ -34,7 +35,7 @@ ArmCacheArchitecture (
   VOID\r
   )\r
 {\r
-  switch (CACHE_ARCHITECTURE(Cp15CacheInfo()))\r
+  switch (CACHE_ARCHITECTURE (ArmCacheInfo ()))\r
   {\r
     case CACHE_ARCHITECTURE_UNIFIED:  return ARM_CACHE_ARCHITECTURE_UNIFIED;\r
     case CACHE_ARCHITECTURE_SEPARATE: return ARM_CACHE_ARCHITECTURE_SEPARATE;\r
@@ -48,7 +49,7 @@ ArmDataCachePresent (
   VOID\r
   )\r
 {\r
-  switch (DATA_CACHE_PRESENT(Cp15CacheInfo()))\r
+  switch (DATA_CACHE_PRESENT (ArmCacheInfo ()))\r
   {\r
     case CACHE_PRESENT:     return TRUE;\r
     case CACHE_NOT_PRESENT: return FALSE;\r
@@ -62,7 +63,7 @@ ArmDataCacheSize (
   VOID\r
   )\r
 {\r
-  switch (DATA_CACHE_SIZE(Cp15CacheInfo()))\r
+  switch (DATA_CACHE_SIZE (ArmCacheInfo ()))\r
   {\r
     case CACHE_SIZE_4_KB:   return   4 * 1024;      \r
     case CACHE_SIZE_8_KB:   return   8 * 1024;\r
@@ -80,7 +81,7 @@ ArmDataCacheAssociativity (
   VOID\r
   )\r
 {\r
-  switch (DATA_CACHE_ASSOCIATIVITY(Cp15CacheInfo()))\r
+  switch (DATA_CACHE_ASSOCIATIVITY (ArmCacheInfo ()))\r
   {\r
     case CACHE_ASSOCIATIVITY_4_WAY:   return 4;\r
     case CACHE_ASSOCIATIVITY_DIRECT:  return 1;\r
@@ -94,7 +95,7 @@ ArmDataCacheLineLength (
   VOID\r
   )\r
 {\r
-  switch (DATA_CACHE_LINE_LENGTH(Cp15CacheInfo()))\r
+  switch (DATA_CACHE_LINE_LENGTH (ArmCacheInfo ()))\r
   {\r
     case CACHE_LINE_LENGTH_32_BYTES: return 32;\r
     default:                         return  0;\r
@@ -107,7 +108,7 @@ ArmInstructionCachePresent (
   VOID\r
   )\r
 {\r
-  switch (INSTRUCTION_CACHE_PRESENT(Cp15CacheInfo()))\r
+  switch (INSTRUCTION_CACHE_PRESENT (ArmCacheInfo ()))\r
   {\r
     case CACHE_PRESENT:     return TRUE;\r
     case CACHE_NOT_PRESENT: return FALSE;\r
@@ -121,7 +122,7 @@ ArmInstructionCacheSize (
   VOID\r
   )\r
 {\r
-  switch (INSTRUCTION_CACHE_SIZE(Cp15CacheInfo()))\r
+  switch (INSTRUCTION_CACHE_SIZE (ArmCacheInfo ()))\r
   {\r
     case CACHE_SIZE_4_KB:   return   4 * 1024;      \r
     case CACHE_SIZE_8_KB:   return   8 * 1024;\r
@@ -139,7 +140,7 @@ ArmInstructionCacheAssociativity (
   VOID\r
   )\r
 {\r
-  switch (INSTRUCTION_CACHE_ASSOCIATIVITY(Cp15CacheInfo()))\r
+  switch (INSTRUCTION_CACHE_ASSOCIATIVITY (ArmCacheInfo ()))\r
   {\r
     case CACHE_ASSOCIATIVITY_8_WAY:   return 8;\r
     case CACHE_ASSOCIATIVITY_4_WAY:   return 4;\r
@@ -154,7 +155,7 @@ ArmInstructionCacheLineLength (
   VOID\r
   )\r
 {\r
-  switch (INSTRUCTION_CACHE_LINE_LENGTH(Cp15CacheInfo()))\r
+  switch (INSTRUCTION_CACHE_LINE_LENGTH (ArmCacheInfo ()))\r
   {\r
     case CACHE_LINE_LENGTH_32_BYTES: return 32;\r
     default:                         return  0;\r

diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
index a3de902cc63b0e61ea4399ec72e751b9dd7daf1f..f3b949565f187a44517787c731458bd5e0fd1327 100644 (file)
--- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
@@ -24,7 +24,7 @@
 .text\r
 .align 2\r
 GCC_ASM_EXPORT(ArmReadMidr)\r
-GCC_ASM_EXPORT(Cp15CacheInfo)\r
+GCC_ASM_EXPORT(ArmCacheInfo)\r
 GCC_ASM_EXPORT(ArmGetInterruptState)\r
 GCC_ASM_EXPORT(ArmGetFiqState)\r
 GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)\r
@@ -54,7 +54,7 @@ ASM_PFX(ArmReadMidr):
   mrc     p15,0,R0,c0,c0,0\r
   bx      LR\r
 \r
-ASM_PFX(Cp15CacheInfo):\r
+ASM_PFX(ArmCacheInfo):\r
   mrc     p15,0,R0,c0,c0,1\r
   bx      LR\r
 \r

diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
index cb69f71bc71f218c3b7e86f25cf8f0dac7245804..2e26ff35cfa99a4a89c63b37a121681093b5c455 100644 (file)
--- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
+++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
@@ -24,7 +24,7 @@
 #endif\r
 \r
     EXPORT ArmReadMidr\r
-    EXPORT Cp15CacheInfo\r
+    EXPORT ArmCacheInfo\r
     EXPORT ArmGetInterruptState\r
     EXPORT ArmGetFiqState\r
     EXPORT ArmGetTTBR0BaseAddress\r
@@ -54,7 +54,7 @@ ArmReadMidr
   mrc     p15,0,R0,c0,c0,0\r
   bx      LR\r
 \r
-Cp15CacheInfo\r
+ArmCacheInfo\r
   mrc     p15,0,R0,c0,c0,1\r
   bx      LR\r
 \r