UefiCpuPkg/PentiumMMsr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>

diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h b/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
index 324fc9b88cfd925d3fc672e293c0aa64e145ce85..3040631fbe34600afa18f10a1826c45d4499410c 100644 (file)
--- a/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
@@ -40,6 +40,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);\r
   AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);\r
   @endcode\r
+  @note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r
 **/\r
 #define MSR_PENTIUM_M_P5_MC_ADDR                 0x00000000\r
 \r
@@ -58,6 +59,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);\r
   AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);\r
   @endcode\r
+  @note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r
 **/\r
 #define MSR_PENTIUM_M_P5_MC_TYPE                 0x00000001\r
 \r
@@ -79,6 +81,7 @@
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);\r
   AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);\r
   @endcode\r
+  @note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
 **/\r
 #define MSR_PENTIUM_M_EBL_CR_POWERON             0x0000002A\r
 \r
@@ -195,6 +198,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);\r
   AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);\r
   @endcode\r
+  @note MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.\r
+        MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.\r
+        MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.\r
+        MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.\r
+        MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.\r
+        MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.\r
+        MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.\r
+        MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.\r
   @{\r
 **/\r
 #define MSR_PENTIUM_M_LASTBRANCH_0               0x00000040\r
@@ -222,6 +233,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL);\r
   AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr);\r
   @endcode\r
+  @note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.\r
 **/\r
 #define MSR_PENTIUM_M_BBL_CR_CTL                 0x00000119\r
 \r
@@ -242,6 +254,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3);\r
   AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64);\r
   @endcode\r
+  @note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
 **/\r
 #define MSR_PENTIUM_M_BBL_CR_CTL3                0x0000011E\r
 \r
@@ -308,6 +321,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL);\r
   AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64);\r
   @endcode\r
+  @note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
 **/\r
 #define MSR_PENTIUM_M_THERM2_CTL                 0x0000019D\r
 \r
@@ -359,6 +373,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE);\r
   AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64);\r
   @endcode\r
+  @note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
 **/\r
 #define MSR_PENTIUM_M_IA32_MISC_ENABLE           0x000001A0\r
 \r
@@ -460,6 +475,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS);\r
   AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr);\r
   @endcode\r
+  @note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
 **/\r
 #define MSR_PENTIUM_M_LASTBRANCH_TOS             0x000001C9\r
 \r
@@ -480,6 +496,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB);\r
   AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr);\r
   @endcode\r
+  @note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.\r
 **/\r
 #define MSR_PENTIUM_M_DEBUGCTLB                  0x000001D9\r
 \r
@@ -502,6 +519,7 @@ typedef union {
 \r
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP);\r
   @endcode\r
+  @note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
 **/\r
 #define MSR_PENTIUM_M_LER_TO_LIP                 0x000001DD\r
 \r
@@ -523,6 +541,7 @@ typedef union {
 \r
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP);\r
   @endcode\r
+  @note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
 **/\r
 #define MSR_PENTIUM_M_LER_FROM_LIP               0x000001DE\r
 \r
@@ -541,6 +560,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL);\r
   AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr);\r
   @endcode\r
+  @note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
 **/\r
 #define MSR_PENTIUM_M_MC4_CTL                    0x0000040C\r
 \r
@@ -559,6 +579,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS);\r
   AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr);\r
   @endcode\r
+  @note MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
 **/\r
 #define MSR_PENTIUM_M_MC4_STATUS                 0x0000040D\r
 \r
@@ -580,6 +601,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR);\r
   AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr);\r
   @endcode\r
+  @note MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
 **/\r
 #define MSR_PENTIUM_M_MC4_ADDR                   0x0000040E\r
 \r
@@ -598,6 +620,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL);\r
   AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr);\r
   @endcode\r
+  @note MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM.\r
 **/\r
 #define MSR_PENTIUM_M_MC3_CTL                    0x00000410\r
 \r
@@ -616,6 +639,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS);\r
   AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr);\r
   @endcode\r
+  @note MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.\r
 **/\r
 #define MSR_PENTIUM_M_MC3_STATUS                 0x00000411\r
 \r
@@ -637,6 +661,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR);\r
   AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr);\r
   @endcode\r
+  @note MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
 **/\r
 #define MSR_PENTIUM_M_MC3_ADDR                   0x00000412\r
 \r