Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);\r
AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r
**/\r
#define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);\r
AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r
**/\r
#define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);\r
AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);\r
@endcode\r
+ @note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
**/\r
#define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);\r
AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.\r
+ MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.\r
+ MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.\r
+ MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.\r
+ MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.\r
+ MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.\r
+ MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.\r
+ MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.\r
@{\r
**/\r
#define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040\r
Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL);\r
AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.\r
**/\r
#define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3);\r
AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64);\r
@endcode\r
+ @note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
**/\r
#define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL);\r
AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64);\r
@endcode\r
+ @note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
**/\r
#define MSR_PENTIUM_M_THERM2_CTL 0x0000019D\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE);\r
AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64);\r
@endcode\r
+ @note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
#define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS);\r
AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
#define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB);\r
AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.\r
**/\r
#define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9\r
\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP);\r
@endcode\r
+ @note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
#define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD\r
\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP);\r
@endcode\r
+ @note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
#define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL);\r
AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
**/\r
#define MSR_PENTIUM_M_MC4_CTL 0x0000040C\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS);\r
AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
**/\r
#define MSR_PENTIUM_M_MC4_STATUS 0x0000040D\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR);\r
AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
**/\r
#define MSR_PENTIUM_M_MC4_ADDR 0x0000040E\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL);\r
AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM.\r
**/\r
#define MSR_PENTIUM_M_MC3_CTL 0x00000410\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS);\r
AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.\r
**/\r
#define MSR_PENTIUM_M_MC3_STATUS 0x00000411\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR);\r
AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
**/\r
#define MSR_PENTIUM_M_MC3_ADDR 0x00000412\r
\r