The expression that was used to set it had no side effects.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Kelly Steele <kelly.steele@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
MRCParams_t *mrc_params)\r
{\r
uint8_t TCL, WL;\r
MRCParams_t *mrc_params)\r
{\r
uint8_t TCL, WL;\r
- uint8_t TRP, TRCD, TRAS, TRFC, TWR, TWTR, TRRD, TRTP, TFAW;\r
+ uint8_t TRP, TRCD, TRAS, TWR, TWTR, TRRD, TRTP, TFAW;\r
uint32_t TCK;\r
\r
RegDTR0 Dtr0;\r
uint32_t TCK;\r
\r
RegDTR0 Dtr0;\r
TRP = TCL; // Per CAT MRC\r
TRCD = TCL; // Per CAT MRC\r
TRAS = MCEIL(mrc_params->params.tRAS, TCK);\r
TRP = TCL; // Per CAT MRC\r
TRCD = TCL; // Per CAT MRC\r
TRAS = MCEIL(mrc_params->params.tRAS, TCK);\r
- TRFC = MCEIL(tRFC[mrc_params->params.DENSITY], TCK);\r
TWR = MCEIL(15000, TCK); // Per JEDEC: tWR=15000ps DDR2/3 from 800-1600\r
\r
TWTR = MCEIL(mrc_params->params.tWTR, TCK);\r
TWR = MCEIL(15000, TCK); // Per JEDEC: tWR=15000ps DDR2/3 from 800-1600\r
\r
TWTR = MCEIL(mrc_params->params.tWTR, TCK);\r