//\r
// address purpose size\r
// ------------ -------- -------------------------\r
- // max(top, 2g) PCI MMIO 0xFEC00000 - max(top, 2g)\r
+ // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
+ // 0xFC000000 gap 44 MB\r
// 0xFEC00000 IO-APIC 4 KB\r
// 0xFEC01000 gap 1020 KB\r
// 0xFED00000 HPET 1 KB\r
// 0xFED00400 gap 1023 KB\r
// 0xFEE00000 LAPIC 1 MB\r
//\r
- AddIoMemoryRangeHob (TopOfMemory < BASE_2GB ? BASE_2GB : TopOfMemory, 0xFEC00000);\r
+ AddIoMemoryRangeHob (TopOfMemory < BASE_2GB ? BASE_2GB : TopOfMemory, 0xFC000000);\r
AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r