/** @file\r
- Copyright (c) 2006, Intel Corporation \r
- All rights reserved. This program and the accompanying materials \r
- are licensed and made available under the terms and conditions of the BSD License \r
- which accompanies this distribution. The full text of the license may be found at \r
- http://opensource.org/licenses/bsd-license.php \r
+ Copyright (c) 2006, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
{ OP_WRITE_10, DataOut },\r
{ OP_WRITE_12, DataOut },\r
{ OP_WRITE_AND_VERIFY, DataOut },\r
- { 0xff, (DATA_DIRECTION) 0xff } \r
+ { 0xff, (DATA_DIRECTION) 0xff }\r
};\r
\r
static CHAR16 *gControllerNameString = (CHAR16 *) L"ATAPI Controller";\r
)\r
{\r
EFI_STATUS Status;\r
- EFI_STATUS DisableStatus;\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
UINT64 Supports;\r
+ UINT64 OriginalPciAttributes;\r
\r
PciIo = NULL;\r
Status = gBS->OpenProtocol (\r
return Status;\r
}\r
\r
+ //\r
+ // Save original PCI attributes\r
+ //\r
+ Status = PciIo->Attributes (\r
+ PciIo,\r
+ EfiPciIoAttributeOperationGet,\r
+ 0,\r
+ &OriginalPciAttributes\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
Status = PciIo->Attributes (\r
PciIo,\r
EfiPciIoAttributeOperationSupported,\r
//\r
// Create SCSI Pass Thru instance for the IDE channel.\r
//\r
- Status = RegisterAtapiScsiPassThru (This, Controller, PciIo);\r
+ Status = RegisterAtapiScsiPassThru (This, Controller, PciIo, OriginalPciAttributes);\r
\r
Done:\r
if (EFI_ERROR (Status)) {\r
- if (PciIo) {\r
- DisableStatus = PciIo->Attributes (\r
- PciIo,\r
- EfiPciIoAttributeOperationSupported,\r
- 0,\r
- &Supports\r
- );\r
- if (!EFI_ERROR (DisableStatus)) {\r
- Supports &= (EFI_PCI_DEVICE_ENABLE |\r
- EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO |\r
- EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO);\r
- DisableStatus = PciIo->Attributes (\r
- PciIo,\r
- EfiPciIoAttributeOperationDisable,\r
- Supports,\r
- NULL\r
- );\r
- }\r
- }\r
+ //\r
+ // Restore original PCI attributes\r
+ //\r
+ PciIo->Attributes (\r
+ PciIo,\r
+ EfiPciIoAttributeOperationSet,\r
+ OriginalPciAttributes,\r
+ NULL\r
+ );\r
\r
gBS->CloseProtocol (\r
Controller,\r
EFI_STATUS Status;\r
EFI_SCSI_PASS_THRU_PROTOCOL *ScsiPassThru;\r
ATAPI_SCSI_PASS_THRU_DEV *AtapiScsiPrivate;\r
- UINT64 Supports;\r
\r
Status = gBS->OpenProtocol (\r
Controller,\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
- // Release Pci Io protocol on the controller handle.\r
+ // Restore original PCI attributes\r
//\r
- Status = AtapiScsiPrivate->PciIo->Attributes (\r
- AtapiScsiPrivate->PciIo,\r
- EfiPciIoAttributeOperationSupported,\r
- 0,\r
- &Supports\r
- );\r
- if (!EFI_ERROR (Status)) {\r
- Supports &= (EFI_PCI_DEVICE_ENABLE |\r
- EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO |\r
- EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO);\r
- Status = AtapiScsiPrivate->PciIo->Attributes (\r
- AtapiScsiPrivate->PciIo,\r
- EfiPciIoAttributeOperationDisable,\r
- Supports,\r
- NULL\r
- );\r
- }\r
+ AtapiScsiPrivate->PciIo->Attributes (\r
+ AtapiScsiPrivate->PciIo,\r
+ EfiPciIoAttributeOperationSet,\r
+ AtapiScsiPrivate->OriginalPciAttributes,\r
+ NULL\r
+ );\r
\r
gBS->CloseProtocol (\r
Controller,\r
/**\r
Attaches SCSI Pass Thru Protocol for specified IDE channel.\r
\r
- @param Controller: Parent device handle to the IDE channel.\r
- @param PciIo: PCI I/O protocol attached on the "Controller".\r
+ @param Controller: Parent device handle to the IDE channel.\r
+ @param PciIo: PCI I/O protocol attached on the "Controller".\r
+ @param OriginalPciAttributes Original PCI attributes\r
+\r
\r
@return EFI_SUCCESS Always returned unless installing SCSI Pass Thru Protocol failed.\r
\r
RegisterAtapiScsiPassThru (\r
IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
IN EFI_HANDLE Controller,\r
- IN EFI_PCI_IO_PROTOCOL *PciIo\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT64 OriginalPciAttributes\r
)\r
{\r
EFI_STATUS Status;\r
ATAPI_SCSI_PASS_THRU_DEV *AtapiScsiPrivate;\r
- UINT64 Supports;\r
IDE_REGISTERS_BASE_ADDR IdeRegsBaseAddr[ATAPI_MAX_CHANNEL];\r
\r
AtapiScsiPrivate = AllocateZeroPool (sizeof (ATAPI_SCSI_PASS_THRU_DEV));\r
\r
CopyMem (AtapiScsiPrivate->ChannelName, gAtapiChannelString, sizeof (gAtapiChannelString));\r
\r
- //\r
- // Enable channel\r
- //\r
- Status = PciIo->Attributes (\r
- PciIo,\r
- EfiPciIoAttributeOperationSupported,\r
- 0,\r
- &Supports\r
- );\r
- if (!EFI_ERROR (Status)) {\r
- Supports &= (EFI_PCI_DEVICE_ENABLE |\r
- EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO |\r
- EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO);\r
- Status = PciIo->Attributes (\r
- PciIo,\r
- EfiPciIoAttributeOperationEnable,\r
- Supports,\r
- NULL\r
- );\r
- }\r
-\r
AtapiScsiPrivate->Signature = ATAPI_SCSI_PASS_THRU_DEV_SIGNATURE;\r
AtapiScsiPrivate->Handle = Controller;\r
\r
//\r
// will reset the IoPort inside each API function.\r
//\r
- AtapiScsiPrivate->IoPort = NULL;\r
- AtapiScsiPrivate->PciIo = PciIo;\r
+ AtapiScsiPrivate->IoPort = NULL;\r
+ AtapiScsiPrivate->PciIo = PciIo;\r
+ AtapiScsiPrivate->OriginalPciAttributes = OriginalPciAttributes;\r
\r
//\r
// Obtain IDE IO port registers' base addresses\r
//\r
// non-RAID SCSI controllers should set both physical and logical attributes\r
//\r
- AtapiScsiPrivate->ScsiPassThruMode.Attributes = EFI_SCSI_PASS_THRU_ATTRIBUTES_PHYSICAL | \r
+ AtapiScsiPrivate->ScsiPassThruMode.Attributes = EFI_SCSI_PASS_THRU_ATTRIBUTES_PHYSICAL |\r
EFI_SCSI_PASS_THRU_ATTRIBUTES_LOGICAL;\r
AtapiScsiPrivate->ScsiPassThruMode.IoAlign = 0;\r
\r
if ((Target > MAX_TARGET_ID) || (Lun != 0)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
- \r
+\r
//\r
// check the data fields in Packet parameter.\r
//\r
Packet->TransferLength = 0;\r
return EFI_SUCCESS;\r
}\r
- \r
+\r
//\r
// According to Target ID, reset the Atapi I/O Register mapping\r
// (Target Id in [0,1] area, using AtapiIoPortRegisters[0],\r
Target = Target % 2;\r
AtapiScsiPrivate->IoPort = &AtapiScsiPrivate->AtapiIoPortRegisters[1];\r
}\r
- \r
+\r
//\r
// the ATAPI SCSI interface does not support non-blocking I/O\r
// ignore the Event parameter\r
}\r
\r
/**\r
- Used to retrieve the list of legal Target IDs for SCSI devices \r
+ Used to retrieve the list of legal Target IDs for SCSI devices\r
on a SCSI channel.\r
\r
@param This Protocol instance pointer.\r
}\r
\r
/**\r
- Used to allocate and build a device path node for a SCSI device \r
+ Used to allocate and build a device path node for a SCSI device\r
on a SCSI channel. Would not build device path for a SCSI Host Controller.\r
\r
@param This Protocol instance pointer.\r
//\r
// Validate parameters passed in.\r
//\r
- \r
+\r
if (DevicePath == NULL) {\r
return EFI_INVALID_PARAMETER;\r
}\r
- \r
+\r
//\r
// can not build device path for the SCSI Host Controller.\r
//\r
if (DevicePath == NULL || Target == NULL || Lun == NULL) {\r
return EFI_INVALID_PARAMETER;\r
}\r
- \r
+\r
//\r
// Check whether the DevicePath belongs to SCSI_DEVICE_PATH\r
//\r
}\r
\r
/**\r
- Resets a SCSI channel.This operation resets all the \r
+ Resets a SCSI channel.This operation resets all the\r
SCSI devices connected to the SCSI channel.\r
\r
@param This Protocol instance pointer.\r
// 0xfb:1111,1011\r
//\r
DeviceControlValue &= 0xfb;\r
- \r
+\r
WritePortB (AtapiScsiPrivate->PciIo, AtapiScsiPrivate->IoPort->Alt.DeviceControl, DeviceControlValue);\r
\r
//\r
if (ResetFlag) {\r
return EFI_SUCCESS;\r
}\r
- \r
+\r
return EFI_TIMEOUT;\r
}\r
\r
if (Target == This->Mode->AdapterId) {\r
return EFI_SUCCESS;\r
}\r
- \r
+\r
//\r
// According to Target ID, reset the Atapi I/O Register mapping\r
// (Target Id in [0,1] area, using AtapiIoPortRegisters[0],\r
} else {\r
AtapiScsiPrivate->IoPort = &AtapiScsiPrivate->AtapiIoPortRegisters[1];\r
}\r
- \r
+\r
//\r
// for ATAPI device, no need to wait DRDY ready after device selecting.\r
//\r
if (EFI_ERROR (StatusWaitForBSYClear (AtapiScsiPrivate, 31000000))) {\r
return EFI_TIMEOUT;\r
}\r
- \r
+\r
//\r
// stall 5 seconds to make the device status stable\r
//\r
\r
Arguments:\r
PciIo - Pointer to the EFI_PCI_IO_PROTOCOL instance\r
- IdeRegsBaseAddr - Pointer to IDE_REGISTERS_BASE_ADDR to \r
+ IdeRegsBaseAddr - Pointer to IDE_REGISTERS_BASE_ADDR to\r
receive IDE IO port registers' base addresses\r
- \r
+\r
Returns:\r
\r
EFI_STATUS\r
- \r
+\r
--*/\r
{\r
EFI_STATUS Status;\r
//\r
// The BARs should be of IO type\r
//\r
- if ((PciData.Device.Bar[0] & BIT0) == 0 || \r
+ if ((PciData.Device.Bar[0] & BIT0) == 0 ||\r
(PciData.Device.Bar[1] & BIT0) == 0) {\r
return EFI_UNSUPPORTED;\r
}\r
Initialize each Channel's Base Address of CommandBlock and ControlBlock.\r
\r
Arguments:\r
- \r
+\r
AtapiScsiPrivate - The pointer of ATAPI_SCSI_PASS_THRU_DEV\r
IdeRegsBaseAddr - The pointer of IDE_REGISTERS_BASE_ADDR\r
- \r
+\r
Returns:\r
- \r
+\r
None\r
\r
---*/ \r
+--*/\r
{\r
- \r
+\r
UINT8 IdeChannel;\r
UINT16 CommandBlockBaseAddr;\r
UINT16 ControlBlockBaseAddr;\r
IDE_BASE_REGISTERS *RegisterPointer;\r
\r
- \r
+\r
for (IdeChannel = 0; IdeChannel < ATAPI_MAX_CHANNEL; IdeChannel++) {\r
\r
RegisterPointer = &AtapiScsiPrivate->AtapiIoPortRegisters[IdeChannel];\r
//\r
CommandBlockBaseAddr = IdeRegsBaseAddr[IdeChannel].CommandBlockBaseAddr;\r
ControlBlockBaseAddr = IdeRegsBaseAddr[IdeChannel].ControlBlockBaseAddr;\r
- \r
+\r
RegisterPointer->Data = CommandBlockBaseAddr;\r
(*(UINT16 *) &RegisterPointer->Reg1) = (UINT16) (CommandBlockBaseAddr + 0x01);\r
RegisterPointer->SectorCount = (UINT16) (CommandBlockBaseAddr + 0x02);\r
RegisterPointer->CylinderMsb = (UINT16) (CommandBlockBaseAddr + 0x05);\r
RegisterPointer->Head = (UINT16) (CommandBlockBaseAddr + 0x06);\r
(*(UINT16 *) &RegisterPointer->Reg) = (UINT16) (CommandBlockBaseAddr + 0x07);\r
- \r
+\r
(*(UINT16 *) &RegisterPointer->Alt) = ControlBlockBaseAddr;\r
RegisterPointer->DriveAddress = (UINT16) (ControlBlockBaseAddr + 0x01);\r
}\r
\r
}\r
\r
- \r
+\r
EFI_STATUS\r
CheckSCSIRequestPacket (\r
EFI_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet\r
\r
Arguments:\r
\r
- Packet - The pointer of EFI_SCSI_PASS_THRU_SCSI_REQUEST_PACKET \r
+ Packet - The pointer of EFI_SCSI_PASS_THRU_SCSI_REQUEST_PACKET\r
\r
Returns:\r
\r
if (Packet->Cdb == NULL) {\r
return EFI_INVALID_PARAMETER;\r
}\r
- \r
+\r
//\r
// Checks whether the request command is supported.\r
//\r
}\r
\r
/**\r
- Checks the requested SCSI command: \r
+ Checks the requested SCSI command:\r
Is it supported by this driver?\r
Is the Data transfer direction reasonable?\r
\r
Packet->SenseDataLength = 0;\r
return PacketCommandStatus;\r
}\r
- \r
+\r
//\r
// Check if SenseData meets the alignment requirement.\r
//\r
}\r
}\r
\r
- \r
+\r
//\r
// Return SenseData if PacketCommandStatus matches\r
// the following return codes.\r
if ((PacketCommandStatus == EFI_BAD_BUFFER_SIZE) ||\r
(PacketCommandStatus == EFI_DEVICE_ERROR) ||\r
(PacketCommandStatus == EFI_TIMEOUT)) {\r
- \r
+\r
//\r
// avoid submit request sense command continuously.\r
//\r
/**\r
Check whether DRQ is clear in the Status Register. (BSY must also be cleared)\r
If TimeoutInMicroSeconds is zero, this routine should wait infinitely for\r
- DRQ clear. Otherwise, it will return EFI_TIMEOUT when specified time is \r
+ DRQ clear. Otherwise, it will return EFI_TIMEOUT when specified time is\r
elapsed.\r
\r
@todo function comment is missing 'Routine Description:'\r
}\r
\r
/**\r
- Check whether DRQ is clear in the Alternate Status Register. \r
+ Check whether DRQ is clear in the Alternate Status Register.\r
(BSY must also be cleared).\r
If TimeoutInMicroSeconds is zero, this routine should wait infinitely for\r
- DRQ clear. Otherwise, it will return EFI_TIMEOUT when specified time is \r
+ DRQ clear. Otherwise, it will return EFI_TIMEOUT when specified time is\r
elapsed.\r
\r
@todo function comment is missing 'Routine Description:'\r
/**\r
Check whether DRQ is ready in the Status Register. (BSY must also be cleared)\r
If TimeoutInMicroSeconds is zero, this routine should wait infinitely for\r
- DRQ ready. Otherwise, it will return EFI_TIMEOUT when specified time is \r
+ DRQ ready. Otherwise, it will return EFI_TIMEOUT when specified time is\r
elapsed.\r
\r
@todo function comment is missing 'Routine Description:'\r
}\r
\r
/**\r
- Check whether DRQ is ready in the Alternate Status Register. \r
+ Check whether DRQ is ready in the Alternate Status Register.\r
(BSY must also be cleared)\r
If TimeoutInMicroSeconds is zero, this routine should wait infinitely for\r
- DRQ ready. Otherwise, it will return EFI_TIMEOUT when specified time is \r
+ DRQ ready. Otherwise, it will return EFI_TIMEOUT when specified time is\r
elapsed.\r
\r
@todo function comment is missing 'Routine Description:'\r
/**\r
Check whether BSY is clear in the Status Register.\r
If TimeoutInMicroSeconds is zero, this routine should wait infinitely for\r
- BSY clear. Otherwise, it will return EFI_TIMEOUT when specified time is \r
+ BSY clear. Otherwise, it will return EFI_TIMEOUT when specified time is\r
elapsed.\r
\r
@todo function comment is missing 'Routine Description:'\r
/**\r
Check whether BSY is clear in the Alternate Status Register.\r
If TimeoutInMicroSeconds is zero, this routine should wait infinitely for\r
- BSY clear. Otherwise, it will return EFI_TIMEOUT when specified time is \r
+ BSY clear. Otherwise, it will return EFI_TIMEOUT when specified time is\r
elapsed.\r
\r
@todo function comment is missing 'Routine Description:'\r
}\r
\r
/**\r
- Check whether DRDY is ready in the Status Register. \r
+ Check whether DRDY is ready in the Status Register.\r
(BSY must also be cleared)\r
If TimeoutInMicroSeconds is zero, this routine should wait infinitely for\r
- DRDY ready. Otherwise, it will return EFI_TIMEOUT when specified time is \r
+ DRDY ready. Otherwise, it will return EFI_TIMEOUT when specified time is\r
elapsed.\r
\r
@todo function comment is missing 'Routine Description:'\r
return EFI_ABORTED;\r
}\r
}\r
- \r
+\r
//\r
// Stall for 30 us\r
//\r
}\r
\r
/**\r
- Check whether DRDY is ready in the Alternate Status Register. \r
+ Check whether DRDY is ready in the Alternate Status Register.\r
(BSY must also be cleared)\r
If TimeoutInMicroSeconds is zero, this routine should wait infinitely for\r
- DRDY ready. Otherwise, it will return EFI_TIMEOUT when specified time is \r
+ DRDY ready. Otherwise, it will return EFI_TIMEOUT when specified time is\r
elapsed.\r
\r
@todo function comment is missing 'Routine Description:'\r
}\r
\r
/**\r
- Check Error Register for Error Information. \r
+ Check Error Register for Error Information.\r
\r
@todo function comment is missing 'Routine Description:'\r
@todo function comment is missing 'Arguments:'\r
AtapiScsiPrivate->PciIo,\r
AtapiScsiPrivate->IoPort->Reg.Status\r
);\r
- \r
+\r
DEBUG_CODE_BEGIN ();\r
\r
if (StatusRegister & DWF) {\r
\r
if (StatusRegister & ERR) {\r
ErrorRegister = ReadPortB (AtapiScsiPrivate->PciIo, AtapiScsiPrivate->IoPort->Reg1.Error);\r
- \r
+\r
\r
if (ErrorRegister & BBK_ERR) {\r
DEBUG (\r
return EFI_SUCCESS;\r
}\r
\r
- \r
+\r
return EFI_DEVICE_ERROR;\r
}\r
\r
/**\r
The user Entry Point for module AtapiPassThru. The user code starts with this function.\r
\r
- @param[in] ImageHandle The firmware allocated handle for the EFI image. \r
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.\r
@param[in] SystemTable A pointer to the EFI System Table.\r
- \r
+\r
@retval EFI_SUCCESS The entry point is executed successfully.\r
@retval other Some error occurs when executing this entry point.\r
\r
/** @file\r
- Copyright (c) 2006, Intel Corporation \r
- All rights reserved. This program and the accompanying materials \r
- are licensed and made available under the terms and conditions of the BSD License \r
- which accompanies this distribution. The full text of the license may be found at \r
- http://opensource.org/licenses/bsd-license.php \r
+ Copyright (c) 2006, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
Module Name: AtapiPassThru.h\r
\r
EFI_SCSI_PASS_THRU_PROTOCOL ScsiPassThru;\r
EFI_SCSI_PASS_THRU_MODE ScsiPassThruMode;\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
+ UINT64 OriginalPciAttributes;\r
//\r
// Local Data goes here\r
//\r
@param This\r
@param Controller\r
@param PciIo\r
+ @param OriginalPciAttributes\r
\r
@todo Add function description\r
@todo This add argument description\r
**/\r
EFI_STATUS\r
RegisterAtapiScsiPassThru (\r
- IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
IN EFI_HANDLE Controller,\r
- IN EFI_PCI_IO_PROTOCOL *PciIo\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT64 OriginalPciAttributes\r
)\r
;\r
\r
\r
Arguments:\r
PciIo - Pointer to the EFI_PCI_IO_PROTOCOL instance\r
- IdeRegsBaseAddr - Pointer to IDE_REGISTERS_BASE_ADDR to \r
+ IdeRegsBaseAddr - Pointer to IDE_REGISTERS_BASE_ADDR to\r
receive IDE IO port registers' base addresses\r
- \r
+\r
Returns:\r
\r
EFI_STATUS\r
- \r
+\r
--*/\r
;\r
\r
Initialize each Channel's Base Address of CommandBlock and ControlBlock.\r
\r
Arguments:\r
- \r
+\r
AtapiScsiPrivate - The pointer of ATAPI_SCSI_PASS_THRU_DEV\r
IdeRegsBaseAddr - The pointer of IDE_REGISTERS_BASE_ADDR\r
- \r
+\r
Returns:\r
- \r
+\r
None\r
\r
---*/ \r
+--*/\r
;\r
\r
#endif\r
goto ON_EXIT;\r
}\r
}\r
- \r
+\r
//\r
// Clean up the asynchronous transfers, currently only\r
// interrupt supports asynchronous operation.\r
\r
//\r
// Software must not write a one to this field unless the host controller\r
- // is in the Halted state. Doing so will yield undefined results. \r
+ // is in the Halted state. Doing so will yield undefined results.\r
// refers to Spec[EHCI1.0-2.3.1]\r
- // \r
+ //\r
if (!EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT)) {\r
Status = EFI_DEVICE_ERROR;\r
break;\r
break;\r
}\r
}\r
- \r
+\r
//\r
// Set one to PortReset bit must also set zero to PortEnable bit\r
//\r
/**\r
Create and initialize a USB2_HC_DEV\r
\r
- @param PciIo The PciIo on this device\r
+ @param PciIo The PciIo on this device\r
+ @param OriginalPciAttributes Original PCI attributes\r
\r
@return The allocated and initialized USB2_HC_DEV structure\r
@return if created, otherwise NULL.\r
STATIC\r
USB2_HC_DEV *\r
EhcCreateUsb2Hc (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT64 OriginalPciAttributes\r
)\r
{\r
USB2_HC_DEV *Ehc;\r
Ehc->Usb2Hc.MajorRevision = 0x1;\r
Ehc->Usb2Hc.MinorRevision = 0x1;\r
\r
- Ehc->PciIo = PciIo;\r
+ Ehc->PciIo = PciIo;\r
+ Ehc->OriginalPciAttributes = OriginalPciAttributes;\r
\r
InitializeListHead (&Ehc->AsyncIntTransfers);\r
\r
USB2_HC_DEV *Ehc;\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
UINT64 Supports;\r
+ UINT64 OriginalPciAttributes;\r
\r
//\r
// Open the PciIo Protocol, then enable the USB host controller\r
return EFI_DEVICE_ERROR;\r
}\r
\r
+ //\r
+ // Save original PCI attributes\r
+ //\r
+ Status = PciIo->Attributes (\r
+ PciIo,\r
+ EfiPciIoAttributeOperationGet,\r
+ 0,\r
+ &OriginalPciAttributes\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
Status = PciIo->Attributes (\r
PciIo,\r
EfiPciIoAttributeOperationSupported,\r
//\r
// Create then install USB2_HC_PROTOCOL\r
//\r
- Ehc = EhcCreateUsb2Hc (PciIo);\r
+ Ehc = EhcCreateUsb2Hc (PciIo, OriginalPciAttributes);\r
\r
if (Ehc == NULL) {\r
EHC_ERROR (("EhcDriverBindingStart: failed to create USB2_HC\n"));\r
gBS->FreePool (Ehc);\r
\r
CLOSE_PCIIO:\r
+ //\r
+ // Restore original PCI attributes\r
+ //\r
+ PciIo->Attributes (\r
+ PciIo,\r
+ EfiPciIoAttributeOperationSet,\r
+ OriginalPciAttributes,\r
+ NULL\r
+ );\r
+\r
gBS->CloseProtocol (\r
Controller,\r
&gEfiPciIoProtocolGuid,\r
EFI_USB2_HC_PROTOCOL *Usb2Hc;\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
USB2_HC_DEV *Ehc;\r
- UINT64 Supports;\r
\r
//\r
// Test whether the Controller handler passed in is a valid\r
}\r
\r
//\r
- // Disable the USB Host Controller\r
+ // Restore original PCI attributes\r
//\r
- Status = PciIo->Attributes (\r
- PciIo,\r
- EfiPciIoAttributeOperationSupported,\r
- 0,\r
- &Supports\r
- );\r
- if (!EFI_ERROR (Status)) {\r
- Supports &= EFI_PCI_DEVICE_ENABLE;\r
- Status = PciIo->Attributes (\r
- PciIo,\r
- EfiPciIoAttributeOperationDisable,\r
- Supports,\r
- NULL\r
- );\r
- }\r
+ PciIo->Attributes (\r
+ PciIo,\r
+ EfiPciIoAttributeOperationSet,\r
+ Ehc->OriginalPciAttributes,\r
+ NULL\r
+ );\r
\r
gBS->CloseProtocol (\r
Controller,\r
Controller\r
);\r
\r
- gBS->FreePool (Ehc);\r
+ FreePool (Ehc);\r
+\r
return EFI_SUCCESS;\r
}\r
\r
EHC_ROOT_PORT_RECOVERY_STALL = 20 * EHC_1_MILLISECOND,\r
\r
//\r
- // Sync and Async transfer polling interval, set by experience, \r
+ // Sync and Async transfer polling interval, set by experience,\r
// and the unit of Async is 100us, means 50ms as interval.\r
//\r
EHC_SYNC_POLL_INTERVAL = 20 * EHC_1_MICROSECOND,\r
- EHC_ASYNC_POLL_INTERVAL = 50 * 10000U, \r
+ EHC_ASYNC_POLL_INTERVAL = 50 * 10000U,\r
\r
//\r
// EHC raises TPL to TPL_NOTIFY to serialize all its operations\r
EFI_USB2_HC_PROTOCOL Usb2Hc;\r
\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
+ UINT64 OriginalPciAttributes;\r
USBHC_MEM_POOL *MemPool;\r
\r
//\r
default:\r
goto ON_INVAILD_PARAMETER;\r
}\r
- \r
+\r
//\r
// Delete all old transactions on the USB bus, then\r
// reinitialize the frame list\r
UhciInitFrameList (Uhc);\r
\r
gBS->RestoreTPL (OldTpl);\r
- \r
+\r
return EFI_SUCCESS;\r
\r
ON_INVAILD_PARAMETER:\r
- \r
+\r
gBS->RestoreTPL (OldTpl);\r
- \r
+\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
UsbCmd |= USBCMD_FGR;\r
UhciWriteReg (Uhc->PciIo, USBCMD_OFFSET, UsbCmd);\r
}\r
- \r
+\r
//\r
// wait 20ms to let resume complete (20ms is specified by UHCI spec)\r
//\r
Status = EFI_DEVICE_ERROR;\r
goto ON_EXIT;\r
}\r
- \r
+\r
//\r
// Set Enter Global Suspend Mode bit to 1.\r
//\r
STATIC\r
USB_HC_DEV *\r
UhciAllocateDev (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT64 OriginalPciAttributes\r
)\r
{\r
USB_HC_DEV *Uhc;\r
Uhc->Usb2Hc.MajorRevision = 0x1;\r
Uhc->Usb2Hc.MinorRevision = 0x1;\r
\r
- Uhc->PciIo = PciIo;\r
- Uhc->MemPool = UsbHcInitMemPool (PciIo, TRUE, 0);\r
+ Uhc->PciIo = PciIo;\r
+ Uhc->OriginalPciAttributes = OriginalPciAttributes;\r
+ Uhc->MemPool = UsbHcInitMemPool (PciIo, TRUE, 0);\r
\r
if (Uhc->MemPool == NULL) {\r
Status = EFI_OUT_OF_RESOURCES;\r
)\r
{\r
USB_HC_DEV *Uhc;\r
- UINT64 Supports;\r
\r
//\r
// Uninstall the USB_HC and USB_HC2 protocol, then disable the controller\r
\r
UhciFreeAllAsyncReq (Uhc);\r
UhciDestoryFrameList (Uhc);\r
- \r
- Uhc->PciIo->Attributes (\r
- Uhc->PciIo,\r
- EfiPciIoAttributeOperationSupported,\r
- 0,\r
- &Supports\r
- );\r
- Supports &= EFI_PCI_DEVICE_ENABLE;\r
+\r
+ //\r
+ // Restore original PCI attributes\r
+ //\r
Uhc->PciIo->Attributes (\r
- Uhc->PciIo,\r
- EfiPciIoAttributeOperationDisable,\r
- Supports,\r
- NULL\r
- );\r
+ Uhc->PciIo,\r
+ EfiPciIoAttributeOperationSet,\r
+ Uhc->OriginalPciAttributes,\r
+ NULL\r
+ );\r
\r
UhciFreeDev (Uhc);\r
}\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
USB_HC_DEV *Uhc;\r
UINT64 Supports;\r
+ UINT64 OriginalPciAttributes;\r
\r
//\r
// Open PCIIO, then enable the EHC device and turn off emulation\r
return Status;\r
}\r
\r
+ //\r
+ // Save original PCI attributes\r
+ //\r
+ Status = PciIo->Attributes (\r
+ PciIo,\r
+ EfiPciIoAttributeOperationGet,\r
+ 0,\r
+ &OriginalPciAttributes\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
UhciTurnOffUsbEmulation (PciIo);\r
\r
Status = PciIo->Attributes (\r
goto CLOSE_PCIIO;\r
}\r
\r
- Uhc = UhciAllocateDev (PciIo);\r
+ Uhc = UhciAllocateDev (PciIo, OriginalPciAttributes);\r
\r
if (Uhc == NULL) {\r
Status = EFI_OUT_OF_RESOURCES;\r
UhciFreeDev (Uhc);\r
\r
CLOSE_PCIIO:\r
+ //\r
+ // Restore original PCI attributes\r
+ //\r
+ PciIo->Attributes (\r
+ PciIo,\r
+ EfiPciIoAttributeOperationSet,\r
+ OriginalPciAttributes,\r
+ NULL\r
+ );\r
+\r
gBS->CloseProtocol (\r
Controller,\r
&gEfiPciIoProtocolGuid,\r
// UHCI register operation timeout, set by experience\r
//\r
UHC_GENERIC_TIMEOUT = UHC_1_SECOND,\r
- \r
+\r
//\r
// Wait for force global resume(FGR) complete, refers to\r
// specification[UHCI11-2.1.1]\r
- // \r
+ //\r
UHC_FORCE_GLOBAL_RESUME_STALL = 20 * UHC_1_MILLISECOND,\r
\r
//\r
// Wait for roothub port reset and recovery, reset stall\r
- // is set by experience, and recovery stall refers to \r
+ // is set by experience, and recovery stall refers to\r
// specification[UHCI11-2.1.1]\r
//\r
UHC_ROOT_PORT_RESET_STALL = 50 * UHC_1_MILLISECOND,\r
UHC_ROOT_PORT_RECOVERY_STALL = 10 * UHC_1_MILLISECOND,\r
\r
//\r
- // Sync and Async transfer polling interval, set by experience, \r
+ // Sync and Async transfer polling interval, set by experience,\r
// and the unit of Async is 100us.\r
//\r
UHC_SYNC_POLL_INTERVAL = 50 * UHC_1_MICROSECOND,\r
UHC_ASYNC_POLL_INTERVAL = 50 * 10000UL,\r
- \r
+\r
//\r
// UHC raises TPL to TPL_NOTIFY to serialize all its operations\r
// to protect shared data structures.\r
EFI_USB_HC_PROTOCOL UsbHc;\r
EFI_USB2_HC_PROTOCOL Usb2Hc;\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
+ UINT64 OriginalPciAttributes;\r
\r
//\r
// Schedule data structures\r
/*++\r
\r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
Module Name:\r
\r
\r
//-------------------------------------------------------------------------\r
// Offsets to the various registers.\r
-// All accesses need not be longword aligned. \r
+// All accesses need not be longword aligned.\r
//-------------------------------------------------------------------------\r
enum speedo_offsets {\r
- SCBStatus = 0, SCBCmd = 2, // Rx/Command Unit command and status. \r
- SCBPointer = 4, // General purpose pointer. \r
- SCBPort = 8, // Misc. commands and operands. \r
- SCBflash = 12, SCBeeprom = 14, // EEPROM and flash memory control. \r
- SCBCtrlMDI = 16, // MDI interface control. \r
- SCBEarlyRx = 20, // Early receive byte count. \r
+ SCBStatus = 0, SCBCmd = 2, // Rx/Command Unit command and status.\r
+ SCBPointer = 4, // General purpose pointer.\r
+ SCBPort = 8, // Misc. commands and operands.\r
+ SCBflash = 12, SCBeeprom = 14, // EEPROM and flash memory control.\r
+ SCBCtrlMDI = 16, // MDI interface control.\r
+ SCBEarlyRx = 20, // Early receive byte count.\r
SCBEarlyRxInt = 24, SCBFlowCtrlReg = 25, SCBPmdr = 27,\r
// offsets for general control registers (GCRs)\r
SCBGenCtrl = 28, SCBGenStatus = 29, SCBGenCtrl2 = 30, SCBRsvd = 31\r
#define GCR2_EEPROM_ACCESS_SEMAPHORE 0x80 // bit offset into the gcr2\r
\r
//-------------------------------------------------------------------------\r
-// Action commands - Commands that can be put in a command list entry. \r
+// Action commands - Commands that can be put in a command list entry.\r
//-------------------------------------------------------------------------\r
enum commands {\r
CmdNOp = 0, CmdIASetup = 1, CmdConfigure = 2, CmdMulticastList = 3,\r
#define BIT_4_6 0x0070\r
#define BIT_4_7 0x00F0\r
#define BIT_5_7 0x00E0\r
-#define BIT_5_9 0x03E0 \r
+#define BIT_5_9 0x03E0\r
#define BIT_5_12 0x1FE0\r
#define BIT_5_15 0xFFE0\r
#define BIT_6_7 0x00c0\r
UINT64 Unique_ID;\r
\r
EFI_PCI_IO_PROTOCOL *Io_Function;\r
+ //\r
+ // Original PCI attributes\r
+ //\r
+ UINT64 OriginalPciAttributes;\r
\r
VOID (*Delay_30)(UINTN); // call back routine\r
VOID (*Virt2Phys_30)(UINT64 virtual_addr, UINT64 physical_ptr); // call back routine\r
/*++\r
\r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
Module Name:\r
\r
--*/\r
\r
#include "Undi32.h"\r
-\r
+#include <Library/BaseLib.h>\r
//\r
// Global Variables\r
//\r
PXE_SW_UNDI *pxe_31 = 0; // 3.1 entry\r
UNDI32_DEV *UNDI32DeviceList[MAX_NIC_INTERFACES];\r
\r
-NII_TABLE *UnidiDataPointer=NULL; \r
+NII_TABLE *UndiDataPointer = NULL;\r
\r
VOID\r
EFIAPI\r
\r
Routine Description:\r
\r
- When EFI is shuting down the boot services, we need to install a \r
+ When EFI is shuting down the boot services, we need to install a\r
configuration table for UNDI to work at runtime!\r
\r
Arguments:\r
Arguments:\r
\r
This - Protocol instance pointer.\r
- \r
+\r
Controller - Handle of device to test.\r
- \r
+\r
RemainingDevicePath - Not used.\r
\r
Returns:\r
\r
EFI_SUCCESS - This driver supports this device.\r
- \r
+\r
other - This driver does not support this device.\r
\r
--*/\r
Arguments:\r
\r
This - Protocol instance pointer.\r
- \r
+\r
Controller - Handle of device to work with.\r
- \r
+\r
RemainingDevicePath - Not used, always produce all possible children.\r
\r
Returns:\r
\r
EFI_SUCCESS - This driver is added to Controller.\r
- \r
+\r
other - This driver does not support this device.\r
\r
--*/\r
UINT16 NewCommand;\r
UINT8 *TmpPxePointer;\r
EFI_PCI_IO_PROTOCOL *PciIoFncs;\r
- UINTN Len; \r
+ UINTN Len;\r
UINT64 Supports;\r
\r
Status = gBS->OpenProtocol (\r
\r
ZeroMem ((CHAR8 *) UNDI32Device, sizeof (UNDI32_DEV));\r
\r
+ //\r
+ // Get original PCI attributes\r
+ //\r
+ Status = PciIoFncs->Attributes (\r
+ PciIoFncs,\r
+ EfiPciIoAttributeOperationGet,\r
+ 0,\r
+ &UNDI32Device->NicInfo.OriginalPciAttributes\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
//\r
// allocate and initialize both (old and new) the !pxe structures here,\r
// there should only be one copy of each of these structure for any number\r
}\r
\r
//\r
- // if the table exists, free it and alloc again, or alloc it directly \r
+ // if the table exists, free it and alloc again, or alloc it directly\r
//\r
- if (UnidiDataPointer != NULL) {\r
- Status = gBS->FreePool(UnidiDataPointer);\r
+ if (UndiDataPointer != NULL) {\r
+ Status = gBS->FreePool(UndiDataPointer);\r
}\r
if (EFI_ERROR (Status)) {\r
goto UndiErrorDeleteDevicePath;\r
}\r
\r
- Len = (pxe_31->IFcnt * sizeof (NII_ENTRY)) + sizeof (UnidiDataPointer);\r
- Status = gBS->AllocatePool (EfiRuntimeServicesData, Len, (VOID **) &UnidiDataPointer);\r
+ Len = (pxe_31->IFcnt * sizeof (NII_ENTRY)) + sizeof (UndiDataPointer);\r
+ Status = gBS->AllocatePool (EfiRuntimeServicesData, Len, (VOID **) &UndiDataPointer);\r
\r
if (EFI_ERROR (Status)) {\r
goto UndiErrorAllocDataPointer;\r
}\r
- \r
+\r
//\r
// Open For Child Device\r
//\r
}\r
\r
UndiErrorDeleteDevice:\r
+ //\r
+ // Restore original PCI attributes\r
+ //\r
+ PciIoFncs->Attributes (\r
+ PciIoFncs,\r
+ EfiPciIoAttributeOperationSet,\r
+ UNDI32Device->NicInfo.OriginalPciAttributes,\r
+ NULL\r
+ );\r
+\r
gBS->FreePool (UNDI32Device);\r
\r
UndiError:\r
\r
UNDI32Device = UNDI_DEV_FROM_THIS (NIIProtocol);\r
\r
+ //\r
+ // Restore original PCI attributes\r
+ //\r
+ Status = UNDI32Device->NicInfo.Io_Function->Attributes (\r
+ UNDI32Device->NicInfo.Io_Function,\r
+ EfiPciIoAttributeOperationSet,\r
+ UNDI32Device->NicInfo.OriginalPciAttributes,\r
+ NULL\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
Status = gBS->CloseProtocol (\r
Controller,\r
&gEfiPciIoProtocolGuid,\r
Arguments:\r
\r
UnqId - Runtime O/S routine might use this, this temp routine does not use it\r
- \r
+\r
MicroSeconds - Determines the length of pause.\r
\r
Returns:\r
Arguments:\r
\r
UnqId - Runtime O/S routine may use this field, this temp routine does not.\r
- \r
+\r
ReadWrite - Determine if it is an I/O or Memory Read/Write Operation.\r
- \r
+\r
Len - Determines the width of the data operation.\r
- \r
+\r
Port - What port to Read/Write from.\r
- \r
+\r
BuffAddr - Address to read to or write from.\r
\r
Returns:\r
Arguments:\r
\r
DevPtr - Pointer which will point to the newly created device path with the MAC node attached.\r
- \r
+\r
BaseDevPtr - Pointer to the device path which the UNDI device driver is latching on to.\r
- \r
+\r
AdapterInfo - Pointer to the NIC data structure information which the UNDI driver is layering on..\r
\r
Returns:\r
\r
EFI_SUCCESS - A MAC address was successfully appended to the Base Device Path.\r
- \r
+\r
other - Not enough resources available to create new Device Path node.\r
\r
--*/\r
Returns:\r
\r
EFI_SUCCESS - Install a GUID/Pointer pair into the system's configuration table.\r
- \r
+\r
other - Did not successfully install the GUID/Pointer pair into the configuration table.\r
\r
--*/\r
return EFI_SUCCESS;\r
}\r
\r
- if(UnidiDataPointer == NULL) { \r
+ if(UndiDataPointer == NULL) {\r
return EFI_SUCCESS;\r
}\r
- \r
- UndiData = (NII_TABLE *)UnidiDataPointer; \r
- \r
+\r
+ UndiData = (NII_TABLE *)UndiDataPointer;\r
+\r
UndiData->NumEntries = pxe_31->IFcnt;\r
UndiData->NextLink = NULL;\r
\r
}\r
\r
/**\r
- \r
+\r
Install driver binding protocol of UNDI.\r
- \r
- @param[in] ImageHandle The firmware allocated handle for the EFI image. \r
+\r
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.\r
@param[in] SystemTable A pointer to the EFI System Table.\r
- \r
+\r
@retval EFI_SUCCESS The entry point is executed successfully.\r
@retval other Some error occurs when executing this entry point.\r
\r
/*++\r
\r
Copyright (c) 2006, Intel Corporation.\r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
Module Name:\r
\r
VOID\r
MdiWrite (\r
IN NIC_DATA_INSTANCE *AdapterInfo,\r
- IN UINT8 RegAddress, \r
+ IN UINT8 RegAddress,\r
IN UINT8 PhyAddress,\r
IN UINT16 DataValue\r
);\r
VOID\r
MdiRead(\r
IN NIC_DATA_INSTANCE *AdapterInfo,\r
- IN UINT8 RegAddress, \r
+ IN UINT8 RegAddress,\r
IN UINT8 PhyAddress,\r
IN OUT UINT16 *DataValue\r
);\r
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