--- /dev/null
+/** @file\r
+ Library instance of PciHostBridgeLib library class for coreboot.\r
+\r
+ Copyright (C) 2016, Red Hat, Inc.\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials are licensed and made available\r
+ under the terms and conditions of the BSD License which accompanies this\r
+ distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+#include <PiDxe.h>\r
+\r
+#include <IndustryStandard/Pci.h>\r
+#include <Protocol/PciHostBridgeResourceAllocation.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/PciHostBridgeLib.h>\r
+#include <Library/PciLib.h>\r
+\r
+#include "PciHostBridge.h"\r
+\r
+STATIC\r
+CONST\r
+CB_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = {\r
+ {\r
+ {\r
+ ACPI_DEVICE_PATH,\r
+ ACPI_DP,\r
+ {\r
+ (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),\r
+ (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)\r
+ }\r
+ },\r
+ EISA_PNP_ID(0x0A03), // HID\r
+ 0 // UID\r
+ },\r
+\r
+ {\r
+ END_DEVICE_PATH_TYPE,\r
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
+ {\r
+ END_DEVICE_PATH_LENGTH,\r
+ 0\r
+ }\r
+ }\r
+};\r
+\r
+\r
+/**\r
+ Initialize a PCI_ROOT_BRIDGE structure.\r
+\r
+ @param[in] Supports Supported attributes.\r
+\r
+ @param[in] Attributes Initial attributes.\r
+\r
+ @param[in] AllocAttributes Allocation attributes.\r
+\r
+ @param[in] RootBusNumber The bus number to store in RootBus.\r
+\r
+ @param[in] MaxSubBusNumber The inclusive maximum bus number that can be\r
+ assigned to any subordinate bus found behind any\r
+ PCI bridge hanging off this root bus.\r
+\r
+ The caller is repsonsible for ensuring that\r
+ RootBusNumber <= MaxSubBusNumber. If\r
+ RootBusNumber equals MaxSubBusNumber, then the\r
+ root bus has no room for subordinate buses.\r
+\r
+ @param[in] Io IO aperture.\r
+\r
+ @param[in] Mem MMIO aperture.\r
+\r
+ @param[in] MemAbove4G MMIO aperture above 4G.\r
+\r
+ @param[in] PMem Prefetchable MMIO aperture.\r
+\r
+ @param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.\r
+\r
+ @param[out] RootBus The PCI_ROOT_BRIDGE structure (allocated by the\r
+ caller) that should be filled in by this\r
+ function.\r
+\r
+ @retval EFI_SUCCESS Initialization successful. A device path\r
+ consisting of an ACPI device path node, with\r
+ UID = RootBusNumber, has been allocated and\r
+ linked into RootBus.\r
+\r
+ @retval EFI_OUT_OF_RESOURCES Memory allocation failed.\r
+**/\r
+EFI_STATUS\r
+InitRootBridge (\r
+ IN UINT64 Supports,\r
+ IN UINT64 Attributes,\r
+ IN UINT64 AllocAttributes,\r
+ IN UINT8 RootBusNumber,\r
+ IN UINT8 MaxSubBusNumber,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Io,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *PMem,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,\r
+ OUT PCI_ROOT_BRIDGE *RootBus\r
+)\r
+{\r
+ CB_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;\r
+\r
+ //\r
+ // Be safe if other fields are added to PCI_ROOT_BRIDGE later.\r
+ //\r
+ ZeroMem (RootBus, sizeof *RootBus);\r
+\r
+ RootBus->Segment = 0;\r
+\r
+ RootBus->Supports = Supports;\r
+ RootBus->Attributes = Attributes;\r
+\r
+ RootBus->DmaAbove4G = FALSE;\r
+\r
+ RootBus->AllocationAttributes = AllocAttributes;\r
+ RootBus->Bus.Base = RootBusNumber;\r
+ RootBus->Bus.Limit = MaxSubBusNumber;\r
+ CopyMem (&RootBus->Io, Io, sizeof (*Io));\r
+ CopyMem (&RootBus->Mem, Mem, sizeof (*Mem));\r
+ CopyMem (&RootBus->MemAbove4G, MemAbove4G, sizeof (*MemAbove4G));\r
+ CopyMem (&RootBus->PMem, PMem, sizeof (*PMem));\r
+ CopyMem (&RootBus->PMemAbove4G, PMemAbove4G, sizeof (*PMemAbove4G));\r
+\r
+ RootBus->NoExtendedConfigSpace = FALSE;\r
+\r
+ DevicePath = AllocateCopyPool (sizeof (mRootBridgeDevicePathTemplate),\r
+ &mRootBridgeDevicePathTemplate);\r
+ if (DevicePath == NULL) {\r
+ DEBUG ((EFI_D_ERROR, "%a: %r\n", __FUNCTION__, EFI_OUT_OF_RESOURCES));\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+ DevicePath->AcpiDevicePath.UID = RootBusNumber;\r
+ RootBus->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;\r
+\r
+ DEBUG ((EFI_D_INFO,\r
+ "%a: populated root bus %d, with room for %d subordinate bus(es)\n",\r
+ __FUNCTION__, RootBusNumber, MaxSubBusNumber - RootBusNumber));\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Return all the root bridge instances in an array.\r
+\r
+ @param Count Return the count of root bridge instances.\r
+\r
+ @return All the root bridge instances in an array.\r
+ The array should be passed into PciHostBridgeFreeRootBridges()\r
+ when it's not used.\r
+**/\r
+PCI_ROOT_BRIDGE *\r
+EFIAPI\r
+PciHostBridgeGetRootBridges (\r
+ UINTN *Count\r
+)\r
+{\r
+ return ScanForRootBridges (Count);\r
+}\r
+\r
+\r
+/**\r
+ Free the root bridge instances array returned from\r
+ PciHostBridgeGetRootBridges().\r
+\r
+ @param The root bridge instances array.\r
+ @param The count of the array.\r
+**/\r
+VOID\r
+EFIAPI\r
+PciHostBridgeFreeRootBridges (\r
+ PCI_ROOT_BRIDGE *Bridges,\r
+ UINTN Count\r
+)\r
+{\r
+ if (Bridges == NULL && Count == 0) {\r
+ return;\r
+ }\r
+ ASSERT (Bridges != NULL && Count > 0);\r
+\r
+ do {\r
+ --Count;\r
+ FreePool (Bridges[Count].DevicePath);\r
+ } while (Count > 0);\r
+\r
+ FreePool (Bridges);\r
+}\r
+\r
+\r
+/**\r
+ Inform the platform that the resource conflict happens.\r
+\r
+ @param HostBridgeHandle Handle of the Host Bridge.\r
+ @param Configuration Pointer to PCI I/O and PCI memory resource\r
+ descriptors. The Configuration contains the resources\r
+ for all the root bridges. The resource for each root\r
+ bridge is terminated with END descriptor and an\r
+ additional END is appended indicating the end of the\r
+ entire resources. The resource descriptor field\r
+ values follow the description in\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ .SubmitResources().\r
+**/\r
+VOID\r
+EFIAPI\r
+PciHostBridgeResourceConflict (\r
+ EFI_HANDLE HostBridgeHandle,\r
+ VOID *Configuration\r
+)\r
+{\r
+ //\r
+ // coreboot UEFI Payload does not do PCI enumeration and should not call this\r
+ // library interface.\r
+ //\r
+ ASSERT (FALSE);\r
+}\r
--- /dev/null
+/** @file\r
+ Scan the entire PCI bus for root bridges to support coreboot UEFI payload.\r
+\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials are licensed and made available\r
+ under the terms and conditions of the BSD License which accompanies this\r
+ distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiDxe.h>\r
+#include <IndustryStandard/Pci.h>\r
+#include <Protocol/PciHostBridgeResourceAllocation.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/PciHostBridgeLib.h>\r
+#include <Library/PciLib.h>\r
+#include "PciHostBridge.h"\r
+\r
+/**\r
+ Adjust the collected PCI resource.\r
+\r
+ @param[in] Io IO aperture.\r
+\r
+ @param[in] Mem MMIO aperture.\r
+\r
+ @param[in] MemAbove4G MMIO aperture above 4G.\r
+\r
+ @param[in] PMem Prefetchable MMIO aperture.\r
+\r
+ @param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.\r
+**/\r
+VOID\r
+AdjustRootBridgeResource (\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Io,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *PMem,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G\r
+)\r
+{\r
+ UINT64 Mask;\r
+\r
+ //\r
+ // For now try to downgrade everything into MEM32 since\r
+ // - coreboot does not assign resource above 4GB\r
+ // - coreboot might allocate interleaved MEM32 and PMEM32 resource\r
+ // in some cases\r
+ //\r
+ if (PMem->Base < Mem->Base) {\r
+ Mem->Base = PMem->Base;\r
+ }\r
+\r
+ if (PMem->Limit > Mem->Limit) {\r
+ Mem->Limit = PMem->Limit;\r
+ }\r
+\r
+ PMem->Base = MAX_UINT64;\r
+ PMem->Limit = 0;\r
+\r
+ if (MemAbove4G->Base < 0x100000000ULL) {\r
+ if (MemAbove4G->Base < Mem->Base) {\r
+ Mem->Base = MemAbove4G->Base;\r
+ }\r
+ if (MemAbove4G->Limit > Mem->Limit) {\r
+ Mem->Limit = MemAbove4G->Limit;\r
+ }\r
+ MemAbove4G->Base = MAX_UINT64;\r
+ MemAbove4G->Limit = 0;\r
+ }\r
+\r
+ if (PMemAbove4G->Base < 0x100000000ULL) {\r
+ if (PMemAbove4G->Base < Mem->Base) {\r
+ Mem->Base = PMemAbove4G->Base;\r
+ }\r
+ if (PMemAbove4G->Limit > Mem->Limit) {\r
+ Mem->Limit = PMemAbove4G->Limit;\r
+ }\r
+ PMemAbove4G->Base = MAX_UINT64;\r
+ PMemAbove4G->Limit = 0;\r
+ }\r
+\r
+ //\r
+ // Align IO resource at 4K boundary\r
+ //\r
+ Mask = 0xFFFULL;\r
+ Io->Limit = (Io->Limit + Mask) & ~Mask;\r
+ if (Io->Base != MAX_UINT64) {\r
+ Io->Base &= ~Mask;\r
+ }\r
+\r
+ //\r
+ // Align MEM resource at 1MB boundary\r
+ //\r
+ Mask = 0xFFFFFULL;\r
+ Mem->Limit = (Mem->Limit + Mask) & ~Mask;\r
+ if (Mem->Base != MAX_UINT64) {\r
+ Mem->Base &= ~Mask;\r
+ }\r
+}\r
+\r
+/**\r
+ Probe a bar is existed or not.\r
+\r
+ @param[in] Address PCI address for the BAR.\r
+ @param[out] OriginalValue The original bar value returned.\r
+ @param[out] Value The probed bar value returned.\r
+**/\r
+STATIC\r
+VOID\r
+PcatPciRootBridgeBarExisted (\r
+ IN UINT64 Address,\r
+ OUT UINT32 *OriginalValue,\r
+ OUT UINT32 *Value\r
+)\r
+{\r
+ UINTN PciAddress;\r
+\r
+ PciAddress = (UINTN)Address;\r
+\r
+ //\r
+ // Preserve the original value\r
+ //\r
+ *OriginalValue = PciRead32 (PciAddress);\r
+\r
+ //\r
+ // Disable timer interrupt while the BAR is probed\r
+ //\r
+ DisableInterrupts ();\r
+\r
+ PciWrite32 (PciAddress, 0xFFFFFFFF);\r
+ *Value = PciRead32 (PciAddress);\r
+ PciWrite32 (PciAddress, *OriginalValue);\r
+\r
+ //\r
+ // Enable interrupt\r
+ //\r
+ EnableInterrupts ();\r
+}\r
+\r
+/**\r
+ Parse PCI bar and collect the assigned PCI resouce information.\r
+\r
+ @param[in] Command Supported attributes.\r
+\r
+ @param[in] Bus PCI bus number.\r
+\r
+ @param[in] Device PCI device number.\r
+\r
+ @param[in] Function PCI function number.\r
+\r
+ @param[in] BarOffsetBase PCI bar start offset.\r
+\r
+ @param[in] BarOffsetEnd PCI bar end offset.\r
+\r
+ @param[in] Io IO aperture.\r
+\r
+ @param[in] Mem MMIO aperture.\r
+\r
+ @param[in] MemAbove4G MMIO aperture above 4G.\r
+\r
+ @param[in] PMem Prefetchable MMIO aperture.\r
+\r
+ @param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.\r
+**/\r
+STATIC\r
+VOID\r
+PcatPciRootBridgeParseBars (\r
+ IN UINT16 Command,\r
+ IN UINTN Bus,\r
+ IN UINTN Device,\r
+ IN UINTN Function,\r
+ IN UINTN BarOffsetBase,\r
+ IN UINTN BarOffsetEnd,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Io,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *PMem,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G\r
+\r
+)\r
+{\r
+ UINT32 OriginalValue;\r
+ UINT32 Value;\r
+ UINT32 OriginalUpperValue;\r
+ UINT32 UpperValue;\r
+ UINT64 Mask;\r
+ UINTN Offset;\r
+ UINT64 Base;\r
+ UINT64 Length;\r
+ UINT64 Limit;\r
+ PCI_ROOT_BRIDGE_APERTURE *MemAperture;\r
+\r
+ for (Offset = BarOffsetBase; Offset < BarOffsetEnd; Offset += sizeof (UINT32)) {\r
+ PcatPciRootBridgeBarExisted (\r
+ PCI_LIB_ADDRESS (Bus, Device, Function, Offset),\r
+ &OriginalValue, &Value\r
+ );\r
+ if (Value == 0) {\r
+ continue;\r
+ }\r
+ if ((Value & BIT0) == BIT0) {\r
+ //\r
+ // IO Bar\r
+ //\r
+ if (Command & EFI_PCI_COMMAND_IO_SPACE) {\r
+ Mask = 0xfffffffc;\r
+ Base = OriginalValue & Mask;\r
+ Length = ((~(Value & Mask)) & Mask) + 0x04;\r
+ if (!(Value & 0xFFFF0000)) {\r
+ Length &= 0x0000FFFF;\r
+ }\r
+ Limit = Base + Length - 1;\r
+\r
+ if ((Base > 0) && (Base < Limit)) {\r
+ if (Io->Base > Base) {\r
+ Io->Base = Base;\r
+ }\r
+ if (Io->Limit < Limit) {\r
+ Io->Limit = Limit;\r
+ }\r
+ }\r
+ }\r
+ } else {\r
+ //\r
+ // Mem Bar\r
+ //\r
+ if (Command & EFI_PCI_COMMAND_MEMORY_SPACE) {\r
+\r
+ Mask = 0xfffffff0;\r
+ Base = OriginalValue & Mask;\r
+ Length = Value & Mask;\r
+\r
+ if ((Value & (BIT1 | BIT2)) == 0) {\r
+ //\r
+ // 32bit\r
+ //\r
+ Length = ((~Length) + 1) & 0xffffffff;\r
+\r
+ if ((Value & BIT3) == BIT3) {\r
+ MemAperture = PMem;\r
+ } else {\r
+ MemAperture = Mem;\r
+ }\r
+ } else {\r
+ //\r
+ // 64bit\r
+ //\r
+ Offset += 4;\r
+ PcatPciRootBridgeBarExisted (\r
+ PCI_LIB_ADDRESS (Bus, Device, Function, Offset),\r
+ &OriginalUpperValue,\r
+ &UpperValue\r
+ );\r
+\r
+ Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32);\r
+ Length = Length | LShiftU64 ((UINT64) UpperValue, 32);\r
+ Length = (~Length) + 1;\r
+\r
+ if ((Value & BIT3) == BIT3) {\r
+ MemAperture = PMemAbove4G;\r
+ } else {\r
+ MemAperture = MemAbove4G;\r
+ }\r
+ }\r
+\r
+ Limit = Base + Length - 1;\r
+ if ((Base > 0) && (Base < Limit)) {\r
+ if (MemAperture->Base > Base) {\r
+ MemAperture->Base = Base;\r
+ }\r
+ if (MemAperture->Limit < Limit) {\r
+ MemAperture->Limit = Limit;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ Scan for all root bridges in platform.\r
+\r
+ @param[out] NumberOfRootBridges Number of root bridges detected\r
+\r
+ @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.\r
+**/\r
+PCI_ROOT_BRIDGE *\r
+ScanForRootBridges (\r
+ OUT UINTN *NumberOfRootBridges\r
+)\r
+{\r
+ UINTN PrimaryBus;\r
+ UINTN SubBus;\r
+ UINT8 Device;\r
+ UINT8 Function;\r
+ UINTN NumberOfDevices;\r
+ UINTN Address;\r
+ PCI_TYPE01 Pci;\r
+ UINT64 Attributes;\r
+ UINT64 Base;\r
+ UINT64 Limit;\r
+ UINT64 Value;\r
+ PCI_ROOT_BRIDGE_APERTURE Io, Mem, MemAbove4G, PMem, PMemAbove4G, *MemAperture;\r
+ PCI_ROOT_BRIDGE *RootBridges;\r
+ UINTN BarOffsetEnd;\r
+\r
+\r
+ *NumberOfRootBridges = 0;\r
+ RootBridges = NULL;\r
+\r
+ //\r
+ // After scanning all the PCI devices on the PCI root bridge's primary bus,\r
+ // update the Primary Bus Number for the next PCI root bridge to be this PCI\r
+ // root bridge's subordinate bus number + 1.\r
+ //\r
+ for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {\r
+ SubBus = PrimaryBus;\r
+ Attributes = 0;\r
+ Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64;\r
+ Io.Limit = Mem.Limit = MemAbove4G.Limit = PMem.Limit = PMemAbove4G.Limit = 0;\r
+ //\r
+ // Scan all the PCI devices on the primary bus of the PCI root bridge\r
+ //\r
+ for (Device = 0, NumberOfDevices = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
+\r
+ for (Function = 0; Function <= PCI_MAX_FUNC; Function++) {\r
+\r
+ //\r
+ // Compute the PCI configuration address of the PCI device to probe\r
+ //\r
+ Address = PCI_LIB_ADDRESS (PrimaryBus, Device, Function, 0);\r
+\r
+ //\r
+ // Read the Vendor ID from the PCI Configuration Header\r
+ //\r
+ if (PciRead16 (Address) == MAX_UINT16) {\r
+ if (Function == 0) {\r
+ //\r
+ // If the PCI Configuration Read fails, or a PCI device does not\r
+ // exist, then skip this entire PCI device\r
+ //\r
+ break;\r
+ } else {\r
+ //\r
+ // If PCI function != 0, VendorId == 0xFFFF, we continue to search\r
+ // PCI function.\r
+ //\r
+ continue;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Read the entire PCI Configuration Header\r
+ //\r
+ PciReadBuffer (Address, sizeof (Pci), &Pci);\r
+\r
+ //\r
+ // Increment the number of PCI device found on the primary bus of the\r
+ // PCI root bridge\r
+ //\r
+ NumberOfDevices++;\r
+\r
+ //\r
+ // Look for devices with the VGA Palette Snoop enabled in the COMMAND\r
+ // register of the PCI Config Header\r
+ //\r
+ if ((Pci.Hdr.Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+ }\r
+\r
+ BarOffsetEnd = 0;\r
+\r
+ //\r
+ // PCI-PCI Bridge\r
+ //\r
+ if (IS_PCI_BRIDGE (&Pci)) {\r
+ //\r
+ // Get the Bus range that the PPB is decoding\r
+ //\r
+ if (Pci.Bridge.SubordinateBus > SubBus) {\r
+ //\r
+ // If the suborinate bus number of the PCI-PCI bridge is greater\r
+ // than the PCI root bridge's current subordinate bus number,\r
+ // then update the PCI root bridge's subordinate bus number\r
+ //\r
+ SubBus = Pci.Bridge.SubordinateBus;\r
+ }\r
+\r
+ //\r
+ // Get the I/O range that the PPB is decoding\r
+ //\r
+ Value = Pci.Bridge.IoBase & 0x0f;\r
+ Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8;\r
+ Limit = (((UINT32) Pci.Bridge.IoLimit & 0xf0) << 8) | 0x0fff;\r
+ if (Value == BIT0) {\r
+ Base |= ((UINT32) Pci.Bridge.IoBaseUpper16 << 16);\r
+ Limit |= ((UINT32) Pci.Bridge.IoLimitUpper16 << 16);\r
+ }\r
+ if ((Base > 0) && (Base < Limit)) {\r
+ if (Io.Base > Base) {\r
+ Io.Base = Base;\r
+ }\r
+ if (Io.Limit < Limit) {\r
+ Io.Limit = Limit;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Get the Memory range that the PPB is decoding\r
+ //\r
+ Base = ((UINT32) Pci.Bridge.MemoryBase & 0xfff0) << 16;\r
+ Limit = (((UINT32) Pci.Bridge.MemoryLimit & 0xfff0) << 16) | 0xfffff;\r
+ if ((Base > 0) && (Base < Limit)) {\r
+ if (Mem.Base > Base) {\r
+ Mem.Base = Base;\r
+ }\r
+ if (Mem.Limit < Limit) {\r
+ Mem.Limit = Limit;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Get the Prefetchable Memory range that the PPB is decoding\r
+ //\r
+ Value = Pci.Bridge.PrefetchableMemoryBase & 0x0f;\r
+ Base = ((UINT32) Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;\r
+ Limit = (((UINT32) Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)\r
+ << 16) | 0xfffff;\r
+ MemAperture = &PMem;\r
+ if (Value == BIT0) {\r
+ Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);\r
+ Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);\r
+ MemAperture = &PMemAbove4G;\r
+ }\r
+ if ((Base > 0) && (Base < Limit)) {\r
+ if (MemAperture->Base > Base) {\r
+ MemAperture->Base = Base;\r
+ }\r
+ if (MemAperture->Limit < Limit) {\r
+ MemAperture->Limit = Limit;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Look at the PPB Configuration for legacy decoding attributes\r
+ //\r
+ if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA)\r
+ == EFI_PCI_BRIDGE_CONTROL_ISA) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
+ }\r
+ if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA)\r
+ == EFI_PCI_BRIDGE_CONTROL_VGA) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
+ if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA_16)\r
+ != 0) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;\r
+ }\r
+ }\r
+\r
+ BarOffsetEnd = OFFSET_OF (PCI_TYPE01, Bridge.Bar[2]);\r
+ } else {\r
+ //\r
+ // Parse the BARs of the PCI device to get what I/O Ranges, Memory\r
+ // Ranges, and Prefetchable Memory Ranges the device is decoding\r
+ //\r
+ if ((Pci.Hdr.HeaderType & HEADER_LAYOUT_CODE) == HEADER_TYPE_DEVICE) {\r
+ BarOffsetEnd = OFFSET_OF (PCI_TYPE00, Device.Bar[6]);\r
+ }\r
+ }\r
+\r
+ PcatPciRootBridgeParseBars (\r
+ Pci.Hdr.Command,\r
+ PrimaryBus,\r
+ Device,\r
+ Function,\r
+ OFFSET_OF (PCI_TYPE00, Device.Bar),\r
+ BarOffsetEnd,\r
+ &Io,\r
+ &Mem, &MemAbove4G,\r
+ &PMem, &PMemAbove4G\r
+ );\r
+\r
+ //\r
+ // See if the PCI device is an IDE controller\r
+ //\r
+ if (IS_CLASS2 (&Pci, PCI_CLASS_MASS_STORAGE,\r
+ PCI_CLASS_MASS_STORAGE_IDE)) {\r
+ if (Pci.Hdr.ClassCode[0] & 0x80) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
+ }\r
+ if (Pci.Hdr.ClassCode[0] & 0x01) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
+ }\r
+ if (Pci.Hdr.ClassCode[0] & 0x04) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
+ }\r
+ }\r
+\r
+ //\r
+ // See if the PCI device is a legacy VGA controller or\r
+ // a standard VGA controller\r
+ //\r
+ if (IS_CLASS2 (&Pci, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) ||\r
+ IS_CLASS2 (&Pci, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA)\r
+ ) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;\r
+ }\r
+\r
+ //\r
+ // See if the PCI Device is a PCI - ISA or PCI - EISA\r
+ // or ISA_POSITIVIE_DECODE Bridge device\r
+ //\r
+ if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) {\r
+ if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA ||\r
+ Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_EISA ||\r
+ Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
+ }\r
+ }\r
+\r
+ //\r
+ // If this device is not a multi function device, then skip the rest\r
+ // of this PCI device\r
+ //\r
+ if (Function == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ //\r
+ // If at least one PCI device was found on the primary bus of this PCI\r
+ // root bridge, then the PCI root bridge exists.\r
+ //\r
+ if (NumberOfDevices > 0) {\r
+ RootBridges = ReallocatePool (\r
+ (*NumberOfRootBridges) * sizeof (PCI_ROOT_BRIDGE),\r
+ (*NumberOfRootBridges + 1) * sizeof (PCI_ROOT_BRIDGE),\r
+ RootBridges\r
+ );\r
+ ASSERT (RootBridges != NULL);\r
+\r
+ AdjustRootBridgeResource (&Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G);\r
+\r
+ InitRootBridge (\r
+ Attributes, Attributes, 0,\r
+ (UINT8) PrimaryBus, (UINT8) SubBus,\r
+ &Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G,\r
+ &RootBridges[*NumberOfRootBridges]\r
+ );\r
+ RootBridges[*NumberOfRootBridges].ResourceAssigned = TRUE;\r
+ //\r
+ // Increment the index for the next PCI Root Bridge\r
+ //\r
+ (*NumberOfRootBridges)++;\r
+ }\r
+ }\r
+\r
+ return RootBridges;\r
+}\r
projects / mirror_edk2.git / commitdiff