/** @file\r
This file contains definitions for the SPD fields on an SDRAM.\r
- \r
- Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials \r
- are licensed and made available under the terms and conditions of the BSD License \r
- which accompanies this distribution. The full text of the license may be found at \r
- http://opensource.org/licenses/bsd-license.php \r
\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+ Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
**/\r
\r
#ifndef _SDRAM_SPD_H_\r
#define _SDRAM_SPD_H_\r
\r
+#include <IndustryStandard/SdramSpdDdr3.h>\r
+#include <IndustryStandard/SdramSpdDdr4.h>\r
+#include <IndustryStandard/SdramSpdLpDdr.h>\r
+\r
//\r
// SDRAM SPD field definitions\r
//\r
//\r
// Memory Type Definitions\r
//\r
-#define SPD_VAL_SDR_TYPE 4 ///< SDR SDRAM memory\r
-#define SPD_VAL_DDR_TYPE 7 ///< DDR SDRAM memory\r
-#define SPD_VAL_DDR2_TYPE 8 ///< DDR2 SDRAM memory\r
+#define SPD_VAL_SDR_TYPE 4 ///< SDR SDRAM memory\r
+#define SPD_VAL_DDR_TYPE 7 ///< DDR SDRAM memory\r
+#define SPD_VAL_DDR2_TYPE 8 ///< DDR2 SDRAM memory\r
+#define SPD_VAL_DDR3_TYPE 11 ///< DDR3 SDRAM memory\r
+#define SPD_VAL_DDR4_TYPE 12 ///< DDR4 SDRAM memory\r
+#define SPD_VAL_LPDDR3_TYPE 15 ///< LPDDR3 SDRAM memory\r
+#define SPD_VAL_LPDDR4_TYPE 16 ///< LPDDR4 SDRAM memory\r
+\r
//\r
// ECC Type Definitions\r
//\r
--- /dev/null
+/** @file\r
+ This file contains definitions for SPD DDR3.\r
+\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Revision Reference:\r
+ - Serial Presence Detect (SPD) for DDR3 SDRAM Modules Document Release 6\r
+ http://www.jedec.org/sites/default/files/docs/4_01_02_11R21A.pdf\r
+**/\r
+\r
+#ifndef _SDRAM_SPD_DDR3_H_\r
+#define _SDRAM_SPD_DDR3_H_\r
+\r
+#pragma pack (push, 1)\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 BytesUsed : 4; ///< Bits 3:0\r
+ UINT8 BytesTotal : 3; ///< Bits 6:4\r
+ UINT8 CrcCoverage : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_DEVICE_DESCRIPTION_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Minor : 4; ///< Bits 3:0\r
+ UINT8 Major : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_REVISION_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Type : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_DRAM_DEVICE_TYPE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 ModuleType : 4; ///< Bits 3:0\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_MODULE_TYPE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Density : 4; ///< Bits 3:0\r
+ UINT8 BankAddress : 3; ///< Bits 6:4\r
+ UINT8 Reserved : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_SDRAM_DENSITY_BANKS_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 ColumnAddress : 3; ///< Bits 2:0\r
+ UINT8 RowAddress : 3; ///< Bits 5:3\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_SDRAM_ADDRESSING_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 OperationAt1_50 : 1; ///< Bits 0:0\r
+ UINT8 OperationAt1_35 : 1; ///< Bits 1:1\r
+ UINT8 OperationAt1_25 : 1; ///< Bits 2:2\r
+ UINT8 Reserved : 5; ///< Bits 7:3\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 SdramDeviceWidth : 3; ///< Bits 2:0\r
+ UINT8 RankCount : 3; ///< Bits 5:3\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_MODULE_ORGANIZATION_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 PrimaryBusWidth : 3; ///< Bits 2:0\r
+ UINT8 BusWidthExtension : 2; ///< Bits 4:3\r
+ UINT8 Reserved : 3; ///< Bits 7:5\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Divisor : 4; ///< Bits 3:0\r
+ UINT8 Dividend : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_FINE_TIMEBASE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Dividend : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Divisor : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT;\r
+\r
+typedef struct {\r
+ SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT Dividend; ///< Medium Timebase (MTB) Dividend\r
+ SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT Divisor; ///< Medium Timebase (MTB) Divisor\r
+} SPD3_MEDIUM_TIMEBASE;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tCKmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_TCK_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT16 Cl4 : 1; ///< Bits 0:0\r
+ UINT16 Cl5 : 1; ///< Bits 1:1\r
+ UINT16 Cl6 : 1; ///< Bits 2:2\r
+ UINT16 Cl7 : 1; ///< Bits 3:3\r
+ UINT16 Cl8 : 1; ///< Bits 4:4\r
+ UINT16 Cl9 : 1; ///< Bits 5:5\r
+ UINT16 Cl10 : 1; ///< Bits 6:6\r
+ UINT16 Cl11 : 1; ///< Bits 7:7\r
+ UINT16 Cl12 : 1; ///< Bits 8:8\r
+ UINT16 Cl13 : 1; ///< Bits 9:9\r
+ UINT16 Cl14 : 1; ///< Bits 10:10\r
+ UINT16 Cl15 : 1; ///< Bits 11:11\r
+ UINT16 Cl16 : 1; ///< Bits 12:12\r
+ UINT16 Cl17 : 1; ///< Bits 13:13\r
+ UINT16 Cl18 : 1; ///< Bits 14:14\r
+ UINT16 Reserved : 1; ///< Bits 15:15\r
+ } Bits;\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
+} SPD3_CAS_LATENCIES_SUPPORTED_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tAAmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_TAA_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tWRmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_TWR_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tRCDmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_TRCD_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tRRDmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_TRRD_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tRPmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_TRP_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tRASminUpper : 4; ///< Bits 3:0\r
+ UINT8 tRCminUpper : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_TRAS_TRC_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tRASmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_TRAS_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tRCmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_TRC_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT16 tRFCmin : 16; ///< Bits 15:0\r
+ } Bits;\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
+} SPD3_TRFC_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tWTRmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_TWTR_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tRTPmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_TRTP_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tFAWminUpper : 4; ///< Bits 3:0\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_TFAW_MIN_MTB_UPPER_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tFAWmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_TFAW_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Rzq6 : 1; ///< Bits 0:0\r
+ UINT8 Rzq7 : 1; ///< Bits 1:1\r
+ UINT8 Reserved : 5; ///< Bits 6:2\r
+ UINT8 DllOff : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 ExtendedTemperatureRange : 1; ///< Bits 0:0\r
+ UINT8 ExtendedTemperatureRefreshRate : 1; ///< Bits 1:1\r
+ UINT8 AutoSelfRefresh : 1; ///< Bits 2:2\r
+ UINT8 OnDieThermalSensor : 1; ///< Bits 3:3\r
+ UINT8 Reserved : 3; ///< Bits 6:4\r
+ UINT8 PartialArraySelfRefresh : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_SDRAM_THERMAL_REFRESH_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 ThermalSensorAccuracy : 7; ///< Bits 6:0\r
+ UINT8 ThermalSensorPresence : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_MODULE_THERMAL_SENSOR_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 SignalLoading : 2; ///< Bits 1:0\r
+ UINT8 Reserved : 2; ///< Bits 3:2\r
+ UINT8 DieCount : 3; ///< Bits 6:4\r
+ UINT8 SdramDeviceType : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_SDRAM_DEVICE_TYPE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tCKminFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD3_TCK_MIN_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tAAminFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD3_TAA_MIN_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tRCDminFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD3_TRCD_MIN_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tRPminFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD3_TRP_MIN_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tRCminFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD3_TRC_MIN_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 MaximumActivateCount : 4; ///< Bits 3:0\r
+ UINT8 MaximumActivateWindow : 2; ///< Bits 5:4\r
+ UINT8 VendorSpecific : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Height : 5; ///< Bits 4:0\r
+ UINT8 RawCardExtension : 3; ///< Bits 7:5\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_UNBUF_MODULE_NOMINAL_HEIGHT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 FrontThickness : 4; ///< Bits 3:0\r
+ UINT8 BackThickness : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_UNBUF_MODULE_NOMINAL_THICKNESS;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Card : 5; ///< Bits 4:0\r
+ UINT8 Revision : 2; ///< Bits 6:5\r
+ UINT8 Extension : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_UNBUF_REFERENCE_RAW_CARD;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 MappingRank1 : 1; ///< Bits 0:0\r
+ UINT8 Reserved : 7; ///< Bits 7:1\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_UNBUF_ADDRESS_MAPPING;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Height : 5; ///< Bits 4:0\r
+ UINT8 Reserved : 3; ///< Bits 7:5\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_RDIMM_MODULE_NOMINAL_HEIGHT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 FrontThickness : 4; ///< Bits 3:0\r
+ UINT8 BackThickness : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_RDIMM_MODULE_NOMINAL_THICKNESS;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Card : 5; ///< Bits 4:0\r
+ UINT8 Revision : 2; ///< Bits 6:5\r
+ UINT8 Extension : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_RDIMM_REFERENCE_RAW_CARD;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 RegisterCount : 2; ///< Bits 1:0\r
+ UINT8 DramRowCount : 2; ///< Bits 3:2\r
+ UINT8 RegisterType : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_RDIMM_MODULE_ATTRIBUTES;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0\r
+ UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT16 ContinuationCount : 7; ///< Bits 6:0\r
+ UINT16 ContinuationParity : 1; ///< Bits 7:7\r
+ UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r
+ } Bits;\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
+} SPD3_MANUFACTURER_ID_CODE;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 RegisterRevisionNumber; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_RDIMM_REGISTER_REVISION_NUMBER;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Bit0 : 1; ///< Bits 0:0\r
+ UINT8 Bit1 : 1; ///< Bits 1:1\r
+ UINT8 Bit2 : 1; ///< Bits 2:2\r
+ UINT8 Reserved : 5; ///< Bits 7:3\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_RDIMM_REGISTER_TYPE;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Reserved : 4; ///< Bits 0:3\r
+ UINT8 CommandAddressAOutputs : 2; ///< Bits 5:4\r
+ UINT8 CommandAddressBOutputs : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 ControlSignalsAOutputs : 2; ///< Bits 0:1\r
+ UINT8 ControlSignalsBOutputs : 2; ///< Bits 3:2\r
+ UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4\r
+ UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Reserved0 : 4; ///< Bits 0:3\r
+ UINT8 Reserved1 : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_RDIMM_REGISTER_CONTROL_RESERVED;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Height : 5; ///< Bits 4:0\r
+ UINT8 Reserved : 3; ///< Bits 7:5\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 FrontThickness : 4; ///< Bits 3:0\r
+ UINT8 BackThickness : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Card : 5; ///< Bits 4:0\r
+ UINT8 Revision : 2; ///< Bits 6:5\r
+ UINT8 Extension : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_LRDIMM_REFERENCE_RAW_CARD;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 RegisterCount : 2; ///< Bits 1:0\r
+ UINT8 DramRowCount : 2; ///< Bits 3:2\r
+ UINT8 RegisterType : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_LRDIMM_MODULE_ATTRIBUTES;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 AddressCommandPrelaunch : 1; ///< Bits 0:0\r
+ UINT8 Rank1Rank5Swap : 1; ///< Bits 1:1\r
+ UINT8 Reserved0 : 1; ///< Bits 2:2\r
+ UINT8 Reserved1 : 1; ///< Bits 3:3\r
+ UINT8 AddressCommandOutputs : 2; ///< Bits 5:4\r
+ UINT8 QxCS_nOutputs : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 QxOdtOutputs : 2; ///< Bits 1:0\r
+ UINT8 QxCkeOutputs : 2; ///< Bits 3:2\r
+ UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4\r
+ UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_LRDIMM_TIMING_DRIVE_STRENGTH;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 YExtendedDelay : 2; ///< Bits 1:0\r
+ UINT8 QxCS_n : 2; ///< Bits 3:2\r
+ UINT8 QxOdt : 2; ///< Bits 5:4\r
+ UINT8 QxCke : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_LRDIMM_EXTENDED_DELAY;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 DelayY : 3; ///< Bits 2:0\r
+ UINT8 Reserved : 1; ///< Bits 3:3\r
+ UINT8 QxCS_n : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 QxCS_n : 4; ///< Bits 3:0\r
+ UINT8 QxOdt : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 RC8MdqOdtStrength : 3; ///< Bits 2:0\r
+ UINT8 RC8Reserved : 1; ///< Bits 3:3\r
+ UINT8 RC9MdqOdtStrength : 3; ///< Bits 6:4\r
+ UINT8 RC9Reserved : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 RC10DA3ValueR0 : 1; ///< Bits 0:0\r
+ UINT8 RC10DA4ValueR0 : 1; ///< Bits 1:1\r
+ UINT8 RC10DA3ValueR1 : 1; ///< Bits 2:2\r
+ UINT8 RC10DA4ValueR1 : 1; ///< Bits 3:3\r
+ UINT8 RC11DA3ValueR0 : 1; ///< Bits 4:4\r
+ UINT8 RC11DA4ValueR0 : 1; ///< Bits 5:5\r
+ UINT8 RC11DA3ValueR1 : 1; ///< Bits 6:6\r
+ UINT8 RC11DA4ValueR1 : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Driver_Impedance : 2; ///< Bits 1:0\r
+ UINT8 Rtt_Nom : 3; ///< Bits 4:2\r
+ UINT8 Reserved : 1; ///< Bits 5:5\r
+ UINT8 Rtt_WR : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_LRDIMM_MR_1_2;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 MinimumDelayTime : 7; ///< Bits 0:6\r
+ UINT8 Reserved : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD3_LRDIMM_MODULE_DELAY_TIME;\r
+\r
+typedef struct {\r
+ UINT8 Year; ///< Year represented in BCD (00h = 2000)\r
+ UINT8 Week; ///< Year represented in BCD (47h = week 47)\r
+} SPD3_MANUFACTURING_DATE;\r
+\r
+typedef union {\r
+ UINT32 Data;\r
+ UINT16 SerialNumber16[2];\r
+ UINT8 SerialNumber8[4];\r
+} SPD3_MANUFACTURER_SERIAL_NUMBER;\r
+\r
+typedef struct {\r
+ UINT8 Location; ///< Module Manufacturing Location\r
+} SPD3_MANUFACTURING_LOCATION;\r
+\r
+typedef struct {\r
+ SPD3_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code\r
+ SPD3_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location\r
+ SPD3_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)\r
+ SPD3_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number\r
+} SPD3_UNIQUE_MODULE_ID;\r
+\r
+typedef union {\r
+ UINT16 Crc[1];\r
+ UINT8 Data8[2];\r
+} SPD3_CYCLIC_REDUNDANCY_CODE;\r
+\r
+typedef struct {\r
+ SPD3_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2\r
+ SPD3_REVISION_STRUCT Revision; ///< 1 SPD Revision\r
+ SPD3_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type\r
+ SPD3_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type\r
+ SPD3_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks\r
+ SPD3_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing\r
+ SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 6 Module Nominal Voltage, VDD\r
+ SPD3_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 7 Module Organization\r
+ SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 8 Module Memory Bus Width\r
+ SPD3_FINE_TIMEBASE_STRUCT FineTimebase; ///< 9 Fine Timebase (FTB) Dividend / Divisor\r
+ SPD3_MEDIUM_TIMEBASE MediumTimebase; ///< 10-11 Medium Timebase (MTB) Dividend\r
+ SPD3_TCK_MIN_MTB_STRUCT tCKmin; ///< 12 SDRAM Minimum Cycle Time (tCKmin)\r
+ UINT8 Reserved0; ///< 13 Reserved\r
+ SPD3_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 14-15 CAS Latencies Supported\r
+ SPD3_TAA_MIN_MTB_STRUCT tAAmin; ///< 16 Minimum CAS Latency Time (tAAmin)\r
+ SPD3_TWR_MIN_MTB_STRUCT tWRmin; ///< 17 Minimum Write Recovery Time (tWRmin)\r
+ SPD3_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 18 Minimum RAS# to CAS# Delay Time (tRCDmin)\r
+ SPD3_TRRD_MIN_MTB_STRUCT tRRDmin; ///< 19 Minimum Row Active to Row Active Delay Time (tRRDmin)\r
+ SPD3_TRP_MIN_MTB_STRUCT tRPmin; ///< 20 Minimum Row Precharge Delay Time (tRPmin)\r
+ SPD3_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 21 Upper Nibbles for tRAS and tRC\r
+ SPD3_TRAS_MIN_MTB_STRUCT tRASmin; ///< 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte\r
+ SPD3_TRC_MIN_MTB_STRUCT tRCmin; ///< 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte\r
+ SPD3_TRFC_MIN_MTB_STRUCT tRFCmin; ///< 24-25 Minimum Refresh Recovery Delay Time (tRFCmin)\r
+ SPD3_TWTR_MIN_MTB_STRUCT tWTRmin; ///< 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)\r
+ SPD3_TRTP_MIN_MTB_STRUCT tRTPmin; ///< 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)\r
+ SPD3_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 28 Upper Nibble for tFAW\r
+ SPD3_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 29 Minimum Four Activate Window Delay Time (tFAWmin)\r
+ SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 30 SDRAM Optional Features\r
+ SPD3_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 31 SDRAM Thermal And Refresh Options\r
+ SPD3_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 32 Module Thermal Sensor\r
+ SPD3_SDRAM_DEVICE_TYPE_STRUCT SdramDeviceType; ///< 33 SDRAM Device Type\r
+ SPD3_TCK_MIN_FTB_STRUCT tCKminFine; ///< 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)\r
+ SPD3_TAA_MIN_FTB_STRUCT tAAminFine; ///< 35 Fine Offset for Minimum CAS Latency Time (tAAmin)\r
+ SPD3_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)\r
+ SPD3_TRP_MIN_FTB_STRUCT tRPminFine; ///< 37 Minimum Row Precharge Delay Time (tRPmin)\r
+ SPD3_TRC_MIN_FTB_STRUCT tRCminFine; ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)\r
+ UINT8 Reserved1[40 - 39 + 1]; ///< 39 - 40 Reserved\r
+ SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT MacValue; ///< 41 SDRAM Maximum Active Count (MAC) Value\r
+ UINT8 Reserved2[59 - 42 + 1]; ///< 42 - 59 Reserved\r
+} SPD3_BASE_SECTION;\r
+\r
+typedef struct {\r
+ SPD3_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
+ SPD3_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
+ SPD3_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
+ SPD3_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 63 Address Mapping from Edge Connector to DRAM\r
+ UINT8 Reserved[116 - 64 + 1]; ///< 64-116 Reserved\r
+} SPD3_MODULE_UNBUFFERED;\r
+\r
+typedef struct {\r
+ SPD3_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
+ SPD3_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
+ SPD3_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
+ SPD3_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 DIMM Module Attributes\r
+ SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution; ///< 64 RDIMM Thermal Heat Spreader Solution\r
+ SPD3_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 65-66 Register Manufacturer ID Code\r
+ SPD3_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 67 Register Revision Number\r
+ SPD3_RDIMM_REGISTER_TYPE RegisterType; ///< 68 Register Type\r
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc1Rc0; ///< 69 RC1 (MS Nibble) / RC0 (LS Nibble) - Reserved\r
+ SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS Rc3Rc2; ///< 70 RC3 (MS Nibble) / RC2 (LS Nibble) - Drive Strength, Command/Address\r
+ SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK Rc5Rc4; ///< 71 RC5 (MS Nibble) / RC4 (LS Nibble) - Drive Strength, Control and Clock\r
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc7Rc6; ///< 72 RC7 (MS Nibble) / RC6 (LS Nibble) - Reserved for Register Vendor\r
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc9Rc8; ///< 73 RC9 (MS Nibble) / RC8 (LS Nibble) - Reserved\r
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc11Rc10; ///< 74 RC11 (MS Nibble) / RC10 (LS Nibble) - Reserved\r
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc13Rc12; ///< 75 RC12 (MS Nibble) / RC12 (LS Nibble) - Reserved\r
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc15Rc14; ///< 76 RC15 (MS Nibble) / RC14 (LS Nibble) - Reserved\r
+ UINT8 Reserved[116 - 77 + 1]; ///< 77-116 Reserved\r
+} SPD3_MODULE_REGISTERED;\r
+\r
+typedef struct {\r
+ SPD3_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
+ SPD3_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
+ SPD3_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
+ UINT8 Reserved[116 - 63 + 1]; ///< 63-116 Reserved\r
+} SPD3_MODULE_CLOCKED;\r
+\r
+typedef struct {\r
+ SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
+ SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
+ SPD3_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
+ SPD3_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 Module Attributes\r
+ UINT8 MemoryBufferRevisionNumber; ///< 64 Memory Buffer Revision Number\r
+ SPD3_MANUFACTURER_ID_CODE ManufacturerIdCode; ///< 65-66 Memory Buffer Manufacturer ID Code\r
+ SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH TimingControlDriveStrengthCaCs; ///< 67 F0RC3 / F0RC2 - Timing Control & Drive Strength, CA & CS\r
+ SPD3_LRDIMM_TIMING_DRIVE_STRENGTH DriveStrength; ///< 68 F0RC5 / F0RC4 - Drive Strength, ODT & CKE and Y\r
+ SPD3_LRDIMM_EXTENDED_DELAY ExtendedDelay; ///< 69 F1RC11 / F1RC8 - Extended Delay for Y, CS and ODT & CKE\r
+ SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA AdditiveDelayForCsCa; ///< 70 F1RC13 / F1RC12 - Additive Delay for CS and CA\r
+ SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE AdditiveDelayForOdtCke; ///< 71 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r
+ SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor800_1066; ///< 72 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor800_1066; ///< 73 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor800_1066; ///< 74 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor800_1066; ///< 75 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor800_1066; ///< 76 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor800_1066; ///< 77 MR1,2 Registers for 800 & 1066\r
+ SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor1333_1600; ///< 78 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor1333_1600; ///< 79 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor1333_1600; ///< 80 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor1333_1600; ///< 81 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor1333_1600; ///< 82 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1333_1600; ///< 83 MR1,2 Registers for 800 & 1066\r
+ SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor1866_2133; ///< 84 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor1866_2133; ///< 85 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor1866_2133; ///< 86 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor1866_2133; ///< 87 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor1866_2133; ///< 88 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1866_2133; ///< 89 MR1,2 Registers for 800 & 1066\r
+ SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_5V; ///< 90 Minimum Module Delay Time for 1.5 V\r
+ SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_5V; ///< 91 Maximum Module Delay Time for 1.5 V\r
+ SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_35V; ///< 92 Minimum Module Delay Time for 1.35 V\r
+ SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_35V; ///< 93 Maximum Module Delay Time for 1.35 V\r
+ SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_25V; ///< 94 Minimum Module Delay Time for 1.25 V\r
+ SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_25V; ///< 95 Maximum Module Delay Time for 1.25 V\r
+ UINT8 Reserved[101 - 96 + 1]; ///< 96-101 Reserved\r
+ UINT8 PersonalityByte[116 - 102 + 1]; ///< 102-116 Memory Buffer Personality Bytes\r
+} SPD3_MODULE_LOADREDUCED;\r
+\r
+typedef union {\r
+ SPD3_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types\r
+ SPD3_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types\r
+ SPD3_MODULE_CLOCKED Clocked; ///< 128-255 Registered Memory Module Types\r
+ SPD3_MODULE_LOADREDUCED LoadReduced; ///< 128-255 Load Reduced Memory Module Types\r
+} SPD3_MODULE_SPECIFIC;\r
+\r
+typedef struct {\r
+ UINT8 ModulePartNumber[145 - 128 + 1]; ///< 128-145 Module Part Number\r
+} SPD3_MODULE_PART_NUMBER;\r
+\r
+typedef struct {\r
+ UINT8 ModuleRevisionCode[147 - 146 + 1]; ///< 146-147 Module Revision Code\r
+} SPD3_MODULE_REVISION_CODE;\r
+\r
+typedef struct {\r
+ UINT8 ManufacturerSpecificData[175 - 150 + 1];///< 150-175 Manufacturer's Specific Data\r
+} SPD3_MANUFACTURER_SPECIFIC;\r
+\r
+///\r
+/// DDR3 Serial Presence Detect structure\r
+///\r
+typedef struct {\r
+ SPD3_BASE_SECTION General; ///< 0-59 General Section\r
+ SPD3_MODULE_SPECIFIC Module; ///< 60-116 Module-Specific Section\r
+ SPD3_UNIQUE_MODULE_ID ModuleId; ///< 117-125 Unique Module ID\r
+ SPD3_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)\r
+ SPD3_MODULE_PART_NUMBER ModulePartNumber; ///< 128-145 Module Part Number\r
+ SPD3_MODULE_REVISION_CODE ModuleRevisionCode; ///< 146-147 Module Revision Code\r
+ SPD3_MANUFACTURER_ID_CODE DramIdCode; ///< 148-149 Dram Manufacturer ID Code\r
+ SPD3_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 150-175 Manufacturer's Specific Data\r
+ UINT8 Reserved[255 - 176 + 1]; ///< 176-255 Open for Customer Use\r
+} SPD_DDR3;\r
+\r
+#pragma pack (pop)\r
+#endif\r
--- /dev/null
+/** @file\r
+ This file contains definitions for SPD DDR4.\r
+\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Revision Reference:\r
+ - Serial Presence Detect (SPD) for DDR4 SDRAM Modules Document Release 4\r
+ http://www.jedec.org/standards-documents/docs/spd412l-4\r
+**/\r
+\r
+#ifndef _SDRAM_SPD_DDR4_H_\r
+#define _SDRAM_SPD_DDR4_H_\r
+\r
+#pragma pack (push, 1)\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 BytesUsed : 4; ///< Bits 3:0\r
+ UINT8 BytesTotal : 3; ///< Bits 6:4\r
+ UINT8 CrcCoverage : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_DEVICE_DESCRIPTION_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Minor : 4; ///< Bits 3:0\r
+ UINT8 Major : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_REVISION_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Type : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_DRAM_DEVICE_TYPE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 ModuleType : 4; ///< Bits 3:0\r
+ UINT8 HybridMedia : 3; ///< Bits 6:4\r
+ UINT8 Hybrid : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_MODULE_TYPE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Density : 4; ///< Bits 3:0\r
+ UINT8 BankAddress : 2; ///< Bits 5:4\r
+ UINT8 BankGroup : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_SDRAM_DENSITY_BANKS_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 ColumnAddress : 3; ///< Bits 2:0\r
+ UINT8 RowAddress : 3; ///< Bits 5:3\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_SDRAM_ADDRESSING_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 SignalLoading : 2; ///< Bits 1:0\r
+ UINT8 Reserved : 2; ///< Bits 3:2\r
+ UINT8 DieCount : 3; ///< Bits 6:4\r
+ UINT8 SdramPackageType : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 MaximumActivateCount : 4; ///< Bits 3:0\r
+ UINT8 MaximumActivateWindow : 2; ///< Bits 5:4\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Reserved : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_SDRAM_THERMAL_REFRESH_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Reserved : 5; ///< Bits 4:0\r
+ UINT8 SoftPPR : 1; ///< Bits 5:5\r
+ UINT8 PostPackageRepair : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 SignalLoading : 2; ///< Bits 1:0\r
+ UINT8 DRAMDensityRatio : 2; ///< Bits 3:2\r
+ UINT8 DieCount : 3; ///< Bits 6:4\r
+ UINT8 SdramPackageType : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 OperationAt1_20 : 1; ///< Bits 0:0\r
+ UINT8 EndurantAt1_20 : 1; ///< Bits 1:1\r
+ UINT8 Reserved : 6; ///< Bits 7:2\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 SdramDeviceWidth : 3; ///< Bits 2:0\r
+ UINT8 RankCount : 3; ///< Bits 5:3\r
+ UINT8 RankMix : 1; ///< Bits 6:6\r
+ UINT8 Reserved : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_MODULE_ORGANIZATION_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 PrimaryBusWidth : 3; ///< Bits 2:0\r
+ UINT8 BusWidthExtension : 2; ///< Bits 4:3\r
+ UINT8 Reserved : 3; ///< Bits 7:5\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Reserved : 7; ///< Bits 6:0\r
+ UINT8 ThermalSensorPresence : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_MODULE_THERMAL_SENSOR_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 ExtendedBaseModuleType : 4; ///< Bits 3:0\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_EXTENDED_MODULE_TYPE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Fine : 2; ///< Bits 1:0\r
+ UINT8 Medium : 2; ///< Bits 3:2\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_TIMEBASE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tCKmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_TCK_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tCKmax : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_TCK_MAX_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT32 Cl7 : 1; ///< Bits 0:0\r
+ UINT32 Cl8 : 1; ///< Bits 1:1\r
+ UINT32 Cl9 : 1; ///< Bits 2:2\r
+ UINT32 Cl10 : 1; ///< Bits 3:3\r
+ UINT32 Cl11 : 1; ///< Bits 4:4\r
+ UINT32 Cl12 : 1; ///< Bits 5:5\r
+ UINT32 Cl13 : 1; ///< Bits 6:6\r
+ UINT32 Cl14 : 1; ///< Bits 7:7\r
+ UINT32 Cl15 : 1; ///< Bits 8:8\r
+ UINT32 Cl16 : 1; ///< Bits 9:9\r
+ UINT32 Cl17 : 1; ///< Bits 10:10\r
+ UINT32 Cl18 : 1; ///< Bits 11:11\r
+ UINT32 Cl19 : 1; ///< Bits 12:12\r
+ UINT32 Cl20 : 1; ///< Bits 13:13\r
+ UINT32 Cl21 : 1; ///< Bits 14:14\r
+ UINT32 Cl22 : 1; ///< Bits 15:15\r
+ UINT32 Cl23 : 1; ///< Bits 16:16\r
+ UINT32 Cl24 : 1; ///< Bits 17:17\r
+ UINT32 Cl25 : 1; ///< Bits 18:18\r
+ UINT32 Cl26 : 1; ///< Bits 19:19\r
+ UINT32 Cl27 : 1; ///< Bits 20:20\r
+ UINT32 Cl28 : 1; ///< Bits 21:21\r
+ UINT32 Cl29 : 1; ///< Bits 22:22\r
+ UINT32 Cl30 : 1; ///< Bits 23:23\r
+ UINT32 Cl31 : 1; ///< Bits 24:24\r
+ UINT32 Cl32 : 1; ///< Bits 25:25\r
+ UINT32 Cl33 : 1; ///< Bits 26:26\r
+ UINT32 Cl34 : 1; ///< Bits 27:27\r
+ UINT32 Cl35 : 1; ///< Bits 28:28\r
+ UINT32 Cl36 : 1; ///< Bits 29:29\r
+ UINT32 Reserved : 1; ///< Bits 30:30\r
+ UINT32 ClRange : 1; ///< Bits 31:31\r
+ } Bits;\r
+ struct {\r
+ UINT32 Cl23 : 1; ///< Bits 0:0\r
+ UINT32 Cl24 : 1; ///< Bits 1:1\r
+ UINT32 Cl25 : 1; ///< Bits 2:2\r
+ UINT32 Cl26 : 1; ///< Bits 3:3\r
+ UINT32 Cl27 : 1; ///< Bits 4:4\r
+ UINT32 Cl28 : 1; ///< Bits 5:5\r
+ UINT32 Cl29 : 1; ///< Bits 6:6\r
+ UINT32 Cl30 : 1; ///< Bits 7:7\r
+ UINT32 Cl31 : 1; ///< Bits 8:8\r
+ UINT32 Cl32 : 1; ///< Bits 9:9\r
+ UINT32 Cl33 : 1; ///< Bits 10:10\r
+ UINT32 Cl34 : 1; ///< Bits 11:11\r
+ UINT32 Cl35 : 1; ///< Bits 12:12\r
+ UINT32 Cl36 : 1; ///< Bits 13:13\r
+ UINT32 Cl37 : 1; ///< Bits 14:14\r
+ UINT32 Cl38 : 1; ///< Bits 15:15\r
+ UINT32 Cl39 : 1; ///< Bits 16:16\r
+ UINT32 Cl40 : 1; ///< Bits 17:17\r
+ UINT32 Cl41 : 1; ///< Bits 18:18\r
+ UINT32 Cl42 : 1; ///< Bits 19:19\r
+ UINT32 Cl43 : 1; ///< Bits 20:20\r
+ UINT32 Cl44 : 1; ///< Bits 21:21\r
+ UINT32 Cl45 : 1; ///< Bits 22:22\r
+ UINT32 Cl46 : 1; ///< Bits 23:23\r
+ UINT32 Cl47 : 1; ///< Bits 24:24\r
+ UINT32 Cl48 : 1; ///< Bits 25:25\r
+ UINT32 Cl49 : 1; ///< Bits 26:26\r
+ UINT32 Cl50 : 1; ///< Bits 27:27\r
+ UINT32 Cl51 : 1; ///< Bits 28:28\r
+ UINT32 Cl52 : 1; ///< Bits 29:29\r
+ UINT32 Reserved : 1; ///< Bits 30:30\r
+ UINT32 ClRange : 1; ///< Bits 31:31\r
+ } HighRangeBits;\r
+ UINT32 Data;\r
+ UINT16 Data16[2];\r
+ UINT8 Data8[4];\r
+} SPD4_CAS_LATENCIES_SUPPORTED_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tAAmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_TAA_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tRCDmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_TRCD_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tRPmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_TRP_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tRASminUpper : 4; ///< Bits 3:0\r
+ UINT8 tRCminUpper : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_TRAS_TRC_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tRASmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_TRAS_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tRCmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_TRC_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT16 tRFCmin : 16; ///< Bits 15:0\r
+ } Bits;\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
+} SPD4_TRFC_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tFAWminUpper : 4; ///< Bits 3:0\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_TFAW_MIN_MTB_UPPER_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tFAWmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_TFAW_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tRRDmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_TRRD_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tCCDmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_TCCD_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tWRminMostSignificantNibble : 4; ///< Bits 3:0\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_TWR_UPPER_NIBBLE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tWRmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_TWR_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tWTR_SminMostSignificantNibble : 4; ///< Bits 3:0\r
+ UINT8 tWTR_LminMostSignificantNibble : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_TWTR_UPPER_NIBBLE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tWTRmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_TWTR_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 BitOrderatSDRAM : 5; ///< Bits 4:0\r
+ UINT8 WiredtoUpperLowerNibble : 1; ///< Bits 5:5\r
+ UINT8 PackageRankMap : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tCCDminFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD4_TCCD_MIN_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tRRDminFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD4_TRRD_MIN_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tRCminFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD4_TRC_MIN_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tRPminFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD4_TRP_MIN_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tRCDminFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD4_TRCD_MIN_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tAAminFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD4_TAA_MIN_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tCKmaxFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD4_TCK_MAX_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tCKminFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD4_TCK_MIN_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Height : 5; ///< Bits 4:0\r
+ UINT8 RawCardExtension : 3; ///< Bits 7:5\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_UNBUF_MODULE_NOMINAL_HEIGHT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 FrontThickness : 4; ///< Bits 3:0\r
+ UINT8 BackThickness : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_UNBUF_MODULE_NOMINAL_THICKNESS;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Card : 5; ///< Bits 4:0\r
+ UINT8 Revision : 2; ///< Bits 6:5\r
+ UINT8 Extension : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_UNBUF_REFERENCE_RAW_CARD;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 MappingRank1 : 1; ///< Bits 0:0\r
+ UINT8 Reserved : 7; ///< Bits 7:1\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_UNBUF_ADDRESS_MAPPING;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Height : 5; ///< Bits 4:0\r
+ UINT8 Reserved : 3; ///< Bits 7:5\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_RDIMM_MODULE_NOMINAL_HEIGHT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 FrontThickness : 4; ///< Bits 3:0\r
+ UINT8 BackThickness : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_RDIMM_MODULE_NOMINAL_THICKNESS;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Card : 5; ///< Bits 4:0\r
+ UINT8 Revision : 2; ///< Bits 6:5\r
+ UINT8 Extension : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_RDIMM_REFERENCE_RAW_CARD;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 RegisterCount : 2; ///< Bits 1:0\r
+ UINT8 DramRowCount : 2; ///< Bits 3:2\r
+ UINT8 RegisterType : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_RDIMM_MODULE_ATTRIBUTES;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0\r
+ UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT16 ContinuationCount : 7; ///< Bits 6:0\r
+ UINT16 ContinuationParity : 1; ///< Bits 7:7\r
+ UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r
+ } Bits;\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
+} SPD4_MANUFACTURER_ID_CODE;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 RegisterRevisionNumber; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_RDIMM_REGISTER_REVISION_NUMBER;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Rank1Mapping : 1; ///< Bits 0:0\r
+ UINT8 Reserved : 7; ///< Bits 7:1\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Cke : 2; ///< Bits 1:0\r
+ UINT8 Odt : 2; ///< Bits 3:2\r
+ UINT8 CommandAddress : 2; ///< Bits 5:4\r
+ UINT8 ChipSelect : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Y0Y2 : 2; ///< Bits 1:0\r
+ UINT8 Y1Y3 : 2; ///< Bits 3:2\r
+ UINT8 Reserved0 : 2; ///< Bits 5:4\r
+ UINT8 RcdOutputSlewRateControl : 1; ///< Bits 6:6\r
+ UINT8 Reserved1 : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Height : 5; ///< Bits 4:0\r
+ UINT8 Reserved : 3; ///< Bits 7:5\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 FrontThickness : 4; ///< Bits 3:0\r
+ UINT8 BackThickness : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Card : 5; ///< Bits 4:0\r
+ UINT8 Revision : 2; ///< Bits 6:5\r
+ UINT8 Extension : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_LRDIMM_REFERENCE_RAW_CARD;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 RegisterCount : 2; ///< Bits 1:0\r
+ UINT8 DramRowCount : 2; ///< Bits 3:2\r
+ UINT8 RegisterType : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_LRDIMM_MODULE_ATTRIBUTES;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0\r
+ UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 RegisterRevisionNumber; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_LRDIMM_REGISTER_REVISION_NUMBER;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Rank1Mapping : 1; ///< Bits 0:0\r
+ UINT8 Reserved : 7; ///< Bits 7:1\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Cke : 2; ///< Bits 1:0\r
+ UINT8 Odt : 2; ///< Bits 3:2\r
+ UINT8 CommandAddress : 2; ///< Bits 5:4\r
+ UINT8 ChipSelect : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Y0Y2 : 2; ///< Bits 1:0\r
+ UINT8 Y1Y3 : 2; ///< Bits 3:2\r
+ UINT8 Reserved0 : 2; ///< Bits 5:4\r
+ UINT8 RcdOutputSlewRateControl : 1; ///< Bits 6:6\r
+ UINT8 Reserved1 : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK;\r
+\r
+typedef struct {\r
+ UINT8 DataBufferRevisionNumber;\r
+} SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 DramVrefDQForPackageRank0 : 6; ///< Bits 5:0\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK;\r
+\r
+typedef struct {\r
+ UINT8 DataBufferVrefDQforDramInterface;\r
+} SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 DramInterfaceMdqDriveStrength : 4; ///< Bits 3:0\r
+ UINT8 DramInterfaceMdqReadTerminationStrength : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 DataRateLe1866 : 2; ///< Bits 1:0\r
+ UINT8 DataRateLe2400 : 2; ///< Bits 3:2\r
+ UINT8 DataRateLe3200 : 2; ///< Bits 5:4\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_LRDIMM_DRAM_DRIVE_STRENGTH;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Rtt_Nom : 3; ///< Bits 2:0\r
+ UINT8 Rtt_WR : 3; ///< Bits 5:3\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 PackageRanks0_1 : 3; ///< Bits 2:0\r
+ UINT8 PackageRanks2_3 : 3; ///< Bits 5:3\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Rank0 : 1; ///< Bits 0:0\r
+ UINT8 Rank1 : 1; ///< Bits 1:1\r
+ UINT8 Rank2 : 1; ///< Bits 2:2\r
+ UINT8 Rank3 : 1; ///< Bits 3:3\r
+ UINT8 DataBuffer : 1; ///< Bits 4:4\r
+ UINT8 Reserved : 3; ///< Bits 7:5\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 DataBufferGainAdjustment : 1; ///< Bits 0:0\r
+ UINT8 DataBufferDfe : 1; ///< Bits 1:1\r
+ UINT8 Reserved : 6; ///< Bits 7:2\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION;\r
+\r
+typedef UINT16 SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT16 ContinuationCount : 7; ///< Bits 6:0\r
+ UINT16 ContinuationParity : 1; ///< Bits 7:7\r
+ UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r
+ } Bits;\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
+} SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE;\r
+\r
+typedef UINT16 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER;\r
+\r
+typedef UINT8 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Card : 5; ///< Bits 4:0\r
+ UINT8 Revision : 2; ///< Bits 6:5\r
+ UINT8 Extension : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_NVDIMM_REFERENCE_RAW_CARD;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Reserved : 4; ///< Bits 3:0\r
+ UINT8 Extension : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD4_NVDIMM_MODULE_CHARACTERISTICS;\r
+\r
+typedef struct {\r
+ UINT8 Reserved;\r
+ UINT8 MediaType;\r
+} SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES;\r
+\r
+typedef UINT8 SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT16 FunctionInterface : 5; ///< Bits 4:0\r
+ UINT16 FunctionClass : 5; ///< Bits 9:5\r
+ UINT16 BlockOffset : 4; ///< Bits 13:10\r
+ UINT16 Reserved : 1; ///< Bits 14:14\r
+ UINT16 Implemented : 1; ///< Bits 15:15\r
+ } Bits;\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
+} SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR;\r
+\r
+typedef struct {\r
+ UINT8 Year; ///< Year represented in BCD (00h = 2000)\r
+ UINT8 Week; ///< Year represented in BCD (47h = week 47)\r
+} SPD4_MANUFACTURING_DATE;\r
+\r
+typedef union {\r
+ UINT32 Data;\r
+ UINT16 SerialNumber16[2];\r
+ UINT8 SerialNumber8[4];\r
+} SPD4_MANUFACTURER_SERIAL_NUMBER;\r
+\r
+typedef struct {\r
+ UINT8 Location; ///< Module Manufacturing Location\r
+} SPD4_MANUFACTURING_LOCATION;\r
+\r
+typedef struct {\r
+ SPD4_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code\r
+ SPD4_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location\r
+ SPD4_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)\r
+ SPD4_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number\r
+} SPD4_UNIQUE_MODULE_ID;\r
+\r
+typedef union {\r
+ UINT16 Crc[1];\r
+ UINT8 Data8[2];\r
+} SPD4_CYCLIC_REDUNDANCY_CODE;\r
+\r
+typedef struct {\r
+ SPD4_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2\r
+ SPD4_REVISION_STRUCT Revision; ///< 1 SPD Revision\r
+ SPD4_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type\r
+ SPD4_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type\r
+ SPD4_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks\r
+ SPD4_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing\r
+ SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT PrimarySdramPackageType; ///< 6 Primary SDRAM Package Type\r
+ SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 7 SDRAM Optional Features\r
+ SPD4_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options\r
+ SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures; ///< 9 Other SDRAM Optional Features\r
+ SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT SecondarySdramPackageType;///< 10 Secondary SDRAM Package Type\r
+ SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD\r
+ SPD4_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization\r
+ SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width\r
+ SPD4_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor\r
+ SPD4_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType; ///< 15 Extended Module Type\r
+ UINT8 Reserved0; ///< 16 Reserved\r
+ SPD4_TIMEBASE_STRUCT Timebase; ///< 17 Timebases\r
+ SPD4_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin)\r
+ SPD4_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax)\r
+ SPD4_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported\r
+ SPD4_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin)\r
+ SPD4_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 25 Minimum RAS# to CAS# Delay Time (tRCDmin)\r
+ SPD4_TRP_MIN_MTB_STRUCT tRPmin; ///< 26 Minimum Row Precharge Delay Time (tRPmin)\r
+ SPD4_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 27 Upper Nibbles for tRAS and tRC\r
+ SPD4_TRAS_MIN_MTB_STRUCT tRASmin; ///< 28 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte\r
+ SPD4_TRC_MIN_MTB_STRUCT tRCmin; ///< 29 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte\r
+ SPD4_TRFC_MIN_MTB_STRUCT tRFC1min; ///< 30-31 Minimum Refresh Recovery Delay Time (tRFC1min)\r
+ SPD4_TRFC_MIN_MTB_STRUCT tRFC2min; ///< 32-33 Minimum Refresh Recovery Delay Time (tRFC2min)\r
+ SPD4_TRFC_MIN_MTB_STRUCT tRFC4min; ///< 34-35 Minimum Refresh Recovery Delay Time (tRFC4min)\r
+ SPD4_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 36 Upper Nibble for tFAW\r
+ SPD4_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 37 Minimum Four Activate Window Delay Time (tFAWmin)\r
+ SPD4_TRRD_MIN_MTB_STRUCT tRRD_Smin; ///< 38 Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group\r
+ SPD4_TRRD_MIN_MTB_STRUCT tRRD_Lmin; ///< 39 Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group\r
+ SPD4_TCCD_MIN_MTB_STRUCT tCCD_Lmin; ///< 40 Minimum CAS to CAS Delay Time (tCCD_Lmin), Same Bank Group\r
+ SPD4_TWR_UPPER_NIBBLE_STRUCT tWRUpperNibble; ///< 41 Upper Nibble for tWRmin\r
+ SPD4_TWR_MIN_MTB_STRUCT tWRmin; ///< 42 Minimum Write Recovery Time (tWRmin)\r
+ SPD4_TWTR_UPPER_NIBBLE_STRUCT tWTRUpperNibble; ///< 43 Upper Nibbles for tWTRmin\r
+ SPD4_TWTR_MIN_MTB_STRUCT tWTR_Smin; ///< 44 Minimum Write to Read Time (tWTR_Smin), Different Bank Group\r
+ SPD4_TWTR_MIN_MTB_STRUCT tWTR_Lmin; ///< 45 Minimum Write to Read Time (tWTR_Lmin), Same Bank Group\r
+ UINT8 Reserved1[59 - 46 + 1]; ///< 46-59 Reserved\r
+ SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping\r
+ UINT8 Reserved2[116 - 78 + 1]; ///< 78-116 Reserved\r
+ SPD4_TCCD_MIN_FTB_STRUCT tCCD_LminFine; ///< 117 Fine Offset for Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group\r
+ SPD4_TRRD_MIN_FTB_STRUCT tRRD_LminFine; ///< 118 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), different bank group\r
+ SPD4_TRRD_MIN_FTB_STRUCT tRRD_SminFine; ///< 119 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), same bank group\r
+ SPD4_TRC_MIN_FTB_STRUCT tRCminFine; ///< 120 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)\r
+ SPD4_TRP_MIN_FTB_STRUCT tRPminFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabmin)\r
+ SPD4_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)\r
+ SPD4_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)\r
+ SPD4_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax)\r
+ SPD4_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Maximum Cycle Time (tCKmin)\r
+ SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)\r
+} SPD4_BASE_SECTION;\r
+\r
+typedef struct {\r
+ SPD4_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height\r
+ SPD4_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness\r
+ SPD4_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used\r
+ SPD4_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 131 Address Mapping from Edge Connector to DRAM\r
+ UINT8 Reserved[253 - 132 + 1]; ///< 132-253 Reserved\r
+ SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r
+} SPD4_MODULE_UNBUFFERED;\r
+\r
+typedef struct {\r
+ SPD4_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height\r
+ SPD4_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness\r
+ SPD4_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used\r
+ SPD4_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 DIMM Module Attributes\r
+ SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION DimmThermalHeatSpreaderSolution; ///< 132 RDIMM Thermal Heat Spreader Solution\r
+ SPD4_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 133-134 Register Manufacturer ID Code\r
+ SPD4_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 135 Register Revision Number\r
+ SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDRAM; ///< 136 Address Mapping from Register to DRAM\r
+ SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress; ///< 137 Register Output Drive Strength for Control and Command Address\r
+ SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock; ///< 138 Register Output Drive Strength for Clock\r
+ UINT8 Reserved[253 - 139 + 1]; ///< 253-139 Reserved\r
+ SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r
+} SPD4_MODULE_REGISTERED;\r
+\r
+typedef struct {\r
+ SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height\r
+ SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness\r
+ SPD4_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used\r
+ SPD4_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 DIMM Module Attributes\r
+ SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution; ///< 132 RDIMM Thermal Heat Spreader Solution\r
+ SPD4_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 133-134 Register Manufacturer ID Code\r
+ SPD4_LRDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 135 Register Revision Number\r
+ SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDram; ///< 136 Address Mapping from Register to DRAM\r
+ SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress; ///< 137 Register Output Drive Strength for Control and Command Address\r
+ SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock; ///< 138 Register Output Drive Strength for Clock\r
+ SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER DataBufferRevisionNumber; ///< 139 Data Buffer Revision Number\r
+ SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank0; ///< 140 DRAM VrefDQ for Package Rank 0\r
+ SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank1; ///< 141 DRAM VrefDQ for Package Rank 1\r
+ SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank2; ///< 142 DRAM VrefDQ for Package Rank 2\r
+ SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank3; ///< 143 DRAM VrefDQ for Package Rank 3\r
+ SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE DataBufferVrefDQForDramInterface; ///< 144 Data Buffer VrefDQ for DRAM Interface\r
+ SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe1866; ///< 145 Data Buffer MDQ Drive Strength and RTT for data rate <= 1866\r
+ SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe2400; ///< 146 Data Buffer MDQ Drive Strength and RTT for data rate <=2400\r
+ SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe3200; ///< 147 Data Buffer MDQ Drive Strength and RTT for data rate <=3200\r
+ SPD4_LRDIMM_DRAM_DRIVE_STRENGTH DramDriveStrength; ///< 148 DRAM Drive Strength\r
+ SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe1866; ///< 149 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 1866\r
+ SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe2400; ///< 150 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 2400\r
+ SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe3200; ///< 151 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 3200\r
+ SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe1866; ///< 152 DRAM ODT (RTT_PARK) for data rate <= 1866\r
+ SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe2400; ///< 153 DRAM ODT (RTT_PARK) for data rate <= 2400\r
+ SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe3200; ///< 154 DRAM ODT (RTT_PARK) for data rate <= 3200\r
+ SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE DataBufferVrefDQForDramInterfaceRange; ///< 155 Data Buffer VrefDQ for DRAM Interface Range\r
+ SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION DataBufferDqDecisionFeedbackEqualization; ///< 156 Data Buffer DQ Decision Feedback Equalization\r
+ UINT8 Reserved[253 - 157 + 1]; ///< 253-132 Reserved\r
+ SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r
+} SPD4_MODULE_LOADREDUCED;\r
+\r
+typedef struct {\r
+ UINT8 Reserved0[191 - 128 + 1]; ///< 128-191 Reserved\r
+ SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER ModuleProductIdentifier; ///< 192-193 Module Product Identifier\r
+ SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE SubsystemControllerManufacturerIdCode; ///< 194-195 Subsystem Controller Manufacturer's ID Code\r
+ SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER SubsystemControllerIdentifier; ///< 196-197 Subsystem Controller Identifier\r
+ SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE SubsystemControllerRevisionCode; ///< 198 Subsystem Controller Revision Code\r
+ SPD4_NVDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 199 Reference Raw Card Used\r
+ SPD4_NVDIMM_MODULE_CHARACTERISTICS ModuleCharacteristics; ///< 200 Module Characteristics\r
+ SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES HybridModuleMediaTypes; ///< 201-202 Hybrid Module Media Types\r
+ SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME MaximumNonVolatileMemoryInitializationTime; ///< 203 Maximum Non-Volatile Memory Initialization Time\r
+ SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR FunctionInterfaceDescriptors[8]; ///< 204-219 Function Interface Descriptors\r
+ UINT8 Reserved[253 - 220 + 1]; ///< 220-253 Reserved\r
+ SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r
+} SPD4_MODULE_NVDIMM;\r
+\r
+typedef union {\r
+ SPD4_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types\r
+ SPD4_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types\r
+ SPD4_MODULE_LOADREDUCED LoadReduced; ///< 128-255 Load Reduced Memory Module Types\r
+ SPD4_MODULE_NVDIMM NonVolatile; ///< 128-255 Non-Volatile (NVDIMM-N) Hybrid Memory Parameters\r
+} SPD4_MODULE_SPECIFIC;\r
+\r
+typedef struct {\r
+ UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number\r
+} SPD4_MODULE_PART_NUMBER;\r
+\r
+typedef struct {\r
+ UINT8 ManufacturerSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data\r
+} SPD4_MANUFACTURER_SPECIFIC;\r
+\r
+typedef UINT8 SPD4_MODULE_REVISION_CODE;///< 349 Module Revision Code\r
+typedef UINT8 SPD4_DRAM_STEPPING; ///< 352 Dram Stepping\r
+\r
+typedef struct {\r
+ SPD4_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID\r
+ SPD4_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number\r
+ SPD4_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code\r
+ SPD4_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code\r
+ SPD4_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping\r
+ SPD4_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 353-381 Manufacturer's Specific Data\r
+ UINT8 Reserved[2]; ///< 382-383 Reserved\r
+} SPD4_MANUFACTURING_DATA;\r
+\r
+typedef struct {\r
+ UINT8 Reserved[511 - 384 + 1]; ///< 384-511 Unbuffered Memory Module Types\r
+} SPD4_END_USER_SECTION;\r
+\r
+///\r
+/// DDR4 Serial Presence Detect structure\r
+///\r
+typedef struct {\r
+ SPD4_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters\r
+ SPD4_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section\r
+ UINT8 Reserved[319 - 256 + 1]; ///< 256-319 Reserved\r
+ SPD4_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information\r
+ SPD4_END_USER_SECTION EndUser; ///< 384-511 End User Programmable\r
+} SPD_DDR4;\r
+\r
+#pragma pack (pop)\r
+#endif\r
--- /dev/null
+/** @file\r
+ This file contains definitions for SPD LPDDR.\r
+\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Revision Reference:\r
+ - Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules Document Release 2\r
+ http://www.jedec.org/standards-documents/docs/spd412m-2\r
+**/\r
+\r
+#ifndef _SDRAM_SPD_LPDDR_H_\r
+#define _SDRAM_SPD_LPDDR_H_\r
+\r
+#pragma pack (push, 1)\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 BytesUsed : 4; ///< Bits 3:0\r
+ UINT8 BytesTotal : 3; ///< Bits 6:4\r
+ UINT8 CrcCoverage : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Minor : 4; ///< Bits 3:0\r
+ UINT8 Major : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_REVISION_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Type : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 ModuleType : 4; ///< Bits 3:0\r
+ UINT8 HybridMedia : 3; ///< Bits 6:4\r
+ UINT8 Hybrid : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_MODULE_TYPE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Density : 4; ///< Bits 3:0\r
+ UINT8 BankAddress : 2; ///< Bits 5:4\r
+ UINT8 BankGroup : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 ColumnAddress : 3; ///< Bits 2:0\r
+ UINT8 RowAddress : 3; ///< Bits 5:3\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_SDRAM_ADDRESSING_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 SignalLoading : 2; ///< Bits 1:0\r
+ UINT8 ChannelsPerDie : 2; ///< Bits 3:2\r
+ UINT8 DieCount : 3; ///< Bits 6:4\r
+ UINT8 SdramPackageType : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 MaximumActivateCount : 4; ///< Bits 3:0\r
+ UINT8 MaximumActivateWindow : 2; ///< Bits 5:4\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Reserved : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Reserved : 5; ///< Bits 4:0\r
+ UINT8 SoftPPR : 1; ///< Bits 5:5\r
+ UINT8 PostPackageRepair : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 OperationAt1_20 : 1; ///< Bits 0:0\r
+ UINT8 EndurantAt1_20 : 1; ///< Bits 1:1\r
+ UINT8 OperationAt1_10 : 1; ///< Bits 2:2\r
+ UINT8 EndurantAt1_10 : 1; ///< Bits 3:3\r
+ UINT8 OperationAtTBD2V : 1; ///< Bits 4:4\r
+ UINT8 EndurantAtTBD2V : 1; ///< Bits 5:5\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 SdramDeviceWidth : 3; ///< Bits 2:0\r
+ UINT8 RankCount : 3; ///< Bits 5:3\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_MODULE_ORGANIZATION_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 PrimaryBusWidth : 3; ///< Bits 2:0\r
+ UINT8 BusWidthExtension : 2; ///< Bits 4:3\r
+ UINT8 NumberofChannels : 3; ///< Bits 7:5\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Reserved : 7; ///< Bits 6:0\r
+ UINT8 ThermalSensorPresence : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 ExtendedBaseModuleType : 4; ///< Bits 3:0\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 ChipSelectLoading : 3; ///< Bits 2:0\r
+ UINT8 CommandAddressControlClockLoading : 3; ///< Bits 5:3\r
+ UINT8 DataStrobeMaskLoading : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_SIGNAL_LOADING_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Fine : 2; ///< Bits 1:0\r
+ UINT8 Medium : 2; ///< Bits 3:2\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_TIMEBASE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tCKmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_TCK_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tCKmax : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_TCK_MAX_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT32 Cl3 : 1; ///< Bits 0:0\r
+ UINT32 Cl6 : 1; ///< Bits 1:1\r
+ UINT32 Cl8 : 1; ///< Bits 2:2\r
+ UINT32 Cl9 : 1; ///< Bits 3:3\r
+ UINT32 Cl10 : 1; ///< Bits 4:4\r
+ UINT32 Cl11 : 1; ///< Bits 5:5\r
+ UINT32 Cl12 : 1; ///< Bits 6:6\r
+ UINT32 Cl14 : 1; ///< Bits 7:7\r
+ UINT32 Cl16 : 1; ///< Bits 8:8\r
+ UINT32 Reserved0 : 1; ///< Bits 9:9\r
+ UINT32 Cl20 : 1; ///< Bits 10:10\r
+ UINT32 Cl22 : 1; ///< Bits 11:11\r
+ UINT32 Cl24 : 1; ///< Bits 12:12\r
+ UINT32 Reserved1 : 1; ///< Bits 13:13\r
+ UINT32 Cl28 : 1; ///< Bits 14:14\r
+ UINT32 Reserved2 : 1; ///< Bits 15:15\r
+ UINT32 Cl32 : 1; ///< Bits 16:16\r
+ UINT32 Reserved3 : 1; ///< Bits 17:17\r
+ UINT32 Cl36 : 1; ///< Bits 18:18\r
+ UINT32 Reserved4 : 1; ///< Bits 19:19\r
+ UINT32 Cl40 : 1; ///< Bits 20:20\r
+ UINT32 Reserved5 : 11; ///< Bits 31:21\r
+ } Bits;\r
+ UINT32 Data;\r
+ UINT16 Data16[2];\r
+ UINT8 Data8[4];\r
+} SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tAAmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_TAA_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 ReadLatencyMode : 2; ///< Bits 1:0\r
+ UINT8 WriteLatencySet : 2; ///< Bits 3:2\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_RW_LATENCY_OPTION_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tRCDmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_TRCD_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tRPab : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_TRP_AB_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tRPpb : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_TRP_PB_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT16 tRFCab : 16; ///< Bits 15:0\r
+ } Bits;\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
+} SPD_LPDDR_TRFC_AB_MTB_STRUCT;\r
+\r
+typedef union {\r
+struct {\r
+ UINT16 tRFCpb : 16; ///< Bits 15:0\r
+ } Bits;\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
+} SPD_LPDDR_TRFC_PB_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 BitOrderatSDRAM : 5; ///< Bits 4:0\r
+ UINT8 WiredtoUpperLowerNibble : 1; ///< Bits 5:5\r
+ UINT8 PackageRankMap : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tRPpbFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD_LPDDR_TRP_PB_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tRPabFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD_LPDDR_TRP_AB_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tRCDminFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD_LPDDR_TRCD_MIN_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tAAminFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD_LPDDR_TAA_MIN_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tCKmaxFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD_LPDDR_TCK_MAX_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tCKminFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD_LPDDR_TCK_MIN_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT16 ContinuationCount : 7; ///< Bits 6:0\r
+ UINT16 ContinuationParity : 1; ///< Bits 7:7\r
+ UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r
+ } Bits;\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
+} SPD_LPDDR_MANUFACTURER_ID_CODE;\r
+\r
+typedef struct {\r
+ UINT8 Location; ///< Module Manufacturing Location\r
+} SPD_LPDDR_MANUFACTURING_LOCATION;\r
+\r
+typedef struct {\r
+ UINT8 Year; ///< Year represented in BCD (00h = 2000)\r
+ UINT8 Week; ///< Year represented in BCD (47h = week 47)\r
+} SPD_LPDDR_MANUFACTURING_DATE;\r
+\r
+typedef union {\r
+ UINT32 Data;\r
+ UINT16 SerialNumber16[2];\r
+ UINT8 SerialNumber8[4];\r
+} SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER;\r
+\r
+typedef struct {\r
+ SPD_LPDDR_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code\r
+ SPD_LPDDR_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location\r
+ SPD_LPDDR_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)\r
+ SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number\r
+} SPD_LPDDR_UNIQUE_MODULE_ID;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 FrontThickness : 4; ///< Bits 3:0\r
+ UINT8 BackThickness : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_MODULE_MAXIMUM_THICKNESS;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Height : 5; ///< Bits 4:0\r
+ UINT8 RawCardExtension : 3; ///< Bits 7:5\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_MODULE_NOMINAL_HEIGHT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Card : 5; ///< Bits 4:0\r
+ UINT8 Revision : 2; ///< Bits 6:5\r
+ UINT8 Extension : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_REFERENCE_RAW_CARD;\r
+\r
+typedef union {\r
+ UINT16 Crc[1];\r
+ UINT8 Data8[2];\r
+} SPD_LPDDR_CYCLIC_REDUNDANCY_CODE;\r
+\r
+typedef struct {\r
+ SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2\r
+ SPD_LPDDR_REVISION_STRUCT Revision; ///< 1 SPD Revision\r
+ SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type\r
+ SPD_LPDDR_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type\r
+ SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks\r
+ SPD_LPDDR_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing\r
+ SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT SdramPackageType; ///< 6 SDRAM Package Type\r
+ SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 7 SDRAM Optional Features\r
+ SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options\r
+ SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures; ///< 9 Other SDRAM Optional Features\r
+ UINT8 Reserved0; ///< 10 Reserved\r
+ SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD\r
+ SPD_LPDDR_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization\r
+ SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width\r
+ SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor\r
+ SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType; ///< 15 Extended Module Type\r
+ SPD_LPDDR_SIGNAL_LOADING_STRUCT SignalLoading; ///< 16 Signal Loading\r
+ SPD_LPDDR_TIMEBASE_STRUCT Timebase; ///< 17 Timebases\r
+ SPD_LPDDR_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin)\r
+ SPD_LPDDR_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax)\r
+ SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported\r
+ SPD_LPDDR_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin)\r
+ SPD_LPDDR_RW_LATENCY_OPTION_STRUCT LatencySetOptions; ///< 25 Read and Write Latency Set Options\r
+ SPD_LPDDR_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin)\r
+ SPD_LPDDR_TRP_AB_MTB_STRUCT tRPab; ///< 27 Minimum Row Precharge Delay Time (tRPab), all banks\r
+ SPD_LPDDR_TRP_PB_MTB_STRUCT tRPpb; ///< 28 Minimum Row Precharge Delay Time (tRPpb), per bank\r
+ SPD_LPDDR_TRFC_AB_MTB_STRUCT tRFCab; ///< 29-30 Minimum Refresh Recovery Delay Time (tRFCab), all banks\r
+ SPD_LPDDR_TRFC_PB_MTB_STRUCT tRFCpb; ///< 31-32 Minimum Refresh Recovery Delay Time (tRFCpb), per bank\r
+ UINT8 Reserved1[59 - 33 + 1]; ///< 33-59 Reserved\r
+ SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping\r
+ UINT8 Reserved2[119 - 78 + 1]; ///< 78-119 Reserved\r
+ SPD_LPDDR_TRP_PB_FTB_STRUCT tRPpbFine; ///< 120 Fine Offset for Minimum Row Precharge Delay Time (tRPpbFine), per bank\r
+ SPD_LPDDR_TRP_AB_FTB_STRUCT tRPabFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabFine), all ranks\r
+ SPD_LPDDR_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)\r
+ SPD_LPDDR_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)\r
+ SPD_LPDDR_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Maximum Cycle Time (tCKmax)\r
+ SPD_LPDDR_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)\r
+ SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)\r
+} SPD_LPDDR_BASE_SECTION;\r
+\r
+typedef struct {\r
+ SPD_LPDDR_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height\r
+ SPD_LPDDR_MODULE_MAXIMUM_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness\r
+ SPD_LPDDR_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used\r
+ UINT8 Reserved[253 - 131 + 1]; ///< 131-253 Reserved\r
+ SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r
+} SPD_LPDDR_MODULE_LPDIMM;\r
+\r
+typedef struct {\r
+ SPD_LPDDR_MODULE_LPDIMM LpDimm; ///< 128-255 Unbuffered Memory Module Types\r
+} SPD_LPDDR_MODULE_SPECIFIC;\r
+\r
+typedef struct {\r
+ UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number\r
+} SPD_LPDDR_MODULE_PART_NUMBER;\r
+\r
+typedef struct {\r
+ UINT8 ManufacturerSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data\r
+} SPD_LPDDR_MANUFACTURER_SPECIFIC;\r
+\r
+typedef UINT8 SPD_LPDDR_MODULE_REVISION_CODE;///< 349 Module Revision Code\r
+typedef UINT8 SPD_LPDDR_DRAM_STEPPING; ///< 352 Dram Stepping\r
+\r
+typedef struct {\r
+ SPD_LPDDR_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID\r
+ SPD_LPDDR_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number\r
+ SPD_LPDDR_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code\r
+ SPD_LPDDR_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code\r
+ SPD_LPDDR_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping\r
+ SPD_LPDDR_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 353-381 Manufacturer's Specific Data\r
+ UINT8 Reserved[383 - 382 + 1]; ///< 382-383 Reserved\r
+} SPD_LPDDR_MANUFACTURING_DATA;\r
+\r
+typedef struct {\r
+ UINT8 Reserved[511 - 384 + 1]; ///< 384-511 End User Programmable\r
+} SPD_LPDDR_END_USER_SECTION;\r
+\r
+///\r
+/// LPDDR Serial Presence Detect structure\r
+///\r
+typedef struct {\r
+ SPD_LPDDR_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters\r
+ SPD_LPDDR_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section\r
+ UINT8 Reserved[319 - 256 + 1]; ///< 256-319 Hybrid Memory Parameters\r
+ SPD_LPDDR_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information\r
+ SPD_LPDDR_END_USER_SECTION EndUser; ///< 384-511 End User Programmable\r
+} SPD_LPDDR;\r
+\r
+#pragma pack (pop)\r
+#endif\r
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