;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
call eax\r
add esp, 4\r
\r
- mov eax, gStmXdSupported\r
+ mov eax, offset gStmXdSupported\r
mov al, [eax]\r
cmp al, 0\r
jz @f\r
; Check XD disable bit\r
;\r
xor esi, esi\r
- mov eax, gStmXdSupported\r
+ mov eax, offset gStmXdSupported\r
mov al, [eax]\r
cmp al, 0\r
jz @StmXdDone\r
;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
EXTERNDEF SmmStmExceptionHandler:PROC\r
EXTERNDEF SmmStmSetup:PROC\r
EXTERNDEF SmmStmTeardown:PROC\r
+EXTERNDEF gStmXdSupported:BYTE\r
\r
CODE_SEL = 08h\r
DATA_SEL = 20h\r
TSS_SEL = 40h\r
\r
+MSR_IA32_MISC_ENABLE EQU 1A0h\r
+MSR_EFER EQU 0c0000080h\r
+MSR_EFER_XD EQU 0800h\r
+\r
.data\r
\r
gcStmPsd LABEL BYTE\r
; Check XD disable bit\r
;\r
xor esi, esi\r
- mov eax, gStmXdSupported\r
+ mov eax, offset gStmXdSupported\r
mov al, [eax]\r
cmp al, 0\r
jz @StmXdDone1\r
\r
call SmmStmSetup\r
\r
- mov eax, gStmXdSupported\r
+ mov eax, offset gStmXdSupported\r
mov al, [eax]\r
cmp al, 0\r
jz @f\r
; Check XD disable bit\r
;\r
xor esi, esi\r
- mov eax, gStmXdSupported\r
+ mov eax, offset gStmXdSupported\r
mov al, [eax]\r
cmp al, 0\r
jz @StmXdDone2\r
\r
call SmmStmTeardown\r
\r
- mov eax, gStmXdSupported\r
+ mov eax, offset gStmXdSupported\r
mov al, [eax]\r
cmp al, 0\r
jz @f\r