If IDE controller is not in IDE mode, we should not clear IO bar.

Signed-off-by: Li Elvin <elvin.li@intel.com>
Reviewed-by: Yao Jiewen <jiewen.yao@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13953 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h
index 7e1a6063ef369d4b5a63b611e63485da2a8d3cd6..6ea3a1c89467f09d882015b07e376ea47486396d 100644 (file)
--- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h
+++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h
@@ -18,6 +18,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 \r
 \r
 #include <FrameworkDxe.h>\r
+#include <IndustryStandard\Pci.h>\r
 \r
 #include <Guid/SmBios.h>\r
 #include <Guid/Acpi.h>\r
@@ -134,6 +135,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 \r
 #define BDA_VIDEO_MODE      0x49\r
 \r
+#define IDE_PI_REGISTER_PNE     BIT0\r
+#define IDE_PI_REGISTER_SNE     BIT2\r
+\r
 typedef struct {\r
   UINTN   PciSegment;\r
   UINTN   PciBus;\r

diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyIde.c b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyIde.c
index 4e52fe9c03a96eb190d4bd076aa39fae99d8c56e..255baf08c69601c65d131a98ee66206816de5e25 100644 (file)
--- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyIde.c
+++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyIde.c
@@ -268,9 +268,9 @@ InitLegacyIdeController (
   )\r
 {\r
   EFI_PCI_IO_PROTOCOL               *PciIo;\r
-  UINT8                             Pi;\r
   UINT32                            IOBarClear;\r
   EFI_STATUS                        Status;\r
+  PCI_TYPE00                        PciData;\r
 \r
   //\r
   // If the IDE channel is in compatibility (legacy) mode, remove all\r
@@ -279,21 +279,38 @@ InitLegacyIdeController (
   // and has PCI I/O resources allocated\r
   //\r
   Status = gBS->HandleProtocol (\r
-                  IdeController,\r
-                  &gEfiPciIoProtocolGuid,\r
-                  (VOID **) &PciIo\r
+                  IdeController, \r
+                  &gEfiPciIoProtocolGuid, \r
+                  &PciIo\r
                   );\r
-  if (!EFI_ERROR (Status)) {\r
-    IOBarClear = 0x00;\r
-    PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x09, 1, &Pi);\r
-    if ((Pi & 0x01) == 0) {\r
-      PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x10, 1, &IOBarClear);\r
-      PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x14, 1, &IOBarClear);\r
-    }\r
-    if ((Pi & 0x04) == 0) {\r
-      PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x18, 1, &IOBarClear);\r
-      PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x1C, 1, &IOBarClear);\r
-    }\r
+  if (EFI_ERROR (Status)) {\r
+    return ;\r
+  }\r
+\r
+  Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0, sizeof (PciData), &PciData);\r
+  if (EFI_ERROR (Status)) {\r
+    return ;\r
+  }\r
+\r
+  //\r
+  // Check whether this is IDE\r
+  //\r
+  if ((PciData.Hdr.ClassCode[2] != PCI_CLASS_MASS_STORAGE) ||\r
+      (PciData.Hdr.ClassCode[1] != PCI_CLASS_MASS_STORAGE_IDE)) {\r
+    return ;\r
+  }\r
+\r
+  //\r
+  // Clear bar for legacy IDE\r
+  //\r
+  IOBarClear = 0x00;\r
+  if ((PciData.Hdr.ClassCode[0] & IDE_PI_REGISTER_PNE) == 0) {\r
+    PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x10, 1, &IOBarClear);\r
+    PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x14, 1, &IOBarClear);\r
+  }\r
+  if ((PciData.Hdr.ClassCode[0] & IDE_PI_REGISTER_SNE) == 0) {\r
+    PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x18, 1, &IOBarClear);\r
+    PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x1C, 1, &IOBarClear);\r
   }\r
 \r
   return ;\r