ArmPkg/ArmMmuLib ARM: assume page tables are in writeback cacheable memory

Given that these days, our ARM port only supports ARMv7 and later, we
can assume that the page table walker's memory accesses are cache
coherent, and so there is no need to perform cache maintenance. It
does require the page tables themselves to reside in memory mapped as
writeback cacheable so ASSERT() that this is the case.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S
index 149b57e059eeabe46929613b732e74bc4a470a8d..f2a517671f0a0fa07cbe7917102b91e6a253479a 100644 (file)
--- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S
@@ -100,8 +100,6 @@ ASM_FUNC(ArmGetTTBR0BaseAddress)
 //  IN VOID  *MVA                    // R1\r
 //  );\r
 ASM_FUNC(ArmUpdateTranslationTableEntry)\r
 //  IN VOID  *MVA                    // R1\r
 //  );\r
 ASM_FUNC(ArmUpdateTranslationTableEntry)\r

-  mcr     p15,0,R0,c7,c14,1     @ DCCIMVAC Clean data cache by MVA\r
-  dsb\r

   mcr     p15,0,R1,c8,c7,1      @ TLBIMVA TLB Invalidate MVA\r
   mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r
   dsb\r
   mcr     p15,0,R1,c8,c7,1      @ TLBIMVA TLB Invalidate MVA\r
   mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r
   dsb\r

diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
index 9eb6dd8d25c844d084b534c6dd9a2936d3c66c1f..33dd2b173eaab8e7f310a4a9c397d577c4e4269c 100644 (file)
--- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
+++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
@@ -343,17 +343,12 @@ ArmConfigureMmu (
   }\r
 \r
   // Translate the Memory Attributes into Translation Table Register Attributes\r
   }\r
 \r
   // Translate the Memory Attributes into Translation Table Register Attributes\r

-  if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||\r
-      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {\r
-    TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_NON_CACHEABLE : TTBR_NON_CACHEABLE;\r
-  } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||\r
+  if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||\r

       (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {\r
     TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC : TTBR_WRITE_BACK_ALLOC;\r
       (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {\r
     TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC : TTBR_WRITE_BACK_ALLOC;\r

-  } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||\r
-      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {\r
-    TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_THROUGH : TTBR_WRITE_THROUGH;\r

   } else {\r
   } else {\r

-    ASSERT (0); // No support has been found for the attributes of the memory region that the translation table belongs to.\r
+    // Page tables must reside in memory mapped as write-back cacheable\r
+    ASSERT (0);\r

     return RETURN_UNSUPPORTED;\r
   }\r
 \r
     return RETURN_UNSUPPORTED;\r
   }\r
 \r


@@ -461,9 +456,6 @@ ConvertSectionToPages (
     PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor;\r
   }\r
 \r
     PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor;\r
   }\r
 \r

-  // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
-  WriteBackInvalidateDataCacheRange ((VOID *)PageTable, TT_DESCRIPTOR_PAGE_SIZE);\r
-\r

   // Formulate page table entry, Domain=0, NS=0\r
   PageTableDescriptor = (((UINTN)PageTable) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
 \r
   // Formulate page table entry, Domain=0, NS=0\r
   PageTableDescriptor = (((UINTN)PageTable) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
 \r