The bug was caused by
728d74973c9262b6c7b7ef4be213223d55affec3
"MdeModulePkg/PciBus: Count multiple hotplug resource paddings".
The patch firstly updated the Bridge->Alignment to the maximum
alignment of all devices under the bridge, then aligned the
Bridge->Length to Bridge->Alignment.
It caused too much resources were claimed.
The new patch firstly aligns Bridge->Length to Bridge->Alignment,
then updates the Bridge->Alignment to the maximum alignment of all
devices under the bridge.
Because the step to update the Bridge->Alignment is to make sure
the resource allocated to the bus under the Bridge meets all
devices alignment. But the Bridge->Length doesn't have to align
to the maximum alignment.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
- // Adjust the bridge's alignment to the MAX (first) alignment of all children.\r
- //\r
- CurrentLink = Bridge->ChildList.ForwardLink;\r
- if (CurrentLink != &Bridge->ChildList) {\r
- Node = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
- if (Node->Alignment > Bridge->Alignment) {\r
- Bridge->Alignment = Node->Alignment;\r
- }\r
- }\r
-\r
- //\r
- // At last, adjust the aperture with the bridge's alignment\r
+ // Adjust the aperture with the bridge's alignment\r
//\r
Aperture[PciResUsageTypical] = ALIGN_VALUE (Aperture[PciResUsageTypical], Bridge->Alignment + 1);\r
Aperture[PciResUsagePadding] = ALIGN_VALUE (Aperture[PciResUsagePadding], Bridge->Alignment + 1);\r
//\r
Aperture[PciResUsageTypical] = ALIGN_VALUE (Aperture[PciResUsageTypical], Bridge->Alignment + 1);\r
Aperture[PciResUsagePadding] = ALIGN_VALUE (Aperture[PciResUsagePadding], Bridge->Alignment + 1);\r
// Use the larger one between the padding resource and actual occupied resource.\r
//\r
Bridge->Length = MAX (Aperture[PciResUsageTypical], Aperture[PciResUsagePadding]);\r
// Use the larger one between the padding resource and actual occupied resource.\r
//\r
Bridge->Length = MAX (Aperture[PciResUsageTypical], Aperture[PciResUsagePadding]);\r
+\r
+ //\r
+ // Adjust the bridge's alignment to the MAX (first) alignment of all children.\r
+ //\r
+ CurrentLink = Bridge->ChildList.ForwardLink;\r
+ if (CurrentLink != &Bridge->ChildList) {\r
+ Node = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
+ if (Node->Alignment > Bridge->Alignment) {\r
+ Bridge->Alignment = Node->Alignment;\r
+ }\r
+ }\r