-/** @file\r
- PCI Segment Library implementation using PCI Root Bridge I/O Protocol.\r
-\r
- Copyright (c) 2007 - 2008, Intel Corporation All rights\r
- reserved. This program and the accompanying materials are\r
- licensed and made available under the terms and conditions of\r
- the BSD License which accompanies this distribution. The full\r
- text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
- \r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include "PciSegmentLib.h"\r
-\r
-//\r
-// Global varible to record data of PCI Root Bridge I/O Protcol instances\r
-//\r
-PCI_ROOT_BRIDGE_DATA *mPciRootBridgeData = NULL;\r
-UINTN mNumberOfPciRootBridges = 0;\r
-\r
-/**\r
- The constructor function caches data of PCI Root Bridge I/O Protcol instances.\r
- \r
- The constructor function locates PCI Root Bridge I/O protocol instances,\r
- and caches the protocol instances, together with their segment numbers and bus ranges.\r
- It will ASSERT() if that related operation fails and it will always return EFI_SUCCESS. \r
-\r
- @param ImageHandle The firmware allocated handle for the EFI image.\r
- @param SystemTable A pointer to the EFI System Table.\r
- \r
- @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-PciSegmentLibConstructor (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINTN Index;\r
- UINTN HandleCount;\r
- EFI_HANDLE *HandleBuffer;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo; \r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
-\r
- HandleCount = 0;\r
- HandleBuffer = NULL;\r
- PciRootBridgeIo = NULL;\r
- Descriptors = NULL;\r
-\r
- Status = gBS->LocateHandleBuffer (\r
- ByProtocol,\r
- &gEfiPciRootBridgeIoProtocolGuid,\r
- NULL,\r
- &HandleCount,\r
- &HandleBuffer\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- mNumberOfPciRootBridges = HandleCount;\r
-\r
- mPciRootBridgeData = AllocatePool (HandleCount * sizeof (PCI_ROOT_BRIDGE_DATA));\r
- ASSERT (mPciRootBridgeData != NULL);\r
-\r
- //\r
- // Traverse all PCI Root Bridge I/O Protocol instances, and record the protocol\r
- // instances, together with their segment numbers and bus ranges.\r
- //\r
- for (Index = 0; Index < HandleCount; Index++) {\r
- Status = gBS->HandleProtocol (\r
- HandleBuffer[Index],\r
- &gEfiPciRootBridgeIoProtocolGuid,\r
- (VOID **) &PciRootBridgeIo\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- mPciRootBridgeData[Index].PciRootBridgeIo = PciRootBridgeIo;\r
- mPciRootBridgeData[Index].SegmentNumber = PciRootBridgeIo->SegmentNumber;\r
-\r
- Status = PciRootBridgeIo->Configuration (PciRootBridgeIo, (VOID **) &Descriptors);\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- while (Descriptors->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
- if (Descriptors->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {\r
- mPciRootBridgeData[Index].MinBusNumber = Descriptors->AddrRangeMin;\r
- mPciRootBridgeData[Index].MaxBusNumber = Descriptors->AddrRangeMax;\r
- break;\r
- }\r
- Descriptors++;\r
- }\r
- ASSERT (Descriptors->Desc != ACPI_END_TAG_DESCRIPTOR);\r
- }\r
-\r
- FreePool(HandleBuffer);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- The destructor function frees memory allocated by constructor.\r
- \r
- The destructor function frees memory for data of protocol instances allocated by constructor.\r
- It will ASSERT() if that related operation fails and it will always return EFI_SUCCESS. \r
-\r
- @param ImageHandle The firmware allocated handle for the EFI image.\r
- @param SystemTable A pointer to the EFI System Table.\r
- \r
- @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-PciSegmentLibDestructor (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-{\r
- FreePool (mPciRootBridgeData);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- According to address, search for the corresponding PCI Root Bridge I/O Protocol instance.\r
-\r
- This internal function extracts segment number and bus number data from address, and\r
- retrieves the corresponding PCI Root Bridge I/O Protocol instance.\r
-\r
- @param Address Address that encodes the Segment, PCI Bus, Device, Function and\r
- Register.\r
-\r
- @return The address for PCI Root Bridge I/O Protocol.\r
-\r
-**/\r
-EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *\r
-PciSegmentLibSearchForRootBridge (\r
- IN UINT64 Address\r
- )\r
-{\r
- UINTN Index;\r
- UINT64 SegmentNumber;\r
- UINT64 BusNumber;\r
-\r
- for (Index = 0; Index < mNumberOfPciRootBridges; Index++) {\r
- //\r
- // Matches segment number of address with the segment number of protocol instance.\r
- //\r
- SegmentNumber = BitFieldRead64 (Address, 32, 63);\r
- if (SegmentNumber == mPciRootBridgeData[Index].SegmentNumber) {\r
- //\r
- // Matches the bus number of address with bus number range of protocol instance.\r
- //\r
- BusNumber = BitFieldRead64 (Address, 20, 27);\r
- if (BusNumber >= mPciRootBridgeData[Index].MinBusNumber && BusNumber <= mPciRootBridgeData[Index].MaxBusNumber) {\r
- return mPciRootBridgeData[Index].PciRootBridgeIo;\r
- }\r
- } \r
- }\r
- return NULL;\r
-}\r
-\r
-/**\r
- Internal worker function to read a PCI configuration register.\r
-\r
- This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() service.\r
- It reads and returns the PCI configuration register specified by Address,\r
- the width of data is specified by Width.\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param Width Width of data to read\r
-\r
- @return The value read from the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-DxePciSegmentLibPciRootBridgeIoReadWorker (\r
- IN UINT64 Address,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width\r
- )\r
-{\r
- UINT32 Data;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo; \r
-\r
- PciRootBridgeIo = PciSegmentLibSearchForRootBridge (Address);\r
- ASSERT (PciRootBridgeIo != NULL);\r
-\r
- PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo,\r
- Width,\r
- PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),\r
- 1,\r
- &Data\r
- );\r
-\r
- return Data;\r
-}\r
-\r
-/**\r
- Internal worker function to writes a PCI configuration register.\r
-\r
- This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write() service.\r
- It writes the PCI configuration register specified by Address with the\r
- value specified by Data. The width of data is specifed by Width.\r
- Data is returned.\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param Width Width of data to write\r
- @param Data The value to write.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-DxePciSegmentLibPciRootBridgeIoWriteWorker (\r
- IN UINT64 Address,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT32 Data\r
- )\r
-{\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo; \r
-\r
- PciRootBridgeIo = PciSegmentLibSearchForRootBridge (Address);\r
- ASSERT (PciRootBridgeIo != NULL);\r
-\r
- PciRootBridgeIo->Pci.Write (\r
- PciRootBridgeIo,\r
- Width,\r
- PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),\r
- 1,\r
- &Data\r
- );\r
-\r
- return Data;\r
-}\r
-\r
-/**\r
- Reads an 8-bit PCI configuration register.\r
-\r
- Reads and returns the 8-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
-\r
- @return The value read from the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentRead8 (\r
- IN UINT64 Address\r
- )\r
-{\r
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
-\r
- return (UINT8) DxePciSegmentLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint8);\r
-}\r
-\r
-/**\r
- Writes an 8-bit PCI configuration register.\r
-\r
- Writes the 8-bit PCI configuration register specified by Address with the\r
- value specified by Value. Value is returned. This function must guarantee\r
- that all PCI read and write operations are serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param Data The value to write.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentWrite8 (\r
- IN UINT64 Address,\r
- IN UINT8 Data\r
- )\r
-{\r
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
-\r
- return (UINT8) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Data);\r
-}\r
-\r
-/**\r
- Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r
- an 8-bit value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
- OrData, and writes the result to the 8-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
- value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 8-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentAnd8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData\r
- )\r
-{\r
- return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
- value, followed a bitwise inclusive OR with another 8-bit value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise inclusive OR between the result of the AND operation and\r
- the value specified by OrData, and writes the result to the 8-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));\r
-}\r
-\r
-/**\r
- Reads a bit field of a PCI configuration register.\r
-\r
- Reads the bit field in an 8-bit PCI configuration register. The bit field is\r
- specified by the StartBit and the EndBit. The value of the bit field is\r
- returned.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
-\r
- @return The value of the bit field read from the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentBitFieldRead8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);\r
-}\r
-\r
-/**\r
- Writes a bit field to a PCI configuration register.\r
-\r
- Writes Value to the bit field of the PCI configuration register. The bit\r
- field is specified by the StartBit and the EndBit. All other bits in the\r
- destination PCI configuration register are preserved. The new value of the\r
- 8-bit register is returned.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentBitFieldWrite8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
- )\r
-{\r
- return PciSegmentWrite8 (\r
- Address,\r
- BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r
- writes the result back to the bit field in the 8-bit port.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
- OrData, and writes the result to the 8-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized. Extra left bits in OrData are stripped.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentBitFieldOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return PciSegmentWrite8 (\r
- Address,\r
- BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r
- AND, and writes the result back to the bit field in the 8-bit register.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 8-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized. Extra left bits in AndData are stripped.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentBitFieldAnd8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
- )\r
-{\r
- return PciSegmentWrite8 (\r
- Address,\r
- BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
- bitwise inclusive OR, and writes the result back to the bit field in the\r
- 8-bit port.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise inclusive OR between the read result and\r
- the value specified by AndData, and writes the result to the 8-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized. Extra left bits in both AndData and\r
- OrData are stripped.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentBitFieldAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return PciSegmentWrite8 (\r
- Address,\r
- BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a 16-bit PCI configuration register.\r
-\r
- Reads and returns the 16-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
-\r
- @return The value read from the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentRead16 (\r
- IN UINT64 Address\r
- )\r
-{\r
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r
-\r
- return (UINT16) DxePciSegmentLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint16);\r
-}\r
-\r
-/**\r
- Writes a 16-bit PCI configuration register.\r
-\r
- Writes the 16-bit PCI configuration register specified by Address with the\r
- value specified by Value. Value is returned. This function must guarantee\r
- that all PCI read and write operations are serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param Data The value to write.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentWrite16 (\r
- IN UINT64 Address,\r
- IN UINT16 Data\r
- )\r
-{\r
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r
-\r
- return (UINT16) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Data);\r
-}\r
-\r
-/**\r
- Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r
- a 16-bit value.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
- OrData, and writes the result to the 16-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
- value.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 16-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentAnd16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData\r
- )\r
-{\r
- return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
- value, followed a bitwise inclusive OR with another 16-bit value.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise inclusive OR between the result of the AND operation and\r
- the value specified by OrData, and writes the result to the 16-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));\r
-}\r
-\r
-/**\r
- Reads a bit field of a PCI configuration register.\r
-\r
- Reads the bit field in a 16-bit PCI configuration register. The bit field is\r
- specified by the StartBit and the EndBit. The value of the bit field is\r
- returned.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
-\r
- @return The value of the bit field read from the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentBitFieldRead16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);\r
-}\r
-\r
-/**\r
- Writes a bit field to a PCI configuration register.\r
-\r
- Writes Value to the bit field of the PCI configuration register. The bit\r
- field is specified by the StartBit and the EndBit. All other bits in the\r
- destination PCI configuration register are preserved. The new value of the\r
- 16-bit register is returned.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentBitFieldWrite16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
- )\r
-{\r
- return PciSegmentWrite16 (\r
- Address,\r
- BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r
- writes the result back to the bit field in the 16-bit port.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
- OrData, and writes the result to the 16-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized. Extra left bits in OrData are stripped.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentBitFieldOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return PciSegmentWrite16 (\r
- Address,\r
- BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r
- AND, and writes the result back to the bit field in the 16-bit register.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 16-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized. Extra left bits in AndData are stripped.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentBitFieldAnd16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
- )\r
-{\r
- return PciSegmentWrite16 (\r
- Address,\r
- BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r
- bitwise inclusive OR, and writes the result back to the bit field in the\r
- 16-bit port.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise inclusive OR between the read result and\r
- the value specified by AndData, and writes the result to the 16-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized. Extra left bits in both AndData and\r
- OrData are stripped.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentBitFieldAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return PciSegmentWrite16 (\r
- Address,\r
- BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a 32-bit PCI configuration register.\r
-\r
- Reads and returns the 32-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
-\r
- @return The value read from the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentRead32 (\r
- IN UINT64 Address\r
- )\r
-{\r
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r
-\r
- return DxePciSegmentLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint32);\r
-}\r
-\r
-/**\r
- Writes a 32-bit PCI configuration register.\r
-\r
- Writes the 32-bit PCI configuration register specified by Address with the\r
- value specified by Value. Value is returned. This function must guarantee\r
- that all PCI read and write operations are serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param Data The value to write.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentWrite32 (\r
- IN UINT64 Address,\r
- IN UINT32 Data\r
- )\r
-{\r
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r
-\r
- return DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Data);\r
-}\r
-\r
-/**\r
- Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r
- a 32-bit value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
- OrData, and writes the result to the 32-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
- value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 32-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentAnd32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData\r
- )\r
-{\r
- return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
- value, followed a bitwise inclusive OR with another 32-bit value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise inclusive OR between the result of the AND operation and\r
- the value specified by OrData, and writes the result to the 32-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);\r
-}\r
-\r
-/**\r
- Reads a bit field of a PCI configuration register.\r
-\r
- Reads the bit field in a 32-bit PCI configuration register. The bit field is\r
- specified by the StartBit and the EndBit. The value of the bit field is\r
- returned.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
-\r
- @return The value of the bit field read from the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentBitFieldRead32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);\r
-}\r
-\r
-/**\r
- Writes a bit field to a PCI configuration register.\r
-\r
- Writes Value to the bit field of the PCI configuration register. The bit\r
- field is specified by the StartBit and the EndBit. All other bits in the\r
- destination PCI configuration register are preserved. The new value of the\r
- 32-bit register is returned.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentBitFieldWrite32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
- )\r
-{\r
- return PciSegmentWrite32 (\r
- Address,\r
- BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r
- writes the result back to the bit field in the 32-bit port.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
- OrData, and writes the result to the 32-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized. Extra left bits in OrData are stripped.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentBitFieldOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return PciSegmentWrite32 (\r
- Address,\r
- BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r
- AND, and writes the result back to the bit field in the 32-bit register.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 32-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized. Extra left bits in AndData are stripped.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentBitFieldAnd32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
- )\r
-{\r
- return PciSegmentWrite32 (\r
- Address,\r
- BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r
- bitwise inclusive OR, and writes the result back to the bit field in the\r
- 32-bit port.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise inclusive OR between the read result and\r
- the value specified by AndData, and writes the result to the 32-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized. Extra left bits in both AndData and\r
- OrData are stripped.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentBitFieldAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return PciSegmentWrite32 (\r
- Address,\r
- BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a range of PCI configuration registers into a caller supplied buffer.\r
-\r
- Reads the range of PCI configuration registers specified by StartAddress and\r
- Size into the buffer specified by Buffer. This function only allows the PCI\r
- configuration registers from a single PCI function to be read. Size is\r
- returned. When possible 32-bit PCI configuration read cycles are used to read\r
- from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
- and 16-bit PCI configuration read cycles may be used at the beginning and the\r
- end of the range.\r
-\r
- If StartAddress > 0x0FFFFFFF, then ASSERT().\r
- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
- If Size > 0 and Buffer is NULL, then ASSERT().\r
-\r
- @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r
- Function and Register.\r
- @param Size Size in bytes of the transfer.\r
- @param Buffer Pointer to a buffer receiving the data read.\r
-\r
- @return Size\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-PciSegmentReadBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- UINTN ReturnValue;\r
-\r
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
-\r
- if (Size == 0) {\r
- return Size;\r
- }\r
-\r
- ASSERT (Buffer != NULL);\r
-\r
- //\r
- // Save Size for return\r
- //\r
- ReturnValue = Size;\r
-\r
- if ((StartAddress & BIT0) != 0) {\r
- //\r
- // Read a byte if StartAddress is byte aligned\r
- //\r
- *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
- //\r
- // Read a word if StartAddress is word aligned\r
- //\r
- *(volatile UINT16 *)Buffer = PciSegmentRead16 (StartAddress);\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- while (Size >= sizeof (UINT32)) {\r
- //\r
- // Read as many double words as possible\r
- //\r
- *(volatile UINT32 *)Buffer = PciSegmentRead32 (StartAddress);\r
- StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16)) {\r
- //\r
- // Read the last remaining word if exist\r
- //\r
- *(volatile UINT16 *)Buffer = PciSegmentRead16 (StartAddress);\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT8)) {\r
- //\r
- // Read the last remaining byte if exist\r
- //\r
- *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);\r
- }\r
-\r
- return ReturnValue;\r
-}\r
-\r
-/**\r
- Copies the data in a caller supplied buffer to a specified range of PCI\r
- configuration space.\r
-\r
- Writes the range of PCI configuration registers specified by StartAddress and\r
- Size from the buffer specified by Buffer. This function only allows the PCI\r
- configuration registers from a single PCI function to be written. Size is\r
- returned. When possible 32-bit PCI configuration write cycles are used to\r
- write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
- 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
- and the end of the range.\r
-\r
- If StartAddress > 0x0FFFFFFF, then ASSERT().\r
- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
- If Size > 0 and Buffer is NULL, then ASSERT().\r
-\r
- @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r
- Function and Register.\r
- @param Size Size in bytes of the transfer.\r
- @param Buffer Pointer to a buffer containing the data to write.\r
-\r
- @return Size\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-PciSegmentWriteBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
- )\r
-{\r
- UINTN ReturnValue;\r
-\r
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
-\r
- if (Size == 0) {\r
- return 0;\r
- }\r
-\r
- ASSERT (Buffer != NULL);\r
-\r
- //\r
- // Save Size for return\r
- //\r
- ReturnValue = Size;\r
-\r
- if ((StartAddress & BIT0) != 0) {\r
- //\r
- // Write a byte if StartAddress is byte aligned\r
- //\r
- PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
- //\r
- // Write a word if StartAddress is word aligned\r
- //\r
- PciSegmentWrite16 (StartAddress, *(UINT16*)Buffer);\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- while (Size >= sizeof (UINT32)) {\r
- //\r
- // Write as many double words as possible\r
- //\r
- PciSegmentWrite32 (StartAddress, *(UINT32*)Buffer);\r
- StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16)) {\r
- //\r
- // Write the last remaining word if exist\r
- //\r
- PciSegmentWrite16 (StartAddress, *(UINT16*)Buffer);\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT8)) {\r
- //\r
- // Write the last remaining byte if exist\r
- //\r
- PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);\r
- }\r
-\r
- return ReturnValue;\r
-}\r