BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1771
Some buses doesn't allow 8 bit MMIO read/write, this adds support for
32 bits read/write. This patch adds the UNI information on the new Pcd
introduced - PcdSerialRegisterAccessWidth
Signed-off-by: "Tien Hock, Loh" <tien.hock.loh@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: "Zhu, YongHong" <yonghong.zhu@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
"TRUE - 16550 serial port registers are in MMIO space.<BR>\n"\r
"FALSE - 16550 serial port registers are in I/O space.<BR>"\r
\r
+#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdSerialRegisterAccessWidth_PROMPT #language en-US "Serial port registers access width"\r
+\r
+#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdSerialRegisterAccessWidth_HELP #language en-US "Sets the 16550 serial port registers access width in MMIO space. Default is 8 bits access.<BR><BR>\n"\r
+ "8 - 16550 serial port MMIO register access are in 8 bits mode.<BR>\n"\r
+ "32 - 16550 serial port MMIO registers acess are in 32 bits mode.<BR>"\r
+\r
#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdSerialUseHardwareFlowControl_PROMPT #language en-US "Enable serial port hardware flow control"\r
\r
#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdSerialUseHardwareFlowControl_HELP #language en-US "Indicates if the 16550 serial port hardware flow control will be enabled. Default is FALSE.<BR><BR>\n"\r