PcAtChipsetPkg/HpetTimerDxe: Fix race condition in SetTimerPeriod()
authorMichael Kinney <michael.d.kinney@intel.com>
Wed, 26 Oct 2016 22:26:03 +0000 (15:26 -0700)
committerMichael Kinney <michael.d.kinney@intel.com>
Fri, 28 Oct 2016 04:46:42 +0000 (21:46 -0700)
https://bugzilla.tianocore.org/show_bug.cgi?id=182

The function TimerDriverSetTimerPeriod() disables the HPET timer
while the HPET timer HW is reprogrammed with a new timer period.
However, the MMIO write to disable the HPET timer HW can be
delayed and an HPET timer interrupt may be processed in the middle
of reprogramming the HPET timer HW and this may produced unexpected
results.

The fix is to raise TPL to TPL_HIGH_LEVEL in
TimerDriverSetTimerPeriod() during the time the HPET timer HW is
reprogrammed.  This guarantees that no timer interrupts are
processed during reprogramming.

The TimerDriverGenerateSoftInterrupt() function in this same
driver also raises TPL to TPL_HIGH_LEVEL, so this fix matches
the logic that is already used in another function for the same
reason.

Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c

index 0ed8743..c62c3a9 100644 (file)
@@ -492,11 +492,17 @@ TimerDriverSetTimerPeriod (
   IN UINT64                   TimerPeriod\r
   )\r
 {\r
+  EFI_TPL                        Tpl;\r
   UINT64                         MainCounter;\r
   UINT64                         Delta;\r
   UINT64                         CurrentComparator;\r
   HPET_TIMER_MSI_ROUTE_REGISTER  HpetTimerMsiRoute;\r
-  \r
+\r
+  //\r
+  // Disable interrupts\r
+  //\r
+  Tpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);\r
+\r
   //\r
   // Disable HPET timer when adjusting the timer period\r
   //\r
@@ -616,7 +622,12 @@ TimerDriverSetTimerPeriod (
   // is disabled.\r
   //\r
   HpetEnable (TRUE);\r
-  \r
+\r
+  //\r
+  // Restore interrupts\r
+  //\r
+  gBS->RestoreTPL (Tpl);\r
+\r
   return EFI_SUCCESS;\r
 }\r
 \r