IntelSiliconPkg/VTdInfoSample: Add RMRR table.

Let system report RMRR table for the platform support
PEI graphic.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>

diff --git a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
index 324f3ef6ba90d00278bd1212123364f94d8b1644..08a4db3e631da40b89a6049673fb77fc22eb84af 100644 (file)
--- a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
+++ b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
@@ -18,21 +18,111 @@
 \r
 #include <Library/PeiServicesLib.h>\r
 #include <Library/DebugLib.h>\r
+#include <Library/PciLib.h>\r
+#include <Library/IoLib.h>\r
+\r
+#define R_SA_MCHBAR               (0x48)\r
+#define R_SA_GGC                  (0x50)\r
+#define N_SKL_SA_GGC_GGMS_OFFSET  (0x6)\r
+#define B_SKL_SA_GGC_GGMS_MASK    (0xc0)\r
+#define N_SKL_SA_GGC_GMS_OFFSET   (0x8)\r
+#define B_SKL_SA_GGC_GMS_MASK     (0xff00)\r
+#define V_SKL_SA_GGC_GGMS_8MB     3\r
+#define R_SA_TOLUD                (0xbc)\r
+\r
+#define R_SA_MCHBAR_VTD1_OFFSET  0x5400  ///< HW UNIT for IGD\r
+#define R_SA_MCHBAR_VTD2_OFFSET  0x5410  ///< HW UNIT for all other - PEG, USB, SATA etc\r
 \r
 typedef struct {\r
-  UINT64                                  Revision;\r
-  UINT8                                   HostAddressWidth;\r
-  UINT8                                   Reserved[3];\r
-  UINT32                                  VTdEngineCount;\r
-  UINT64                                  VTdEngineAddress[2];\r
+  EFI_ACPI_DMAR_HEADER                         DmarHeader;\r
+  //\r
+  // VTd engine 1 - integrated graphic\r
+  //\r
+  EFI_ACPI_DMAR_DRHD_HEADER                    Drhd1;\r
+  EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER  Drhd11;\r
+  EFI_ACPI_DMAR_PCI_PATH                       Drhd111;\r
+  //\r
+  // VTd engine 2 - all rest\r
+  //\r
+  EFI_ACPI_DMAR_DRHD_HEADER                    Drhd2;\r
+  //\r
+  // RMRR 1 - integrated graphic\r
+  //\r
+  EFI_ACPI_DMAR_RMRR_HEADER                    Rmrr1;\r
+  EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER  Rmrr11;\r
+  EFI_ACPI_DMAR_PCI_PATH                       Rmrr111;\r
 } MY_VTD_INFO_PPI;\r
 \r
 MY_VTD_INFO_PPI  mPlatformVTdSample = {\r
-  EDKII_VTD_INFO_PPI_REVISION,\r
-  0x26,\r
-  {0},\r
-  2,\r
-  {0xFED90000, 0xFED91000},\r
+  { // DmarHeader\r
+    { // Header\r
+      EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE,\r
+      sizeof(MY_VTD_INFO_PPI),\r
+      EFI_ACPI_DMAR_REVISION,\r
+    },\r
+    0x26, // HostAddressWidth\r
+  },\r
+\r
+  { // Drhd1\r
+    { // Header\r
+      EFI_ACPI_DMAR_TYPE_DRHD,\r
+      sizeof(EFI_ACPI_DMAR_DRHD_HEADER) +\r
+        sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +\r
+        sizeof(EFI_ACPI_DMAR_PCI_PATH)\r
+    },\r
+    0, // Flags\r
+    0, // Reserved\r
+    0, // SegmentNumber\r
+    0xFED90000 // RegisterBaseAddress -- TO BE PATCHED\r
+  },\r
+  { // Drhd11\r
+    EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT,\r
+    sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +\r
+      sizeof(EFI_ACPI_DMAR_PCI_PATH),\r
+    0, // Reserved2\r
+    0, // EnumerationId\r
+    0  // StartBusNumber\r
+  },\r
+  { // Drhd111\r
+    2,  // Device\r
+    0   // Function\r
+  },\r
+\r
+  { // Drhd2\r
+    { // Header\r
+      EFI_ACPI_DMAR_TYPE_DRHD,\r
+      sizeof(EFI_ACPI_DMAR_DRHD_HEADER)\r
+    },\r
+    EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL, // Flags\r
+    0, // Reserved\r
+    0, // SegmentNumber\r
+    0xFED91000 // RegisterBaseAddress -- TO BE PATCHED\r
+  },\r
+\r
+  { // Rmrr1\r
+    { // Header\r
+      EFI_ACPI_DMAR_TYPE_RMRR,\r
+      sizeof(EFI_ACPI_DMAR_RMRR_HEADER) +\r
+        sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +\r
+        sizeof(EFI_ACPI_DMAR_PCI_PATH)\r
+    },\r
+    {0}, // Reserved\r
+    0, // SegmentNumber\r
+    0x0, // ReservedMemoryRegionBaseAddress -- TO BE PATCHED\r
+    0x0 // ReservedMemoryRegionLimitAddress -- TO BE PATCHED\r
+  },\r
+  { // Rmrr11\r
+    EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT,\r
+    sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +\r
+      sizeof(EFI_ACPI_DMAR_PCI_PATH),\r
+    0, // Reserved2\r
+    0, // EnumerationId\r
+    0  // StartBusNumber\r
+  },\r
+  { // Rmrr111\r
+    2,  // Device\r
+    0   // Function\r
+  },\r
 };\r
 \r
 EFI_PEI_PPI_DESCRIPTOR mPlatformVTdInfoSampleDesc = {\r
@@ -41,6 +131,50 @@ EFI_PEI_PPI_DESCRIPTOR mPlatformVTdInfoSampleDesc = {
   &mPlatformVTdSample\r
 };\r
 \r
+/**\r
+  Patch Graphic UMA address in RMRR and base address.\r
+**/\r
+VOID\r
+PatchDmar (\r
+  VOID\r
+  )\r
+{\r
+  UINT32              MchBar;\r
+  UINT16              IgdMode;\r
+  UINT16              GttMode;\r
+  UINT32              IgdMemSize;\r
+  UINT32              GttMemSize;\r
+\r
+  ///\r
+  /// Calculate IGD memsize\r
+  ///\r
+  IgdMode = ((PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & B_SKL_SA_GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF;\r
+  if (IgdMode < 0xF0) {\r
+    IgdMemSize = IgdMode * 32 * (1024) * (1024);\r
+  } else {\r
+    IgdMemSize = 4 * (IgdMode - 0xF0 + 1) * (1024) * (1024);\r
+  }\r
+\r
+  ///\r
+  /// Calculate GTT mem size\r
+  ///\r
+  GttMemSize = 0;\r
+  GttMode = PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC) & B_SKL_SA_GGC_GGMS_MASK) >> N_SKL_SA_GGC_GGMS_OFFSET;\r
+  if (GttMode <= V_SKL_SA_GGC_GGMS_8MB) {\r
+    GttMemSize = (1 << GttMode) * (1024) * (1024);\r
+  }\r
+\r
+  mPlatformVTdSample.Rmrr1.ReservedMemoryRegionBaseAddress  = (PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_TOLUD)) & ~(0x01)) - IgdMemSize - GttMemSize;\r
+  mPlatformVTdSample.Rmrr1.ReservedMemoryRegionLimitAddress = mPlatformVTdSample.Rmrr1.ReservedMemoryRegionBaseAddress + IgdMemSize + GttMemSize - 1;\r
+\r
+  ///\r
+  /// Update DRHD structures of DmarTable\r
+  ///\r
+  MchBar = PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0;\r
+  mPlatformVTdSample.Drhd1.RegisterBaseAddress = (MmioRead32 (MchBar + R_SA_MCHBAR_VTD1_OFFSET) &~1);\r
+  mPlatformVTdSample.Drhd2.RegisterBaseAddress = (MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET) &~1);\r
+}\r
+\r
 /**\r
   Platform VTd Info sample driver.\r
 \r
@@ -58,6 +192,8 @@ PlatformVTdInfoSampleInitialize (
 {\r
   EFI_STATUS  Status;\r
 \r
+  PatchDmar ();\r
+\r
   Status = PeiServicesInstallPpi (&mPlatformVTdInfoSampleDesc);\r
   ASSERT_EFI_ERROR (Status);\r
 \r

diff --git a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
index fe12821d3d3d337e379ee42c735c780767b00a7e..96adb70edca071828558825a40e8e1fe79e709ea 100644 (file)
--- a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
+++ b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
@@ -39,6 +39,9 @@
 [LibraryClasses]\r
   PeimEntryPoint\r
   PeiServicesLib\r
+  DebugLib\r
+  PciLib\r
+  IoLib\r
 \r
 [Ppis]\r
   gEdkiiVTdInfoPpiGuid         ## PRODUCES\r