ArmPkg/ArmLib: Fixed TBLs invalidation in EL1

'tlb alle1' was used to invalidate the TLBs in EL1. Expect this instruction can only
be invoked from EL2.
The correct instruction to invalidate TLBs in EL1 is 'tlbi vmalle1' - it invalidates
the TLBs of the current VMID.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14509 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
index c45e33d6b92a2a8742b7517c73ab004e48503d7e..ad9fdda5253d9cd49012436033a3b8dfd908490d 100644 (file)
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
@@ -123,7 +123,7 @@ ASM_PFX(ArmEnableMmu):
 3: mrs     x0, sctlr_el3       // Read System control register EL3\r
 4: orr     x0, x0, #CTRL_M_BIT // Set MMU enable bit\r
    EL1_OR_EL2_OR_EL3(x1)\r
-1: tlbi    alle1\r
+1: tlbi    vmalle1\r
    isb\r
    msr     sctlr_el1, x0       // Write back\r
    b       4f\r
@@ -149,7 +149,7 @@ ASM_PFX(ArmDisableMmu):
 4: bic     x0, x0, #CTRL_M_BIT  // Clear MMU enable bit\r
    EL1_OR_EL2_OR_EL3(x1)\r
 1: msr     sctlr_el1, x0        // Write back\r
-   tlbi    alle1\r
+   tlbi    vmalle1\r
    b       4f\r
 2: msr     sctlr_el2, x0        // Write back\r
    tlbi    alle2\r
@@ -441,7 +441,7 @@ ASM_PFX(ArmCallWFI):
 \r
 ASM_PFX(ArmInvalidateInstructionAndDataTlb):\r
    EL1_OR_EL2_OR_EL3(x0)\r
-1: tlbi  alle1\r
+1: tlbi  vmalle1\r
    b     4f\r
 2: tlbi  alle2\r
    b     4f\r

diff --git a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
index d7b2881b9807c69eb939a7ade9130afe9aacad03..2db812616a35c4f807af7af6b3015088cdcb2c0c 100644 (file)
--- a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
@@ -167,7 +167,7 @@ ASM_PFX(ArmUpdateTranslationTableEntry):
 \r
 ASM_PFX(ArmInvalidateTlb):\r
    EL1_OR_EL2_OR_EL3(x0)\r
-1: tlbi  alle1\r
+1: tlbi  vmalle1\r
    b     4f\r
 2: tlbi  alle2\r
    b     4f\r