1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver.
2) Remove ExtractProcessorLocation() from MpInitLib library.
3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
Signed-off-by: Michael Kinney <Michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael Kinney <Michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
IN BOOLEAN LevelTriggered,\r
IN BOOLEAN AssertionLevel\r
);\r
+\r
+/**\r
+ Get Package ID/Core ID/Thread ID of a processor.\r
+\r
+ The algorithm assumes the target system has symmetry across physical\r
+ package boundaries with respect to the number of logical processors\r
+ per package, number of cores per package.\r
+\r
+ @param[in] InitialApicId Initial APIC ID of the target logical processor.\r
+ @param[out] Package Returns the processor package ID.\r
+ @param[out] Core Returns the processor core ID.\r
+ @param[out] Thread Returns the processor thread ID.\r
+**/\r
+VOID\r
+GetProcessorLocation(\r
+ IN UINT32 InitialApicId,\r
+ OUT UINT32 *Package OPTIONAL,\r
+ OUT UINT32 *Core OPTIONAL,\r
+ OUT UINT32 *Thread OPTIONAL\r
+ );\r
\r
#endif\r
\r
}\r
return MsiData.Uint64;\r
}\r
+\r
+/**\r
+ Get Package ID/Core ID/Thread ID of a processor.\r
+\r
+ The algorithm assumes the target system has symmetry across physical\r
+ package boundaries with respect to the number of logical processors\r
+ per package, number of cores per package.\r
+\r
+ @param[in] InitialApicId Initial APIC ID of the target logical processor.\r
+ @param[out] Package Returns the processor package ID.\r
+ @param[out] Core Returns the processor core ID.\r
+ @param[out] Thread Returns the processor thread ID.\r
+**/\r
+VOID\r
+GetProcessorLocation(\r
+ IN UINT32 InitialApicId,\r
+ OUT UINT32 *Package OPTIONAL,\r
+ OUT UINT32 *Core OPTIONAL,\r
+ OUT UINT32 *Thread OPTIONAL\r
+ )\r
+{\r
+ BOOLEAN TopologyLeafSupported;\r
+ UINTN ThreadBits;\r
+ UINTN CoreBits;\r
+ CPUID_VERSION_INFO_EBX VersionInfoEbx;\r
+ CPUID_VERSION_INFO_EDX VersionInfoEdx;\r
+ CPUID_CACHE_PARAMS_EAX CacheParamsEax;\r
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;\r
+ CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;\r
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;\r
+ UINT32 MaxCpuIdIndex;\r
+ UINT32 SubIndex;\r
+ UINTN LevelType;\r
+ UINT32 MaxLogicProcessorsPerPackage;\r
+ UINT32 MaxCoresPerPackage;\r
+\r
+ //\r
+ // Check if the processor is capable of supporting more than one logical processor.\r
+ //\r
+ AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r
+ if (VersionInfoEdx.Bits.HTT == 0) {\r
+ if (Thread != NULL) {\r
+ *Thread = 0;\r
+ }\r
+ if (Core != NULL) {\r
+ *Core = 0;\r
+ }\r
+ if (Package != NULL) {\r
+ *Package = 0;\r
+ }\r
+ return;\r
+ }\r
+\r
+ ThreadBits = 0;\r
+ CoreBits = 0;\r
+\r
+ //\r
+ // Assume three-level mapping of APIC ID: Package:Core:SMT.\r
+ //\r
+ TopologyLeafSupported = FALSE;\r
+\r
+ //\r
+ // Get the max index of basic CPUID\r
+ //\r
+ AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r
+\r
+ //\r
+ // If the extended topology enumeration leaf is available, it\r
+ // is the preferred mechanism for enumerating topology.\r
+ //\r
+ if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r
+ AsmCpuidEx(\r
+ CPUID_EXTENDED_TOPOLOGY,\r
+ 0,\r
+ &ExtendedTopologyEax.Uint32,\r
+ &ExtendedTopologyEbx.Uint32,\r
+ &ExtendedTopologyEcx.Uint32,\r
+ NULL\r
+ );\r
+ //\r
+ // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for\r
+ // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not\r
+ // supported on that processor.\r
+ //\r
+ if (ExtendedTopologyEbx.Uint32 != 0) {\r
+ TopologyLeafSupported = TRUE;\r
+\r
+ //\r
+ // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract\r
+ // the SMT sub-field of x2APIC ID.\r
+ //\r
+ LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
+ ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r
+ ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;\r
+\r
+ //\r
+ // Software must not assume any "level type" encoding\r
+ // value to be related to any sub-leaf index, except sub-leaf 0.\r
+ //\r
+ SubIndex = 1;\r
+ do {\r
+ AsmCpuidEx(\r
+ CPUID_EXTENDED_TOPOLOGY,\r
+ SubIndex,\r
+ &ExtendedTopologyEax.Uint32,\r
+ NULL,\r
+ &ExtendedTopologyEcx.Uint32,\r
+ NULL\r
+ );\r
+ LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
+ if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {\r
+ CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;\r
+ break;\r
+ }\r
+ SubIndex++;\r
+ } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);\r
+ }\r
+ }\r
+\r
+ if (!TopologyLeafSupported) {\r
+ AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);\r
+ MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;\r
+ if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {\r
+ AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);\r
+ MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;\r
+ }\r
+ else {\r
+ //\r
+ // Must be a single-core processor.\r
+ //\r
+ MaxCoresPerPackage = 1;\r
+ }\r
+\r
+ ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r
+ CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }\r
+\r
+ if (Thread != NULL) {\r
+ *Thread = InitialApicId & ((1 << ThreadBits) - 1);\r
+ }\r
+ if (Core != NULL) {\r
+ *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);\r
+ }\r
+ if (Package != NULL) {\r
+ *Package = (InitialApicId >> (ThreadBits + CoreBits));\r
+ }\r
+}\r
}\r
return MsiData.Uint64;\r
}\r
+\r
+/**\r
+ Get Package ID/Core ID/Thread ID of a processor.\r
+\r
+ The algorithm assumes the target system has symmetry across physical\r
+ package boundaries with respect to the number of logical processors\r
+ per package, number of cores per package.\r
+\r
+ @param[in] InitialApicId Initial APIC ID of the target logical processor.\r
+ @param[out] Package Returns the processor package ID.\r
+ @param[out] Core Returns the processor core ID.\r
+ @param[out] Thread Returns the processor thread ID.\r
+**/\r
+VOID\r
+GetProcessorLocation(\r
+ IN UINT32 InitialApicId,\r
+ OUT UINT32 *Package OPTIONAL,\r
+ OUT UINT32 *Core OPTIONAL,\r
+ OUT UINT32 *Thread OPTIONAL\r
+ )\r
+{\r
+ BOOLEAN TopologyLeafSupported;\r
+ UINTN ThreadBits;\r
+ UINTN CoreBits;\r
+ CPUID_VERSION_INFO_EBX VersionInfoEbx;\r
+ CPUID_VERSION_INFO_EDX VersionInfoEdx;\r
+ CPUID_CACHE_PARAMS_EAX CacheParamsEax;\r
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;\r
+ CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;\r
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;\r
+ UINT32 MaxCpuIdIndex;\r
+ UINT32 SubIndex;\r
+ UINTN LevelType;\r
+ UINT32 MaxLogicProcessorsPerPackage;\r
+ UINT32 MaxCoresPerPackage;\r
+\r
+ //\r
+ // Check if the processor is capable of supporting more than one logical processor.\r
+ //\r
+ AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r
+ if (VersionInfoEdx.Bits.HTT == 0) {\r
+ if (Thread != NULL) {\r
+ *Thread = 0;\r
+ }\r
+ if (Core != NULL) {\r
+ *Core = 0;\r
+ }\r
+ if (Package != NULL) {\r
+ *Package = 0;\r
+ }\r
+ return;\r
+ }\r
+\r
+ ThreadBits = 0;\r
+ CoreBits = 0;\r
+\r
+ //\r
+ // Assume three-level mapping of APIC ID: Package:Core:SMT.\r
+ //\r
+ TopologyLeafSupported = FALSE;\r
+\r
+ //\r
+ // Get the max index of basic CPUID\r
+ //\r
+ AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r
+\r
+ //\r
+ // If the extended topology enumeration leaf is available, it\r
+ // is the preferred mechanism for enumerating topology.\r
+ //\r
+ if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r
+ AsmCpuidEx(\r
+ CPUID_EXTENDED_TOPOLOGY,\r
+ 0,\r
+ &ExtendedTopologyEax.Uint32,\r
+ &ExtendedTopologyEbx.Uint32,\r
+ &ExtendedTopologyEcx.Uint32,\r
+ NULL\r
+ );\r
+ //\r
+ // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for\r
+ // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not\r
+ // supported on that processor.\r
+ //\r
+ if (ExtendedTopologyEbx.Uint32 != 0) {\r
+ TopologyLeafSupported = TRUE;\r
+\r
+ //\r
+ // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract\r
+ // the SMT sub-field of x2APIC ID.\r
+ //\r
+ LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
+ ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r
+ ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;\r
+\r
+ //\r
+ // Software must not assume any "level type" encoding\r
+ // value to be related to any sub-leaf index, except sub-leaf 0.\r
+ //\r
+ SubIndex = 1;\r
+ do {\r
+ AsmCpuidEx(\r
+ CPUID_EXTENDED_TOPOLOGY,\r
+ SubIndex,\r
+ &ExtendedTopologyEax.Uint32,\r
+ NULL,\r
+ &ExtendedTopologyEcx.Uint32,\r
+ NULL\r
+ );\r
+ LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
+ if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {\r
+ CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;\r
+ break;\r
+ }\r
+ SubIndex++;\r
+ } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);\r
+ }\r
+ }\r
+\r
+ if (!TopologyLeafSupported) {\r
+ AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);\r
+ MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;\r
+ if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {\r
+ AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);\r
+ MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;\r
+ }\r
+ else {\r
+ //\r
+ // Must be a single-core processor.\r
+ //\r
+ MaxCoresPerPackage = 1;\r
+ }\r
+\r
+ ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r
+ CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }\r
+\r
+ if (Thread != NULL) {\r
+ *Thread = InitialApicId & ((1 << ThreadBits) - 1);\r
+ }\r
+ if (Core != NULL) {\r
+ *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);\r
+ }\r
+ if (Package != NULL) {\r
+ *Package = (InitialApicId >> (ThreadBits + CoreBits));\r
+ }\r
+}\r
return Enabled;\r
}\r
\r
-/**\r
- Get CPU Package/Core/Thread location information.\r
-\r
- @param[in] InitialApicId CPU APIC ID\r
- @param[out] Location Pointer to CPU location information\r
-**/\r
-VOID\r
-ExtractProcessorLocation (\r
- IN UINT32 InitialApicId,\r
- OUT EFI_CPU_PHYSICAL_LOCATION *Location\r
- )\r
-{\r
- BOOLEAN TopologyLeafSupported;\r
- UINTN ThreadBits;\r
- UINTN CoreBits;\r
- CPUID_VERSION_INFO_EBX VersionInfoEbx;\r
- CPUID_VERSION_INFO_EDX VersionInfoEdx;\r
- CPUID_CACHE_PARAMS_EAX CacheParamsEax;\r
- CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;\r
- CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;\r
- CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;\r
- UINT32 MaxCpuIdIndex;\r
- UINT32 SubIndex;\r
- UINTN LevelType;\r
- UINT32 MaxLogicProcessorsPerPackage;\r
- UINT32 MaxCoresPerPackage;\r
-\r
- //\r
- // Check if the processor is capable of supporting more than one logical processor.\r
- //\r
- AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r
- if (VersionInfoEdx.Bits.HTT == 0) {\r
- Location->Thread = 0;\r
- Location->Core = 0;\r
- Location->Package = 0;\r
- return;\r
- }\r
-\r
- ThreadBits = 0;\r
- CoreBits = 0;\r
-\r
- //\r
- // Assume three-level mapping of APIC ID: Package:Core:SMT.\r
- //\r
-\r
- TopologyLeafSupported = FALSE;\r
- //\r
- // Get the max index of basic CPUID\r
- //\r
- AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r
-\r
- //\r
- // If the extended topology enumeration leaf is available, it\r
- // is the preferred mechanism for enumerating topology.\r
- //\r
- if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r
- AsmCpuidEx (\r
- CPUID_EXTENDED_TOPOLOGY,\r
- 0,\r
- &ExtendedTopologyEax.Uint32,\r
- &ExtendedTopologyEbx.Uint32,\r
- &ExtendedTopologyEcx.Uint32,\r
- NULL\r
- );\r
- //\r
- // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for\r
- // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not\r
- // supported on that processor.\r
- //\r
- if (ExtendedTopologyEbx.Uint32 != 0) {\r
- TopologyLeafSupported = TRUE;\r
-\r
- //\r
- // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract\r
- // the SMT sub-field of x2APIC ID.\r
- //\r
- LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
- ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r
- ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;\r
-\r
- //\r
- // Software must not assume any "level type" encoding\r
- // value to be related to any sub-leaf index, except sub-leaf 0.\r
- //\r
- SubIndex = 1;\r
- do {\r
- AsmCpuidEx (\r
- CPUID_EXTENDED_TOPOLOGY,\r
- SubIndex,\r
- &ExtendedTopologyEax.Uint32,\r
- NULL,\r
- &ExtendedTopologyEcx.Uint32,\r
- NULL\r
- );\r
- LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
- if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {\r
- CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;\r
- break;\r
- }\r
- SubIndex++;\r
- } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);\r
- }\r
- }\r
-\r
- if (!TopologyLeafSupported) {\r
- AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);\r
- MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;\r
- if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {\r
- AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);\r
- MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;\r
- } else {\r
- //\r
- // Must be a single-core processor.\r
- //\r
- MaxCoresPerPackage = 1;\r
- }\r
-\r
- ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r
- CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);\r
- }\r
-\r
- Location->Thread = InitialApicId & ((1 << ThreadBits) - 1);\r
- Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);\r
- Location->Package = (InitialApicId >> (ThreadBits + CoreBits));\r
-}\r
-\r
/**\r
Worker function for SwitchBSP().\r
\r
//\r
// Get processor location information\r
//\r
- ExtractProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId, &ProcessorInfoBuffer->Location);\r
+ GetProcessorLocation (\r
+ CpuMpData->CpuData[ProcessorNumber].ApicId,\r
+ &ProcessorInfoBuffer->Location.Package,\r
+ &ProcessorInfoBuffer->Location.Core,\r
+ &ProcessorInfoBuffer->Location.Thread\r
+ );\r
\r
if (HealthData != NULL) {\r
HealthData->Uint32 = CpuMpData->CpuData[ProcessorNumber].Health;\r
SmmRegisterExceptionHandler\r
};\r
\r
-/**\r
- Get Package ID/Core ID/Thread ID of a processor.\r
-\r
- APIC ID must be an initial APIC ID.\r
-\r
- The algorithm below assumes the target system has symmetry across physical package boundaries\r
- with respect to the number of logical processors per package, number of cores per package.\r
-\r
- @param ApicId APIC ID of the target logical processor.\r
- @param Location Returns the processor location information.\r
-**/\r
-VOID\r
-SmmGetProcessorLocation (\r
- IN UINT32 ApicId,\r
- OUT EFI_CPU_PHYSICAL_LOCATION *Location\r
- )\r
-{\r
- UINTN ThreadBits;\r
- UINTN CoreBits;\r
- UINT32 RegEax;\r
- UINT32 RegEbx;\r
- UINT32 RegEcx;\r
- UINT32 RegEdx;\r
- UINT32 MaxCpuIdIndex;\r
- UINT32 SubIndex;\r
- UINTN LevelType;\r
- UINT32 MaxLogicProcessorsPerPackage;\r
- UINT32 MaxCoresPerPackage;\r
- BOOLEAN TopologyLeafSupported;\r
-\r
- ASSERT (Location != NULL);\r
-\r
- ThreadBits = 0;\r
- CoreBits = 0;\r
- TopologyLeafSupported = FALSE;\r
-\r
- //\r
- // Check if the processor is capable of supporting more than one logical processor.\r
- //\r
- AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);\r
- ASSERT ((RegEdx & BIT28) != 0);\r
-\r
- //\r
- // Assume three-level mapping of APIC ID: Package:Core:SMT.\r
- //\r
-\r
- //\r
- // Get the max index of basic CPUID\r
- //\r
- AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r
-\r
- //\r
- // If the extended topology enumeration leaf is available, it\r
- // is the preferred mechanism for enumerating topology.\r
- //\r
- if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r
- AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, &RegEcx, NULL);\r
- //\r
- // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for\r
- // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not\r
- // supported on that processor.\r
- //\r
- if ((RegEbx & 0xffff) != 0) {\r
- TopologyLeafSupported = TRUE;\r
-\r
- //\r
- // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract\r
- // the SMT sub-field of x2APIC ID.\r
- //\r
- LevelType = (RegEcx >> 8) & 0xff;\r
- ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r
- if ((RegEbx & 0xffff) > 1 ) {\r
- ThreadBits = RegEax & 0x1f;\r
- } else {\r
- //\r
- // HT is not supported\r
- //\r
- ThreadBits = 0;\r
- }\r
-\r
- //\r
- // Software must not assume any "level type" encoding\r
- // value to be related to any sub-leaf index, except sub-leaf 0.\r
- //\r
- SubIndex = 1;\r
- do {\r
- AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL, &RegEcx, NULL);\r
- LevelType = (RegEcx >> 8) & 0xff;\r
- if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {\r
- CoreBits = (RegEax & 0x1f) - ThreadBits;\r
- break;\r
- }\r
- SubIndex++;\r
- } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);\r
- }\r
- }\r
-\r
- if (!TopologyLeafSupported) {\r
- AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);\r
- MaxLogicProcessorsPerPackage = (RegEbx >> 16) & 0xff;\r
- if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {\r
- AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL);\r
- MaxCoresPerPackage = (RegEax >> 26) + 1;\r
- } else {\r
- //\r
- // Must be a single-core processor.\r
- //\r
- MaxCoresPerPackage = 1;\r
- }\r
-\r
- ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r
- CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);\r
- }\r
-\r
- Location->Thread = ApicId & ~((-1) << ThreadBits);\r
- Location->Core = (ApicId >> ThreadBits) & ~((-1) << CoreBits);\r
- Location->Package = (ApicId >> (ThreadBits+ CoreBits));\r
-}\r
-\r
/**\r
Gets processor information on the requested processor at the instant this call is made.\r
\r
gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) {\r
gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId;\r
gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0;\r
- SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate->ProcessorInfo[Index].Location);\r
+ GetProcessorLocation (\r
+ (UINT32)ProcessorId,\r
+ &gSmmCpuPrivate->ProcessorInfo[Index].Location.Package,\r
+ &gSmmCpuPrivate->ProcessorInfo[Index].Location.Core,\r
+ &gSmmCpuPrivate->ProcessorInfo[Index].Location.Thread\r
+ );\r
\r
*ProcessorNumber = Index;\r
gSmmCpuPrivate->Operation[Index] = SmmCpuAdd;\r