EHCI driver need enable routine and disable Legacy USB

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@2233 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/EdkModulePkg/Bus/Pci/Ehci/Dxe/Debug.c b/EdkModulePkg/Bus/Pci/Ehci/Dxe/Debug.c
new file mode 100644 (file)
index 0000000..d994212
--- /dev/null
+++ b/EdkModulePkg/Bus/Pci/Ehci/Dxe/Debug.c
@@ -0,0 +1,52 @@
+/*++\r
+\r
+Copyright (c) 2006, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+Module Name:\r
+\r
+    Debug.c\r
+\r
+Abstract:\r
+\r
+\r
+Revision History\r
+--*/\r
+\r
+\r
+#include "Ehci.h"\r
+\r
+void \r
+DumpEHCIPortsStatus (\r
+  IN USB2_HC_DEV    *HcDev\r
+  )\r
+{\r
+  UINT8       PortNumber;\r
+  UINT8       Index;\r
+  UINT32      Value;\r
+\r
+  ReadEhcCapabiltiyReg (\r
+     HcDev,\r
+     HCSPARAMS,\r
+     &Value\r
+     );\r
+\r
+  PortNumber = (UINT8) (Value & HCSP_NPORTS);\r
+\r
+  for (Index = 0; Index < PortNumber; Index++) {\r
+    ReadEhcOperationalReg (\r
+      HcDev,\r
+      PORTSC + 4 * Index,\r
+      &Value\r
+      );\r
+     DEBUG((gEHCDebugLevel, "Port[%d] = 0x%x\n", Index, Value));\r
+  }\r
+}\r
+\r
+\r

diff --git a/EdkModulePkg/Bus/Pci/Ehci/Dxe/Ehci.c b/EdkModulePkg/Bus/Pci/Ehci/Dxe/Ehci.c
index c6105eb0b545952ea47fa3680337ea3579152aa3..d573532f7e07cf44c08d5eede736eefd82849a91 100644 (file)
--- a/EdkModulePkg/Bus/Pci/Ehci/Dxe/Ehci.c
+++ b/EdkModulePkg/Bus/Pci/Ehci/Dxe/Ehci.c
@@ -441,6 +441,13 @@ EhciDriverBindingStart (
     Status = EFI_DEVICE_ERROR;\r
     goto uninstall_usb2hc_protocol;\r
   }\r
+\r
+  ClearLegacySupport (HcDev);\r
+  HostReset (HcDev);\r
+\r
+  DEBUG_CODE (\r
+   DumpEHCIPortsStatus (HcDev);\r
+  );\r
   \r
   //\r
   // Create and Init Perodic Frame List\r

diff --git a/EdkModulePkg/Bus/Pci/Ehci/Dxe/Ehci.h b/EdkModulePkg/Bus/Pci/Ehci/Dxe/Ehci.h
index 035d3302bd502489a0a18fbc89b6a987a85b3d16..eb0508fce47921a0f3067cc8e271dce041bce037 100644 (file)
--- a/EdkModulePkg/Bus/Pci/Ehci/Dxe/Ehci.h
+++ b/EdkModulePkg/Bus/Pci/Ehci/Dxe/Ehci.h
@@ -2681,4 +2681,18 @@ Returns:
 --*/\r
 ;\r
 \r
+VOID\r
+ClearLegacySupport (\r
+  IN USB2_HC_DEV     *HcDev\r
+  );\r
+\r
+VOID\r
+HostReset (\r
+  IN USB2_HC_DEV    *HcDev\r
+  );\r
+\r
+VOID \r
+DumpEHCIPortsStatus (\r
+  IN USB2_HC_DEV    *HcDev\r
+  );\r
 #endif\r

diff --git a/EdkModulePkg/Bus/Pci/Ehci/Dxe/Ehci.msa b/EdkModulePkg/Bus/Pci/Ehci/Dxe/Ehci.msa
index b260dfd08094b3e4e40b14911b9211b2b9baae69..d4af1f85bfc2db6e2d2a2f8b6edfdaa943c4a9e9 100644 (file)
--- a/EdkModulePkg/Bus/Pci/Ehci/Dxe/Ehci.msa
+++ b/EdkModulePkg/Bus/Pci/Ehci/Dxe/Ehci.msa
@@ -49,6 +49,7 @@
   </LibraryClassDefinitions>\r
   <SourceFiles>\r
     <Filename>Ehci.c</Filename>\r
+    <Filename>Debug.c</Filename>\r
     <Filename>EhciMem.c</Filename>\r
     <Filename>EhciReg.c</Filename>\r
     <Filename>EhciSched.c</Filename>\r

diff --git a/EdkModulePkg/Bus/Pci/Ehci/Dxe/EhciReg.c b/EdkModulePkg/Bus/Pci/Ehci/Dxe/EhciReg.c
index 9ce816ecc97405473f27056d65a04197e8f75f4b..70d1d5cf382459eb31e8cec18aa671a290dc95c3 100644 (file)
--- a/EdkModulePkg/Bus/Pci/Ehci/Dxe/EhciReg.c
+++ b/EdkModulePkg/Bus/Pci/Ehci/Dxe/EhciReg.c
@@ -22,6 +22,75 @@ Revision History
 #include "Ehci.h"\r
 \r
 \r
+VOID\r
+HostReset (\r
+  IN USB2_HC_DEV    *HcDev\r
+  )\r
+{\r
+  UINT32  Value;\r
+  UINT32  TimeOut;\r
+ \r
+  ReadEhcOperationalReg (\r
+    HcDev,\r
+    USBCMD,\r
+    &Value\r
+    );\r
+\r
+  Value = Value & (~USBCMD_RS);\r
+  WriteEhcOperationalReg (\r
+    HcDev,\r
+    USBCMD,\r
+    Value\r
+    );\r
+\r
+  TimeOut = 40;\r
+  while (TimeOut --) {\r
+    gBS->Stall (500);\r
+    ReadEhcOperationalReg (\r
+      HcDev,\r
+      USBSTS,\r
+      &Value\r
+      );\r
+    if ((Value & USBSTS_HCH) != 0) {\r
+      break;\r
+    }\r
+  }\r
+\r
+  if (TimeOut == 0) {\r
+    DEBUG((gEHCErrorLevel, "TimeOut for clearing Run/Stop bit\n"));\r
+  }\r
+\r
+  ReadEhcOperationalReg (\r
+    HcDev,\r
+    USBCMD,\r
+    &Value\r
+    );\r
+  Value = Value | USBCMD_HCRESET;\r
+  WriteEhcOperationalReg (\r
+    HcDev,\r
+    USBCMD,\r
+    Value\r
+    );\r
+\r
+  TimeOut = 40;\r
+  while (TimeOut --) {\r
+    gBS->Stall (500);\r
+    ReadEhcOperationalReg (\r
+      HcDev,\r
+      USBCMD,\r
+      &Value\r
+      );\r
+    if ((Value & USBCMD_HCRESET) == 0) {\r
+      break;\r
+    }\r
+  }\r
+\r
+  if (TimeOut == 0) {\r
+    DEBUG((gEHCErrorLevel, "TimeOut for Host Reset\n"));\r
+  }\r
+\r
+}\r
+\r
 EFI_STATUS\r
 ReadEhcCapabiltiyReg (\r
   IN USB2_HC_DEV             *HcDev,\r
@@ -129,6 +198,126 @@ Returns:
                              );\r
 }\r
 \r
+VOID\r
+ClearLegacySupport (\r
+  IN USB2_HC_DEV     *HcDev\r
+  )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+  Stop the legacy USB SMI\r
+\r
+Arguments:\r
+\r
+  HcDev - USB2_HC_DEV\r
+\r
+Returns:\r
+\r
+  EFI_SUCCESS       Success\r
+  EFI_DEVICE_ERROR  Fail\r
+\r
+--*/\r
+{\r
+  UINT32  EECP;\r
+  UINT32  Value;\r
+  UINT32  TimeOut;\r
+\r
+  ReadEhcCapabiltiyReg (\r
+    HcDev,\r
+    HCCPARAMS,\r
+    &EECP\r
+    );\r
+\r
+  EECP = (EECP >> 8) & 0xFF;\r
+\r
+  DEBUG ((gEHCDebugLevel, "EHCI: EECPBase = 0x%x\n", EECP));\r
+\r
+\r
+  HcDev->PciIo->Pci.Read (\r
+                     HcDev->PciIo,\r
+                     EfiPciIoWidthUint32,\r
+                     EECP,\r
+                     1,\r
+                     &Value \r
+                     );\r
+\r
+  DEBUG((gEHCDebugLevel, "EECP[0] = 0x%x\n", Value));\r
+\r
+  HcDev->PciIo->Pci.Read (\r
+                     HcDev->PciIo,\r
+                     EfiPciIoWidthUint32,\r
+                     EECP + 0x4,\r
+                     1,\r
+                     &Value \r
+                     );\r
+\r
+  DEBUG((gEHCDebugLevel, "EECP[4] = 0x%x\n", Value));\r
+\r
+  HcDev->PciIo->Pci.Read (\r
+                     HcDev->PciIo,\r
+                     EfiPciIoWidthUint32,\r
+                     EECP,\r
+                     1,\r
+                     &Value \r
+                     );\r
+\r
+  Value = Value | (0x1 << 24);\r
+  DEBUG((gEHCErrorLevel, "Value Written = 0x%x\n", Value));\r
+\r
+  HcDev->PciIo->Pci.Write (\r
+                     HcDev->PciIo,\r
+                     EfiPciIoWidthUint32,\r
+                     EECP,\r
+                     1,\r
+                     &Value \r
+                     );\r
+\r
+ TimeOut = 40;\r
+ while (TimeOut --) {\r
+   gBS->Stall (500);\r
+\r
+   HcDev->PciIo->Pci.Read (\r
+                      HcDev->PciIo,\r
+                      EfiPciIoWidthUint32,\r
+                      EECP,\r
+                      1,\r
+                      &Value \r
+                      );\r
+  if ((Value & 0x01010000) == 0x01000000) {\r
+    break;\r
+  }\r
+ }\r
+\r
+  if (TimeOut == 0) {\r
+    DEBUG((gEHCErrorLevel, "Timeout for getting HC OS Owned Semaphore\n" ));\r
+  } \r
+  \r
+  DEBUG((gEHCErrorLevel, "After Release Value\n" ));\r
+\r
+  HcDev->PciIo->Pci.Read (\r
+                     HcDev->PciIo,\r
+                     EfiPciIoWidthUint32,\r
+                     EECP,\r
+                     1,\r
+                     &Value \r
+                     );\r
+\r
+  DEBUG((gEHCDebugLevel, "EECP[0] = 0x%x\n", Value));\r
+\r
+  HcDev->PciIo->Pci.Read (\r
+                     HcDev->PciIo,\r
+                     EfiPciIoWidthUint32,\r
+                     EECP + 0x4,\r
+                     1,\r
+                     &Value \r
+                     );\r
+\r
+  DEBUG((gEHCDebugLevel, "EECP[4] = 0x%x\n", Value));\r
+\r
+\r
+}\r
+\r
 EFI_STATUS\r
 GetCapabilityLen (\r
   IN USB2_HC_DEV     *HcDev\r