// Init Pci Device PRT PRW information structure from PCD\r
//\r
mConfigData = (PCI_DEVICE_SETTING *)AllocateZeroPool (sizeof (PCI_DEVICE_SETTING));\r
- ASSERT_EFI_ERROR (mConfigData);\r
+ ASSERT (mConfigData != NULL);\r
InitPciDeviceInfoStructure (mConfigData);\r
//\r
// Get the Acpi SDT protocol for manipulation on acpi table\r
//ASSERT (NumberOfCPUs <= 2 && NumberOfCPUs > 0);\r
MadtSize = GetAcutalMadtTableSize (&MadtConfigData, NumberOfCPUs);\r
Madt = (EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *)AllocateZeroPool (MadtSize);\r
- ASSERT_EFI_ERROR (Madt);\r
+ ASSERT (Madt != NULL);\r
//\r
// Initialize MADT Header information\r
//\r
//\r
\r
SpiProtocol = LocateSpiProtocol (NULL); // This routine will not be called in SMM.\r
- ASSERT_EFI_ERROR (SpiProtocol != NULL);\r
+ ASSERT (SpiProtocol != NULL);\r
if (SpiProtocol != NULL) {\r
Status = SpiProtocol->Lock (SpiProtocol);\r
\r
// memory above 1MB. So Memory Callback can set cache for the system memory\r
// correctly on S3 boot path, just like it does on Normal boot path.\r
//\r
- ASSERT_EFI_ERROR ((S3MemoryRangeData->SystemMemoryLength - 0x100000) > 0);\r
+ ASSERT ((S3MemoryRangeData->SystemMemoryLength - 0x100000) > 0);\r
BuildResourceDescriptorHob (\r
EFI_RESOURCE_SYSTEM_MEMORY,\r
(\r