--- /dev/null
+/** @file\r
+ PCI Library functions that use\r
+ (a) I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles, layering\r
+ on top of one PCI CF8 Library instance; or\r
+ (b) PCI Library functions that use the 256 MB PCI Express MMIO window to\r
+ perform PCI Configuration cycles, layering on PCI Express Library.\r
+\r
+ The decision is made in the entry point function, based on the OVMF platform\r
+ type, and then adhered to during the lifetime of the client module.\r
+\r
+ Copyright (C) 2016, Red Hat, Inc.\r
+\r
+ Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include <Base.h>\r
+\r
+#include <IndustryStandard/Q35MchIch9.h>\r
+\r
+#include <Library/PciLib.h>\r
+#include <Library/PciCf8Lib.h>\r
+#include <Library/PciExpressLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+STATIC BOOLEAN mRunningOnQ35;\r
+\r
+RETURN_STATUS\r
+EFIAPI\r
+InitializeConfigAccessMethod (\r
+ VOID\r
+ )\r
+{\r
+ mRunningOnQ35 = (PcdGet16 (PcdOvmfHostBridgePciDevId) ==\r
+ INTEL_Q35_MCH_DEVICE_ID);\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+ Registers a PCI device so PCI configuration registers may be accessed after \r
+ SetVirtualAddressMap().\r
+ \r
+ Registers the PCI device specified by Address so all the PCI configuration registers \r
+ associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r
+ \r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ \r
+ @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function \r
+ after ExitBootServices().\r
+ @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r
+ at runtime could not be mapped.\r
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r
+ complete the registration.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+PciRegisterForRuntimeAccess (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressRegisterForRuntimeAccess (Address) :\r
+ PciCf8RegisterForRuntimeAccess (Address);\r
+}\r
+\r
+/**\r
+ Reads an 8-bit PCI configuration register.\r
+\r
+ Reads and returns the 8-bit PCI configuration register specified by Address.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+\r
+ @return The read value from the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciRead8 (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressRead8 (Address) :\r
+ PciCf8Read8 (Address);\r
+}\r
+\r
+/**\r
+ Writes an 8-bit PCI configuration register.\r
+\r
+ Writes the 8-bit PCI configuration register specified by Address with the\r
+ value specified by Value. Value is returned. This function must guarantee\r
+ that all PCI read and write operations are serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param Value The value to write.\r
+\r
+ @return The value written to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciWrite8 (\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressWrite8 (Address, Value) :\r
+ PciCf8Write8 (Address, Value);\r
+}\r
+\r
+/**\r
+ Performs a bitwise OR of an 8-bit PCI configuration register with\r
+ an 8-bit value.\r
+\r
+ Reads the 8-bit PCI configuration register specified by Address, performs a\r
+ bitwise OR between the read result and the value specified by\r
+ OrData, and writes the result to the 8-bit PCI configuration register\r
+ specified by Address. The value written to the PCI configuration register is\r
+ returned. This function must guarantee that all PCI read and write operations\r
+ are serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param OrData The value to OR with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciOr8 (\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressOr8 (Address, OrData) :\r
+ PciCf8Or8 (Address, OrData);\r
+}\r
+\r
+/**\r
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
+ value.\r
+\r
+ Reads the 8-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData, and\r
+ writes the result to the 8-bit PCI configuration register specified by\r
+ Address. The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciAnd8 (\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressAnd8 (Address, AndData) :\r
+ PciCf8And8 (Address, AndData);\r
+}\r
+\r
+/**\r
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
+ value, followed a bitwise OR with another 8-bit value.\r
+\r
+ Reads the 8-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData,\r
+ performs a bitwise OR between the result of the AND operation and\r
+ the value specified by OrData, and writes the result to the 8-bit PCI\r
+ configuration register specified by Address. The value written to the PCI\r
+ configuration register is returned. This function must guarantee that all PCI\r
+ read and write operations are serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciAndThenOr8 (\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressAndThenOr8 (Address, AndData, OrData) :\r
+ PciCf8AndThenOr8 (Address, AndData, OrData);\r
+}\r
+\r
+/**\r
+ Reads a bit field of a PCI configuration register.\r
+\r
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is\r
+ specified by the StartBit and the EndBit. The value of the bit field is\r
+ returned.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to read.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+\r
+ @return The value of the bit field read from the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciBitFieldRead8 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressBitFieldRead8 (Address, StartBit, EndBit) :\r
+ PciCf8BitFieldRead8 (Address, StartBit, EndBit);\r
+}\r
+\r
+/**\r
+ Writes a bit field to a PCI configuration register.\r
+\r
+ Writes Value to the bit field of the PCI configuration register. The bit\r
+ field is specified by the StartBit and the EndBit. All other bits in the\r
+ destination PCI configuration register are preserved. The new value of the\r
+ 8-bit register is returned.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param Value The new value of the bit field.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciBitFieldWrite8 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value) :\r
+ PciCf8BitFieldWrite8 (Address, StartBit, EndBit, Value);\r
+}\r
+\r
+/**\r
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r
+ writes the result back to the bit field in the 8-bit port.\r
+\r
+ Reads the 8-bit PCI configuration register specified by Address, performs a\r
+ bitwise OR between the read result and the value specified by\r
+ OrData, and writes the result to the 8-bit PCI configuration register\r
+ specified by Address. The value written to the PCI configuration register is\r
+ returned. This function must guarantee that all PCI read and write operations\r
+ are serialized. Extra left bits in OrData are stripped.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param OrData The value to OR with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciBitFieldOr8 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData) :\r
+ PciCf8BitFieldOr8 (Address, StartBit, EndBit, OrData);\r
+}\r
+\r
+/**\r
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r
+ AND, and writes the result back to the bit field in the 8-bit register.\r
+\r
+ Reads the 8-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData, and\r
+ writes the result to the 8-bit PCI configuration register specified by\r
+ Address. The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized. Extra left bits in AndData are stripped.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciBitFieldAnd8 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData) :\r
+ PciCf8BitFieldAnd8 (Address, StartBit, EndBit, AndData);\r
+}\r
+\r
+/**\r
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
+ bitwise OR, and writes the result back to the bit field in the\r
+ 8-bit port.\r
+\r
+ Reads the 8-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND followed by a bitwise OR between the read result and\r
+ the value specified by AndData, and writes the result to the 8-bit PCI\r
+ configuration register specified by Address. The value written to the PCI\r
+ configuration register is returned. This function must guarantee that all PCI\r
+ read and write operations are serialized. Extra left bits in both AndData and\r
+ OrData are stripped.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciBitFieldAndThenOr8 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData) :\r
+ PciCf8BitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData);\r
+}\r
+\r
+/**\r
+ Reads a 16-bit PCI configuration register.\r
+\r
+ Reads and returns the 16-bit PCI configuration register specified by Address.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+\r
+ @return The read value from the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciRead16 (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressRead16 (Address) :\r
+ PciCf8Read16 (Address);\r
+}\r
+\r
+/**\r
+ Writes a 16-bit PCI configuration register.\r
+\r
+ Writes the 16-bit PCI configuration register specified by Address with the\r
+ value specified by Value. Value is returned. This function must guarantee\r
+ that all PCI read and write operations are serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param Value The value to write.\r
+\r
+ @return The value written to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciWrite16 (\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressWrite16 (Address, Value) :\r
+ PciCf8Write16 (Address, Value);\r
+}\r
+\r
+/**\r
+ Performs a bitwise OR of a 16-bit PCI configuration register with\r
+ a 16-bit value.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address, performs a\r
+ bitwise OR between the read result and the value specified by\r
+ OrData, and writes the result to the 16-bit PCI configuration register\r
+ specified by Address. The value written to the PCI configuration register is\r
+ returned. This function must guarantee that all PCI read and write operations\r
+ are serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param OrData The value to OR with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciOr16 (\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressOr16 (Address, OrData) :\r
+ PciCf8Or16 (Address, OrData);\r
+}\r
+\r
+/**\r
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
+ value.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData, and\r
+ writes the result to the 16-bit PCI configuration register specified by\r
+ Address. The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciAnd16 (\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressAnd16 (Address, AndData) :\r
+ PciCf8And16 (Address, AndData);\r
+}\r
+\r
+/**\r
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
+ value, followed a bitwise OR with another 16-bit value.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData,\r
+ performs a bitwise OR between the result of the AND operation and\r
+ the value specified by OrData, and writes the result to the 16-bit PCI\r
+ configuration register specified by Address. The value written to the PCI\r
+ configuration register is returned. This function must guarantee that all PCI\r
+ read and write operations are serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciAndThenOr16 (\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressAndThenOr16 (Address, AndData, OrData) :\r
+ PciCf8AndThenOr16 (Address, AndData, OrData);\r
+}\r
+\r
+/**\r
+ Reads a bit field of a PCI configuration register.\r
+\r
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is\r
+ specified by the StartBit and the EndBit. The value of the bit field is\r
+ returned.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to read.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+\r
+ @return The value of the bit field read from the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciBitFieldRead16 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressBitFieldRead16 (Address, StartBit, EndBit) :\r
+ PciCf8BitFieldRead16 (Address, StartBit, EndBit);\r
+}\r
+\r
+/**\r
+ Writes a bit field to a PCI configuration register.\r
+\r
+ Writes Value to the bit field of the PCI configuration register. The bit\r
+ field is specified by the StartBit and the EndBit. All other bits in the\r
+ destination PCI configuration register are preserved. The new value of the\r
+ 16-bit register is returned.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param Value The new value of the bit field.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciBitFieldWrite16 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value) :\r
+ PciCf8BitFieldWrite16 (Address, StartBit, EndBit, Value);\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r
+ writes the result back to the bit field in the 16-bit port.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address, performs a\r
+ bitwise OR between the read result and the value specified by\r
+ OrData, and writes the result to the 16-bit PCI configuration register\r
+ specified by Address. The value written to the PCI configuration register is\r
+ returned. This function must guarantee that all PCI read and write operations\r
+ are serialized. Extra left bits in OrData are stripped.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param OrData The value to OR with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciBitFieldOr16 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData) :\r
+ PciCf8BitFieldOr16 (Address, StartBit, EndBit, OrData);\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r
+ AND, and writes the result back to the bit field in the 16-bit register.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData, and\r
+ writes the result to the 16-bit PCI configuration register specified by\r
+ Address. The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized. Extra left bits in AndData are stripped.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciBitFieldAnd16 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData) :\r
+ PciCf8BitFieldAnd16 (Address, StartBit, EndBit, AndData);\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r
+ bitwise OR, and writes the result back to the bit field in the\r
+ 16-bit port.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND followed by a bitwise OR between the read result and\r
+ the value specified by AndData, and writes the result to the 16-bit PCI\r
+ configuration register specified by Address. The value written to the PCI\r
+ configuration register is returned. This function must guarantee that all PCI\r
+ read and write operations are serialized. Extra left bits in both AndData and\r
+ OrData are stripped.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciBitFieldAndThenOr16 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData) :\r
+ PciCf8BitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);\r
+}\r
+\r
+/**\r
+ Reads a 32-bit PCI configuration register.\r
+\r
+ Reads and returns the 32-bit PCI configuration register specified by Address.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+\r
+ @return The read value from the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciRead32 (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressRead32 (Address) :\r
+ PciCf8Read32 (Address);\r
+}\r
+\r
+/**\r
+ Writes a 32-bit PCI configuration register.\r
+\r
+ Writes the 32-bit PCI configuration register specified by Address with the\r
+ value specified by Value. Value is returned. This function must guarantee\r
+ that all PCI read and write operations are serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param Value The value to write.\r
+\r
+ @return The value written to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciWrite32 (\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressWrite32 (Address, Value) :\r
+ PciCf8Write32 (Address, Value);\r
+}\r
+\r
+/**\r
+ Performs a bitwise OR of a 32-bit PCI configuration register with\r
+ a 32-bit value.\r
+\r
+ Reads the 32-bit PCI configuration register specified by Address, performs a\r
+ bitwise OR between the read result and the value specified by\r
+ OrData, and writes the result to the 32-bit PCI configuration register\r
+ specified by Address. The value written to the PCI configuration register is\r
+ returned. This function must guarantee that all PCI read and write operations\r
+ are serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param OrData The value to OR with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciOr32 (\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressOr32 (Address, OrData) :\r
+ PciCf8Or32 (Address, OrData);\r
+}\r
+\r
+/**\r
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
+ value.\r
+\r
+ Reads the 32-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData, and\r
+ writes the result to the 32-bit PCI configuration register specified by\r
+ Address. The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciAnd32 (\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressAnd32 (Address, AndData) :\r
+ PciCf8And32 (Address, AndData);\r
+}\r
+\r
+/**\r
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
+ value, followed a bitwise OR with another 32-bit value.\r
+\r
+ Reads the 32-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData,\r
+ performs a bitwise OR between the result of the AND operation and\r
+ the value specified by OrData, and writes the result to the 32-bit PCI\r
+ configuration register specified by Address. The value written to the PCI\r
+ configuration register is returned. This function must guarantee that all PCI\r
+ read and write operations are serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciAndThenOr32 (\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressAndThenOr32 (Address, AndData, OrData) :\r
+ PciCf8AndThenOr32 (Address, AndData, OrData);\r
+}\r
+\r
+/**\r
+ Reads a bit field of a PCI configuration register.\r
+\r
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is\r
+ specified by the StartBit and the EndBit. The value of the bit field is\r
+ returned.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to read.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+\r
+ @return The value of the bit field read from the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciBitFieldRead32 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressBitFieldRead32 (Address, StartBit, EndBit) :\r
+ PciCf8BitFieldRead32 (Address, StartBit, EndBit);\r
+}\r
+\r
+/**\r
+ Writes a bit field to a PCI configuration register.\r
+\r
+ Writes Value to the bit field of the PCI configuration register. The bit\r
+ field is specified by the StartBit and the EndBit. All other bits in the\r
+ destination PCI configuration register are preserved. The new value of the\r
+ 32-bit register is returned.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param Value The new value of the bit field.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciBitFieldWrite32 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value) :\r
+ PciCf8BitFieldWrite32 (Address, StartBit, EndBit, Value);\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r
+ writes the result back to the bit field in the 32-bit port.\r
+\r
+ Reads the 32-bit PCI configuration register specified by Address, performs a\r
+ bitwise OR between the read result and the value specified by\r
+ OrData, and writes the result to the 32-bit PCI configuration register\r
+ specified by Address. The value written to the PCI configuration register is\r
+ returned. This function must guarantee that all PCI read and write operations\r
+ are serialized. Extra left bits in OrData are stripped.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param OrData The value to OR with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciBitFieldOr32 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData) :\r
+ PciCf8BitFieldOr32 (Address, StartBit, EndBit, OrData);\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r
+ AND, and writes the result back to the bit field in the 32-bit register.\r
+\r
+ Reads the 32-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData, and\r
+ writes the result to the 32-bit PCI configuration register specified by\r
+ Address. The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized. Extra left bits in AndData are stripped.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciBitFieldAnd32 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData) :\r
+ PciCf8BitFieldAnd32 (Address, StartBit, EndBit, AndData);\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r
+ bitwise OR, and writes the result back to the bit field in the\r
+ 32-bit port.\r
+\r
+ Reads the 32-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND followed by a bitwise OR between the read result and\r
+ the value specified by AndData, and writes the result to the 32-bit PCI\r
+ configuration register specified by Address. The value written to the PCI\r
+ configuration register is returned. This function must guarantee that all PCI\r
+ read and write operations are serialized. Extra left bits in both AndData and\r
+ OrData are stripped.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciBitFieldAndThenOr32 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData) :\r
+ PciCf8BitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData);\r
+}\r
+\r
+/**\r
+ Reads a range of PCI configuration registers into a caller supplied buffer.\r
+\r
+ Reads the range of PCI configuration registers specified by StartAddress and\r
+ Size into the buffer specified by Buffer. This function only allows the PCI\r
+ configuration registers from a single PCI function to be read. Size is\r
+ returned. When possible 32-bit PCI configuration read cycles are used to read\r
+ from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
+ and 16-bit PCI configuration read cycles may be used at the beginning and the\r
+ end of the range.\r
+\r
+ If StartAddress > 0x0FFFFFFF, then ASSERT().\r
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
+ If Size > 0 and Buffer is NULL, then ASSERT().\r
+\r
+ @param StartAddress The starting address that encodes the PCI Bus, Device,\r
+ Function and Register.\r
+ @param Size The size in bytes of the transfer.\r
+ @param Buffer The pointer to a buffer receiving the data read.\r
+\r
+ @return Size\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+PciReadBuffer (\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressReadBuffer (StartAddress, Size, Buffer) :\r
+ PciCf8ReadBuffer (StartAddress, Size, Buffer);\r
+}\r
+\r
+/**\r
+ Copies the data in a caller supplied buffer to a specified range of PCI\r
+ configuration space.\r
+\r
+ Writes the range of PCI configuration registers specified by StartAddress and\r
+ Size from the buffer specified by Buffer. This function only allows the PCI\r
+ configuration registers from a single PCI function to be written. Size is\r
+ returned. When possible 32-bit PCI configuration write cycles are used to\r
+ write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
+ and the end of the range.\r
+\r
+ If StartAddress > 0x0FFFFFFF, then ASSERT().\r
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
+ If Size > 0 and Buffer is NULL, then ASSERT().\r
+\r
+ @param StartAddress The starting address that encodes the PCI Bus, Device,\r
+ Function and Register.\r
+ @param Size The size in bytes of the transfer.\r
+ @param Buffer The pointer to a buffer containing the data to write.\r
+\r
+ @return Size written to StartAddress.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+PciWriteBuffer (\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ return mRunningOnQ35 ?\r
+ PciExpressWriteBuffer (StartAddress, Size, Buffer) :\r
+ PciCf8WriteBuffer (StartAddress, Size, Buffer);\r
+}\r
projects / mirror_edk2.git / commitdiff