--- /dev/null
+#\r
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ PLATFORM_NAME = ArmVExpress-FVP-AArch64\r
+ PLATFORM_GUID = 0de70077-9b3b-43bf-ba38-0ea37d77141b\r
+ PLATFORM_VERSION = 0.1\r
+ DSC_SPECIFICATION = 0x00010005\r
+ OUTPUT_DIRECTORY = Build/ArmVExpress-FVP-AArch64\r
+ SUPPORTED_ARCHITECTURES = AARCH64\r
+ BUILD_TARGETS = DEBUG|RELEASE\r
+ SKUID_IDENTIFIER = DEFAULT\r
+ FLASH_DEFINITION = ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.fdf\r
+\r
+!include ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc\r
+\r
+[LibraryClasses.common]\r
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf\r
+ ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexAEMv8Lib/ArmCortexAEMv8Lib.inf\r
+ ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf\r
+\r
+ ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf\r
+ NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf\r
+!ifndef ARM_FOUNDATION_FVP\r
+ LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf\r
+!endif\r
+\r
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf\r
+\r
+[LibraryClasses.common.SEC]\r
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf\r
+ ArmPlatformSecLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/ArmVExpressSecLib.inf\r
+ ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec.inf\r
+\r
+[BuildOptions]\r
+ GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM\r
+\r
+\r
+################################################################################\r
+#\r
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform\r
+#\r
+################################################################################\r
+\r
+[PcdsFeatureFlag.common]\r
+\r
+ ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.\r
+ # It could be set FALSE to save size.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE\r
+\r
+ ## FVP platforms support hardware power control\r
+ # Disabled for now as we have a version mismatch.\r
+ gArmTokenSpaceGuid.PcdArmPsciSupport|FALSE\r
+\r
+[PcdsFixedAtBuild.common]\r
+ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Fixed Virtual Platform"\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ARM-FVP"\r
+\r
+ # Up to 8 cores on Base models. This works fine if model happens to have less.\r
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|8\r
+\r
+ #\r
+ # NV Storage PCDs. Use base of 0x0C000000 for NOR1\r
+ #\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0FFC0000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0FFD0000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000\r
+\r
+ gArmTokenSpaceGuid.PcdVFPEnabled|1\r
+\r
+ # FVP models can have 2 clusters with 4 cpus each\r
+ # Stacks for MPCores in Secure World\r
+ # Trusted SRAM (DRAM on Foundation model)\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x04000000\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x1000\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x800\r
+\r
+ # Stacks for MPCores in Normal World\r
+ # Non-Trusted SRAM\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x2E000000\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x800\r
+\r
+ # System Memory (2GB)\r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000\r
+\r
+ # Size of the region used by UEFI in permanent memory (Reserved 64MB)\r
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000\r
+\r
+ #\r
+ # ARM Pcds\r
+ #\r
+ gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000\r
+\r
+ ## Trustzone enable (to make the transition from EL3 to NS EL2 in ArmPlatformPkg/Sec)\r
+ gArmTokenSpaceGuid.PcdTrustzoneSupport|TRUE\r
+\r
+ #\r
+ # ARM PrimeCell\r
+ #\r
+\r
+ ## SP805 Watchdog - Motherboard Watchdog at 24MHz\r
+ gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x1C0F0000\r
+ gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|24000000\r
+\r
+ ## PL011 - Serial Terminal\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1c090000\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400\r
+\r
+ ## PL031 RealTimeClock\r
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000\r
+\r
+!ifndef ARM_FOUNDATION_FVP\r
+ ## PL111 Versatile Express Motherboard controller\r
+ gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x1C1F0000\r
+\r
+ ## PL180 MMC/SD card controller\r
+ gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x1C010048\r
+ gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000\r
+!endif\r
+\r
+ #\r
+ # ARM General Interrupt Controller\r
+ #\r
+!ifdef ARM_FVP_LEGACY_GICV2_LOCATION\r
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C002000\r
+!else\r
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x2f000000\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C000000\r
+!endif\r
+\r
+ #\r
+ # ARM OS Loader\r
+ #\r
+ # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from SemiHosting"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/Image"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/filesystem.cpio.gz"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0 earlyprintk=pl011,0x1c090000 debug user_debug=31 loglevel=9"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2\r
+ gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/fdt.dtb"\r
+\r
+ # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi()"\r
+\r
+ #\r
+ # ARM Architectual Timer Frequency\r
+ #\r
+ # Set tick frequency value to 120Mhz\r
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|120000000\r
+\r
+################################################################################\r
+#\r
+# Components Section - list of all EDK II Modules needed by this Platform\r
+#\r
+################################################################################\r
+[Components.common]\r
+\r
+ #\r
+ # SEC\r
+ #\r
+ ArmPlatformPkg/Sec/Sec.inf {\r
+ <LibraryClasses>\r
+ # Use the implementation which set the Secure bits\r
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf\r
+ }\r
+\r
+ #\r
+ # PEI Phase modules\r
+ #\r
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf {\r
+ <LibraryClasses>\r
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.inf\r
+ }\r
+ MdeModulePkg/Core/Pei/PeiMain.inf\r
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ }\r
+ ArmPlatformPkg/PlatformPei/PlatformPeim.inf\r
+ ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf\r
+ ArmPkg/Drivers/CpuPei/CpuPei.inf\r
+ IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf\r
+ Nt32Pkg/BootModePei/BootModePei.inf\r
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {\r
+ <LibraryClasses>\r
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf\r
+ }\r
+\r
+ #\r
+ # DXE\r
+ #\r
+ MdeModulePkg/Core/Dxe/DxeMain.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf\r
+ }\r
+\r
+ #\r
+ # Architectural Protocols\r
+ #\r
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
+\r
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+ EmbeddedPkg/SerialDxe/SerialDxe.inf\r
+\r
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+\r
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
+ ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
+!ifndef ARM_FOUNDATION_FVP\r
+ ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
+!endif\r
+ ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf\r
+\r
+ #\r
+ # Semi-hosting filesystem\r
+ #\r
+ ArmPkg/Filesystem/SemihostFs/SemihostFs.inf\r
+\r
+!ifndef ARM_FOUNDATION_FVP\r
+ #\r
+ # Multimedia Card Interface\r
+ #\r
+ EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf\r
+ ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf\r
+!endif\r
+\r
+ #\r
+ # FAT filesystem + GPT/MBR partitioning\r
+ #\r
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+\r
+ #\r
+ # Bds\r
+ #\r
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+ ArmPlatformPkg/Bds/Bds.inf\r
--- /dev/null
+#\r
+# Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+\r
+################################################################################\r
+#\r
+# FD Section\r
+# The [FD] Section is made up of the definition statements and a\r
+# description of what goes into the Flash Device Image. Each FD section\r
+# defines one flash "device" image. A flash device image may be one of\r
+# the following: Removable media bootable image (like a boot floppy\r
+# image,) an Option ROM image (that would be "flashed" into an add-in\r
+# card,) a System "Flash" image (that would be burned into a system's\r
+# flash) or an Update ("Capsule") image that will be used to update and\r
+# existing system flash.\r
+#\r
+################################################################################\r
+\r
+[FD.FVP_AARCH64_EFI_SEC]\r
+BaseAddress = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in SecureROM.\r
+Size = 0x04000000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the device (64MiB).\r
+ErasePolarity = 1\r
+\r
+# This one is tricky, it must be: BlockSize * NumBlocks = Size\r
+BlockSize = 0x00001000\r
+NumBlocks = 0x4000\r
+\r
+################################################################################\r
+#\r
+# Following are lists of FD Region layout which correspond to the locations of different\r
+# images within the flash device.\r
+#\r
+# Regions must be defined in ascending order and may not overlap.\r
+#\r
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by\r
+# the pipe "|" character, followed by the size of the region, also in hex with the leading\r
+# "0x" characters. Like:\r
+# Offset|Size\r
+# PcdOffsetCName|PcdSizeCName\r
+# RegionType <FV, DATA, or FILE>\r
+#\r
+################################################################################\r
+\r
+0x00000000|0x00080000\r
+gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize\r
+FV = FVMAIN_SEC\r
+\r
+[FD.FVP_AARCH64_EFI]\r
+BaseAddress = 0x08000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in Flash0.\r
+Size = 0x04000000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the device (64MiB).\r
+ErasePolarity = 1\r
+\r
+# This one is tricky, it must be: BlockSize * NumBlocks = Size\r
+BlockSize = 0x00001000\r
+NumBlocks = 0x4000\r
+\r
+0x00000000|0x00280000\r
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize\r
+FV = FVMAIN_COMPACT\r
+\r
+################################################################################\r
+#\r
+# FV Section\r
+#\r
+# [FV] section is used to define what components or modules are placed within a flash\r
+# device file. This section also defines order the components and modules are positioned\r
+# within the image. The [FV] section consists of define statements, set statements and\r
+# module statements.\r
+#\r
+################################################################################\r
+\r
+[FV.FVMAIN_SEC]\r
+FvBaseAddress = 0x0 # Secure ROM\r
+FvForceRebase = TRUE\r
+FvAlignment = 16\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+ INF ArmPlatformPkg/Sec/Sec.inf\r
+\r
+\r
+[FV.FvMain]\r
+BlockSize = 0x40\r
+NumBlocks = 0 # This FV gets compressed so make it just big enough\r
+FvAlignment = 16 # FV alignment and FV attributes setting.\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf\r
+\r
+ #\r
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)\r
+ #\r
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
+\r
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+\r
+ #\r
+ # Multiple Console IO support\r
+ #\r
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+ INF EmbeddedPkg/SerialDxe/SerialDxe.inf\r
+\r
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
+ INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
+!ifndef ARM_FOUNDATION_FVP\r
+ INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
+!endif\r
+ INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf\r
+\r
+ #\r
+ # Semi-hosting filesystem\r
+ #\r
+ INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf\r
+\r
+ #\r
+ # FAT filesystem + GPT/MBR partitioning\r
+ #\r
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+ INF FatBinPkg/EnhancedFatDxe/Fat.inf\r
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+\r
+!ifndef ARM_FOUNDATION_FVP\r
+ #\r
+ # Multimedia Card Interface\r
+ #\r
+ INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf\r
+ INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf\r
+!endif\r
+\r
+ #\r
+ # UEFI application (Shell Embedded Boot Loader)\r
+ #\r
+ INF ShellBinPkg/UefiShell/UefiShell.inf\r
+\r
+ #\r
+ # Bds\r
+ #\r
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+ INF ArmPlatformPkg/Bds/Bds.inf\r
+\r
+\r
+[FV.FVMAIN_COMPACT]\r
+FvAlignment = 16\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf\r
+ INF MdeModulePkg/Core/Pei/PeiMain.inf\r
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf\r
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf\r
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf\r
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
+ INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf\r
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf\r
+\r
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {\r
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {\r
+ SECTION FV_IMAGE = FVMAIN\r
+ }\r
+ }\r
+\r
+\r
+################################################################################\r
+#\r
+# Rules are use with the [FV] section's module INF type to define\r
+# how an FFS file is created for a given INF file. The following Rule are the default\r
+# rules for the different module type. User can add the customized rules to define the\r
+# content of the FFS file.\r
+#\r
+################################################################################\r
+\r
+\r
+############################################################################\r
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #\r
+############################################################################\r
+#\r
+#[Rule.Common.DXE_DRIVER]\r
+# FILE DRIVER = $(NAMED_GUID) {\r
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+# COMPRESS PI_STD {\r
+# GUIDED {\r
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+# UI STRING="$(MODULE_NAME)" Optional\r
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+# }\r
+# }\r
+# }\r
+#\r
+############################################################################\r
+\r
+[Rule.Common.SEC]\r
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {\r
+ TE TE Align = 128 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ }\r
+\r
+[Rule.Common.PEI_CORE]\r
+ FILE PEI_CORE = $(NAMED_GUID) {\r
+ TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING ="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.PEIM]\r
+ FILE PEIM = $(NAMED_GUID) {\r
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.PEIM.TIANOCOMPRESSED]\r
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {\r
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+ }\r
+\r
+[Rule.Common.DXE_CORE]\r
+ FILE DXE_CORE = $(NAMED_GUID) {\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.UEFI_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.DXE_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.DXE_RUNTIME_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.UEFI_APPLICATION]\r
+ FILE APPLICATION = $(NAMED_GUID) {\r
+ UI STRING ="$(MODULE_NAME)" Optional\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ }\r
+\r
+[Rule.Common.UEFI_DRIVER.BINARY]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional |.depex\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.UEFI_APPLICATION.BINARY]\r
+ FILE APPLICATION = $(NAMED_GUID) {\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
--- /dev/null
+//\r
+// Copyright (c) 2013, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+\r
+// Register definitions used by GCC for GICv3 access.\r
+// These are defined by ARMCC, so keep them in the GCC specific code for now.\r
+#define ICC_SRE_EL2 S3_4_C12_C9_5\r
+#define ICC_SRE_EL3 S3_6_C12_C12_5\r
+#define ICC_CTLR_EL1 S3_0_C12_C12_4\r
+#define ICC_CTLR_EL3 S3_6_C12_C12_4\r
+#define ICC_PMR_EL1 S3_0_C4_C6_0\r
+\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_EXPORT(InitializeGicV3)\r
+\r
+/* Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3 yet */\r
+ASM_PFX(InitializeGicV3):\r
+ // We have a GICv3. UEFI still uses the GICv2 mode. We must do enough setup\r
+ // to allow Linux to use GICv3 if it chooses.\r
+\r
+ // In order to setup NS side we need to enable it first.\r
+ mrs x0, scr_el3\r
+ orr x0, x0, #1\r
+ msr scr_el3, x0\r
+\r
+ // Enable SRE at EL3 and ICC_SRE_EL2 access\r
+ mov x0, #((1 << 3) | (1 << 0)) // Enable | SRE\r
+ mrs x1, ICC_SRE_EL3\r
+ orr x1, x1, x0\r
+ msr ICC_SRE_EL3, x1\r
+ isb\r
+\r
+ // Enable SRE at EL2 and ICC_SRE_EL1 access..\r
+ mrs x1, ICC_SRE_EL2\r
+ orr x1, x1, x0\r
+ msr ICC_SRE_EL2, x1\r
+ isb\r
+\r
+ // Configure CPU interface\r
+ msr ICC_CTLR_EL3, xzr\r
+ isb\r
+ msr ICC_CTLR_EL1, xzr\r
+ isb\r
+\r
+ // The MemoryMap view and Register view may not be consistent, So Set PMR again.\r
+ mov w1, #1 << 7 // allow NS access to GICC_PMR\r
+ msr ICC_PMR_EL1, x1\r
+ isb\r
+\r
+ // Remove the SCR.NS bit\r
+ mrs x0, scr_el3\r
+ bic x0, x0, #1\r
+ msr scr_el3, x0\r
+ ret\r
--- /dev/null
+//\r
+// Copyright (c) 2013, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_EXPORT(InitializeGicV3)\r
+\r
+/* Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3 yet */\r
+ASM_PFX(InitializeGicV3):\r
+ // GICv3 Initialization not Supported yet\r
+ bx lr\r
--- /dev/null
+//\r
+// Copyright (c) 2013, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+\r
+ EXPORT InitializeGicV3\r
+\r
+ PRESERVE8\r
+ AREA GicV3, CODE, READONLY\r
+\r
+/* Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3 yet */\r
+InitializeGicV3 FUNCTION\r
+ // GICv3 Initialization not Supported yet\r
+ bx lr\r
+ ENDFUNC\r
+\r
+ END\r
#/* @file\r
-# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http://opensource.org/licenses/bsd-license.php \r
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
#*/\r
\r
[Sources.ARM]\r
Arm/RTSMBoot.asm | RVCT\r
Arm/RTSMBoot.S | GCC\r
+ Arm/GicV3.asm | RVCT\r
+ Arm/GicV3.S | GCC\r
\r
[Sources.AARCH64]\r
AArch64/RTSMBoot.S | GCC\r
+ AArch64/GicV3.S | GCC\r
\r
[FixedPcd]\r
gArmTokenSpaceGuid.PcdFvBaseAddress\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
/** @file\r
*\r
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-* \r
-* This program and the accompanying materials \r
-* are licensed and made available under the terms and conditions of the BSD License \r
-* which accompanies this distribution. The full text of the license may be found at \r
-* http://opensource.org/licenses/bsd-license.php \r
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#include <Library/IoLib.h>\r
+#include <Library/ArmGicLib.h>\r
#include <Library/ArmPlatformLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
\r
#include <ArmPlatform.h>\r
\r
+// Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3 yet\r
+VOID\r
+InitializeGicV3 (\r
+ VOID\r
+ );\r
+\r
/**\r
Initialize the Secure peripherals and memory regions\r
\r
IN UINTN MpId\r
)\r
{\r
+ UINT32 Identification;\r
+\r
// If it is not the primary core then there is nothing to do\r
if (!ArmPlatformIsPrimaryCore (MpId)) {\r
return RETURN_SUCCESS;\r
// Configure SP810 to use 1MHz clock and disable\r
MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);\r
\r
+ // Read the GIC Identification Register\r
+ Identification = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIDR);\r
+\r
+ // Check if we are GICv3\r
+ if (ARM_GIC_ICCIDR_GET_ARCH_VERSION(Identification) >= 0x3) {\r
+ InitializeGicV3 ();\r
+ }\r
+\r
return RETURN_SUCCESS;\r
}\r
\r
projects / mirror_edk2.git / commitdiff