ArmPlatformPkg/ArmVExpressPkg: Create ArmVExpressPkg/Include/VExpressMotherBoard.h

This file contains the ARM Versatile Express motherboard definitions.
It allows to avoid duplication between different platforms based on ARM VExpress
motherboard.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11749 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc
index 2aeeaf198b070de15121d91f27c86f31e4e2dc9d..75362e19dab03593a2c7a2de60d82b60ed58d5d1 100644 (file)
--- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc
+++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc
@@ -230,12 +230,14 @@
   NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
 
 [BuildOptions]
-  RVCT:*_*_ARM_ARCHCC_FLAGS  == --cpu Cortex-A9 --thumb -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
-  RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu Cortex-A9 -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
-  RVCT:RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
-
-  ARMGCC:*_*_ARM_ARCHCC_FLAGS  == -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
-  ARMGCC:RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
+  RVCT:*_*_ARM_ARCHCC_FLAGS  == --cpu Cortex-A9 --thumb
+  RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu Cortex-A9
+  RVCT:RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG
+  RVCT:*_*_ARM_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
+
+  ARMGCC:*_*_ARM_ARCHCC_FLAGS  == 
+  ARMGCC:RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG
+  ARMGCC:*_*_ARM_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
   
 
 ################################################################################

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4/ArmPlatform.h b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4/ArmPlatform.h
index fa6e8d8bd0fd488bd2cbb998403df7a042336f4d..3dc622ecc38d70e5f74350e6df0b4a9ede76c941 100644 (file)
--- a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4/ArmPlatform.h
+++ b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4/ArmPlatform.h
@@ -2,31 +2,34 @@
 *  Header defining Versatile Express constants (Base addresses, sizes, flags)\r
 *\r
 *  Copyright (c) 2011, ARM Limited. All rights reserved.\r
-*  \r
-*  This program and the accompanying materials                          \r
-*  are licensed and made available under the terms and conditions of the BSD License         \r
-*  which accompanies this distribution.  The full text of the license may be found at        \r
-*  http://opensource.org/licenses/bsd-license.php                                            \r
 *\r
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+*  This program and the accompanying materials\r
+*  are licensed and made available under the terms and conditions of the BSD License\r
+*  which accompanies this distribution.  The full text of the license may be found at\r
+*  http://opensource.org/licenses/bsd-license.php\r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
 *\r
 **/\r
 \r
 #ifndef __ARM_VEXPRESS_H__\r
 #define __ARM_VEXPRESS_H__\r
 \r
-/*******************************************\r
+#include <Base.h>\r
+#include <VExpressMotherBoard.h>\r
+\r
+/***********************************************************************************\r
 // Platform Memory Map\r
-*******************************************/\r
+************************************************************************************/\r
 \r
 // Can be NOR0, NOR1, DRAM\r
 #define ARM_VE_REMAP_BASE                       0x00000000\r
-#define ARM_VE_REMAP_SZ                         0x04000000\r
+#define ARM_VE_REMAP_SZ                         SIZE_64MB\r
 \r
 // Motherboard Peripheral and On-chip peripheral\r
 #define ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE       0x10000000\r
-#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ         0x10000000 /* 256 MB */\r
+#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ         SIZE_256MB\r
 #define ARM_VE_BOARD_PERIPH_BASE                0x10000000\r
 #define ARM_VE_CHIP_PERIPH_BASE                 0x10020000\r
 \r
@@ -36,17 +39,17 @@
 \r
 // NOR Flash 1\r
 #define ARM_VE_SMB_NOR0_BASE                    0x40000000\r
-#define ARM_VE_SMB_NOR0_SZ                      0x04000000 /* 64 MB */\r
+#define ARM_VE_SMB_NOR0_SZ                      SIZE_64MB\r
 // NOR Flash 2\r
 #define ARM_VE_SMB_NOR1_BASE                    0x44000000\r
-#define ARM_VE_SMB_NOR1_SZ                      0x04000000 /* 64 MB */\r
+#define ARM_VE_SMB_NOR1_SZ                      SIZE_64MB\r
 // SRAM\r
 #define ARM_VE_SMB_SRAM_BASE                    0x48000000\r
-#define ARM_VE_SMB_SRAM_SZ                      0x02000000 /* 32 MB */\r
+#define ARM_VE_SMB_SRAM_SZ                      SIZE_32MB\r
 // USB, Ethernet, VRAM\r
 #define ARM_VE_SMB_PERIPH_BASE                  0x4C000000\r
-#define ARM_VE_SMB_PERIPH_VRAM                  0x4C000000\r
-#define ARM_VE_SMB_PERIPH_SZ                    0x04000000 /* 32 MB */\r
+#define PL111_CLCD_VRAM_MOTHERBOARD_BASE        ARM_VE_SMB_PERIPH_BASE\r
+#define ARM_VE_SMB_PERIPH_SZ                    SIZE_64MB\r
 \r
 // DRAM\r
 #define ARM_VE_DRAM_BASE                        0x60000000\r
@@ -54,49 +57,48 @@
 \r
 // External AXI between daughterboards (Logic Tile)\r
 #define ARM_VE_EXT_AXI_BASE                     0xE0000000\r
-#define ARM_VE_EXT_AXI_SZ                       0x20000000\r
-\r
-/*******************************************\r
-// Motherboard peripherals\r
-*******************************************/\r
-\r
-// Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)\r
-#define ARM_VE_SYS_FLAGS_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x00030)\r
-#define ARM_VE_SYS_FLAGS_SET_REG                (ARM_VE_BOARD_PERIPH_BASE + 0x00030)\r
-#define ARM_VE_SYS_FLAGS_CLR_REG                (ARM_VE_BOARD_PERIPH_BASE + 0x00034)\r
-#define ARM_VE_SYS_FLAGS_NV_REG                 (ARM_VE_BOARD_PERIPH_BASE + 0x00038)\r
-#define ARM_VE_SYS_FLAGS_NV_SET_REG             (ARM_VE_BOARD_PERIPH_BASE + 0x00038)\r
-#define ARM_VE_SYS_FLAGS_NV_CLR_REG             (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)\r
-#define ARM_VE_SYS_PROCID0_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x00084)\r
-#define ARM_VE_SYS_PROCID1_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x00088)\r
-#define ARM_VE_SYS_CFGDATA_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)\r
-#define ARM_VE_SYS_CFGCTRL_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x000A4)\r
-#define ARM_VE_SYS_CFGSTAT_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)\r
-\r
-// SP810 Controller\r
-#define SP810_CTRL_BASE                      (ARM_VE_BOARD_PERIPH_BASE + 0x01000)\r
-\r
-// Uart0\r
-#define PL011_CONSOLE_UART_BASE                (ARM_VE_BOARD_PERIPH_BASE + 0x09000)\r
-#define PL011_CONSOLE_UART_SPEED               38400\r
-\r
-// SP804 Timer Bases\r
-#define SP804_TIMER0_BASE                    (ARM_VE_BOARD_PERIPH_BASE + 0x11000)\r
-#define SP804_TIMER1_BASE                    (ARM_VE_BOARD_PERIPH_BASE + 0x11020)\r
-#define SP804_TIMER2_BASE                    (ARM_VE_BOARD_PERIPH_BASE + 0x12000)\r
-#define SP804_TIMER3_BASE                    (ARM_VE_BOARD_PERIPH_BASE + 0x12020)\r
-\r
-// Dynamic Memory Controller Base\r
-#define ARM_VE_DMC_BASE                         0x100E0000\r
-\r
-// Static Memory Controller Base\r
-#define ARM_VE_SMC_CTRL_BASE                    0x100E1000\r
+#define ARM_VE_EXT_AXI_SZ                       0x20000000  /* 512 MB */\r
+\r
+\r
+/***********************************************************************************\r
+   Core Tile memory-mapped Peripherals\r
+************************************************************************************/\r
+\r
+// PL111 Colour LCD Controller - core tile\r
+#define PL111_CLCD_CORE_TILE_BASE               (ARM_VE_BOARD_PERIPH_BASE + 0x20000)\r
+\r
+// PL341 Dynamic Memory Controller Base\r
+#define ARM_VE_DMC_BASE                         (ARM_VE_BOARD_PERIPH_BASE + 0xE0000)\r
+\r
+// PL354 Static Memory Controller Base\r
+#define ARM_VE_SMC_CTRL_BASE                    (ARM_VE_BOARD_PERIPH_BASE + 0xE1000)\r
 \r
 // System Configuration Controller register Base addresses\r
-//#define ARM_VE_SYS_CFG_CTRL_BASE                0x100E2000\r
-#define ARM_VE_SYS_CFGRW0_REG                   0x100E2000\r
-#define ARM_VE_SYS_CFGRW1_REG                   0x100E2004\r
-#define ARM_VE_SYS_CFGRW2_REG                   0x100E2008\r
+//#define ARM_VE_SYS_CFG_CTRL_BASE              (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)\r
+#define ARM_VE_SYS_CFGRW0_REG                   (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)\r
+#define ARM_VE_SYS_CFGRW1_REG                   (ARM_VE_BOARD_PERIPH_BASE + 0xE2004)\r
+#define ARM_VE_SYS_CFGRW2_REG                   (ARM_VE_BOARD_PERIPH_BASE + 0xE2008)\r
+\r
+#define ARM_PLATFORM_SCC_BASE                   ARM_VE_SYS_CFGRW0_REG\r
+\r
+// SP805 Watchdog on Cortex A9 core tile\r
+#define SP805_WDOG_CORE_TILE_BASE               (ARM_VE_BOARD_PERIPH_BASE + 0xE5000)\r
+\r
+// BP147 TZPC Base Address\r
+#define ARM_VE_TZPC_BASE                        (ARM_VE_BOARD_PERIPH_BASE + 0xE6000)\r
+\r
+// PL301 Fast AXI Base Address\r
+#define ARM_VE_FAXI_BASE                        (ARM_VE_BOARD_PERIPH_BASE + 0xE9000)\r
+\r
+// TZASC Trust Zone Address Space Controller Base Address\r
+#define ARM_VE_TZASC_BASE                       (ARM_VE_BOARD_PERIPH_BASE + 0xEC000)\r
+\r
+// PL310 L2x0 Cache Controller Base Address\r
+//#define ARM_VE_L2x0_CTLR_BASE                 0x1E00A000\r
+\r
+/***********************************************************************************\r
+   Peripherals' misc settings\r
+************************************************************************************/\r
 \r
 #define ARM_VE_CFGRW1_TZASC_EN_BIT_MASK         0x2000\r
 #define ARM_VE_CFGRW1_REMAP_NOR0                0\r
@@ -104,14 +106,7 @@
 #define ARM_VE_CFGRW1_REMAP_EXT_AXI             (1 << 29)\r
 #define ARM_VE_CFGRW1_REMAP_DRAM                (1 << 30)\r
 \r
-// TZPC Base Address\r
-#define ARM_VE_TZPC_BASE                        0x100E6000\r
-\r
-// PL301 Fast AXI Base Address\r
-#define ARM_VE_FAXI_BASE                        0x100E9000\r
-\r
-// TZASC Defintions\r
-#define ARM_VE_TZASC_BASE                       0x100EC000\r
+// TZASC - Other settings\r
 #define ARM_VE_DECPROT_BIT_TZPC                 (1 << 6)\r
 #define ARM_VE_DECPROT_BIT_DMC_TZASC            (1 << 11)\r
 #define ARM_VE_DECPROT_BIT_NMC_TZASC            (1 << 12)\r
@@ -121,22 +116,19 @@
 #define ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK       (1 << 4)\r
 #define ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK       (1 << 5)\r
 \r
-// L2x0 Cache Controller Base Address\r
-//#define ARM_VE_L2x0_CTLR_BASE                   0x1E00A000\r
 \r
-\r
-/*******************************************\r
+/***********************************************************************************\r
 // Interrupt Map\r
-*******************************************/\r
+************************************************************************************/\r
 \r
 // Timer Interrupts\r
-#define TIMER01_INTERRUPT_NUM                34\r
-#define TIMER23_INTERRUPT_NUM                35\r
+#define TIMER01_INTERRUPT_NUM                   34\r
+#define TIMER23_INTERRUPT_NUM                   35\r
 \r
 \r
-/*******************************************\r
+/***********************************************************************************\r
 // EFI Memory Map in Permanent Memory (DRAM)\r
-*******************************************/\r
+************************************************************************************/\r
 \r
 // This region is allocated at the bottom of the DRAM. It will be used\r
 // for fixed address allocations such as Vector Table\r
@@ -144,7 +136,6 @@
 \r
 // This region is the memory declared to PEI as permanent memory for PEI\r
 // and DXE. EFI stacks and heaps will be declared in this region.\r
-#define ARM_VE_EFI_MEMORY_REGION_SZ             0x1000000\r
-\r
+#define ARM_VE_EFI_MEMORY_REGION_SZ             SIZE_256MB\r
 \r
-#endif \r
+#endif\r

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Include/VExpressMotherBoard.h b/ArmPlatformPkg/ArmVExpressPkg/Include/VExpressMotherBoard.h
new file mode 100644 (file)
index 0000000..3fcd74f
--- /dev/null
+++ b/ArmPlatformPkg/ArmVExpressPkg/Include/VExpressMotherBoard.h
@@ -0,0 +1,76 @@
+/** @file\r
+*  Header defining Versatile Express constants (Base addresses, sizes, flags)\r
+*\r
+*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*\r
+*  This program and the accompanying materials\r
+*  are licensed and made available under the terms and conditions of the BSD License\r
+*  which accompanies this distribution.  The full text of the license may be found at\r
+*  http://opensource.org/licenses/bsd-license.php\r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#ifndef __VEXPRESSMOTHERBOARD_H_\r
+#define __VEXPRESSMOTHERBOARD_H_\r
+\r
+#include <ArmPlatform.h>\r
+\r
+/***********************************************************************************\r
+// Motherboard memory-mapped peripherals\r
+************************************************************************************/\r
+\r
+// Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)\r
+#define ARM_VE_SYS_LED_REG                        (ARM_VE_BOARD_PERIPH_BASE + 0x00008)\r
+#define ARM_VE_SYS_FLAGS_REG                      (ARM_VE_BOARD_PERIPH_BASE + 0x00030)\r
+#define ARM_VE_SYS_FLAGS_SET_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x00030)\r
+#define ARM_VE_SYS_FLAGS_CLR_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x00034)\r
+#define ARM_VE_SYS_FLAGS_NV_REG                   (ARM_VE_BOARD_PERIPH_BASE + 0x00038)\r
+#define ARM_VE_SYS_FLAGS_NV_SET_REG               (ARM_VE_BOARD_PERIPH_BASE + 0x00038)\r
+#define ARM_VE_SYS_FLAGS_NV_CLR_REG               (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)\r
+#define ARM_VE_SYS_FLASH                          (ARM_VE_BOARD_PERIPH_BASE + 0x0004C)\r
+#define ARM_VE_SYS_PROCID0_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x00084)\r
+#define ARM_VE_SYS_PROCID1_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x00088)\r
+#define ARM_VE_SYS_CFGDATA_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)\r
+#define ARM_VE_SYS_CFGCTRL_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x000A4)\r
+#define ARM_VE_SYS_CFGSTAT_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)\r
+\r
+// SP810 Controller\r
+#define SP810_CTRL_BASE                           (ARM_VE_BOARD_PERIPH_BASE + 0x01000)\r
+\r
+// Uart0\r
+#define PL011_CONSOLE_UART_BASE                   (ARM_VE_BOARD_PERIPH_BASE + 0x09000)\r
+\r
+// SP805 Watchdog on motherboard\r
+#define SP805_WDOG_MOTHERBOARD_BASE               (ARM_VE_BOARD_PERIPH_BASE + 0x0F000)\r
+\r
+// SP804 Timer Bases\r
+#define SP804_TIMER0_BASE                         (ARM_VE_BOARD_PERIPH_BASE + 0x11000)\r
+#define SP804_TIMER1_BASE                         (ARM_VE_BOARD_PERIPH_BASE + 0x11020)\r
+#define SP804_TIMER2_BASE                         (ARM_VE_BOARD_PERIPH_BASE + 0x12000)\r
+#define SP804_TIMER3_BASE                         (ARM_VE_BOARD_PERIPH_BASE + 0x12020)\r
+\r
+// PL031 Real Time Clock\r
+#define PL031_RTC_BASE                            (ARM_VE_BOARD_PERIPH_BASE + 0x17000)\r
+\r
+// PL111 Colour LCD Controller - motherboard\r
+#define PL111_CLCD_MOTHERBOARD_BASE               (ARM_VE_BOARD_PERIPH_BASE + 0x1F000)\r
+#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID  1\r
+\r
+// VRAM offset for the PL111 Colour LCD Controller on the motherboard\r
+#define VRAM_MOTHERBOARD_BASE                     (ARM_VE_SMB_PERIPH_BASE   + 0x00000)\r
+\r
+#define SYS_PROC_ID_UNSUPPORTED                   0xFF\r
+#define SYS_PROC_ID_CORTEX_A9                     0x0C\r
+\r
+//\r
+// Sites where the peripheral is fitted\r
+//\r
+#define ARM_VE_UNSUPPORTED                        ~0\r
+#define ARM_VE_MOTHERBOARD_SITE                   0\r
+#define ARM_VE_DAUGHTERBOARD_1_SITE               1\r
+#define ARM_VE_DAUGHTERBOARD_2_SITE               2\r
+\r
+#endif /* VEXPRESSMOTHERBOARD_H_ */\r

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.S
index f18d0569fd6a179d1029ce83a6e4b518dd6c3401..fe63904d62c00837802a43900ab1d0de3ff125cf 100644 (file)
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.S
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.S
@@ -67,7 +67,7 @@ ASM_PFX(ArmPlatformInitializeBootMemory):
   mov   r5, lr\r
   // Initialize PL354 SMC\r
   LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)\r
-  LoadConstantToReg (ARM_VE_SMB_PERIPH_VRAM, r2)\r
+  LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2)\r
   blx   ASM_PFX(InitializeSMC)\r
   bx   r5\r
 \r

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.asm b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.asm
index 673052f14e2958d2fc9c27b510cfbc9a4409df26..7d59f5017d72f7dab6937fd35e434d15ebcacc81 100644 (file)
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.asm
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.asm
@@ -61,7 +61,7 @@ ArmPlatformInitializeBootMemory
   mov   r5, lr\r
   // Initialize PL354 SMC\r
   LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)\r
-  LoadConstantToReg (ARM_VE_SMB_PERIPH_VRAM, r2)\r
+  LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2)\r
   blx   InitializeSMC\r
   bx   r5\r
   \r