Correctly character in comments of BaseLib BitField.

Signed-off-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14497 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdePkg/Library/BaseLib/BitField.c b/MdePkg/Library/BaseLib/BitField.c
index 167ee5b692c31784f8e154db94d2767e0846fc1d..eb9e276acc7132ce9043314500b7e132cd0f972f 100644 (file)
--- a/MdePkg/Library/BaseLib/BitField.c
+++ b/MdePkg/Library/BaseLib/BitField.c
@@ -71,8 +71,8 @@ InternalBaseLibBitFieldOrUint (
   //\r
   // Higher bits in OrData those are not used must be zero. \r
   //\r
-  // EndBit \96 StartBit + 1 might be 32 while the result right shifting 32 on a 32bit integer is undefined,\r
-  // So the logic is updated to right shift (EndBit \96 StartBit) bits and compare the last bit directly.\r
+  // EndBit - StartBit + 1 might be 32 while the result right shifting 32 on a 32bit integer is undefined,\r
+  // So the logic is updated to right shift (EndBit - StartBit) bits and compare the last bit directly.\r
   //\r
   ASSERT ((OrData >> (EndBit - StartBit)) == ((OrData >> (EndBit - StartBit)) & 1));\r
   \r
@@ -113,8 +113,8 @@ InternalBaseLibBitFieldAndUint (
   //\r
   // Higher bits in AndData those are not used must be zero. \r
   //\r
-  // EndBit \96 StartBit + 1 might be 32 while the result right shifting 32 on a 32bit integer is undefined,\r
-  // So the logic is updated to right shift (EndBit \96 StartBit) bits and compare the last bit directly.\r
+  // EndBit - StartBit + 1 might be 32 while the result right shifting 32 on a 32bit integer is undefined,\r
+  // So the logic is updated to right shift (EndBit - StartBit) bits and compare the last bit directly.\r
   //\r
   ASSERT ((AndData >> (EndBit - StartBit)) == ((AndData >> (EndBit - StartBit)) & 1));\r
 \r
@@ -811,8 +811,8 @@ BitFieldOr64 (
   //\r
   // Higher bits in OrData those are not used must be zero. \r
   //\r
-  // EndBit \96 StartBit + 1 might be 64 while the result right shifting 64 on RShiftU64() API is invalid,\r
-  // So the logic is updated to right shift (EndBit \96 StartBit) bits and compare the last bit directly.\r
+  // EndBit - StartBit + 1 might be 64 while the result right shifting 64 on RShiftU64() API is invalid,\r
+  // So the logic is updated to right shift (EndBit - StartBit) bits and compare the last bit directly.\r
   //\r
   ASSERT (RShiftU64 (OrData, EndBit - StartBit) == (RShiftU64 (OrData, EndBit - StartBit) & 1));\r
 \r
@@ -863,8 +863,8 @@ BitFieldAnd64 (
   //\r
   // Higher bits in AndData those are not used must be zero. \r
   //\r
-  // EndBit \96 StartBit + 1 might be 64 while the right shifting 64 on RShiftU64() API is invalid,\r
-  // So the logic is updated to right shift (EndBit \96 StartBit) bits and compare the last bit directly.\r
+  // EndBit - StartBit + 1 might be 64 while the right shifting 64 on RShiftU64() API is invalid,\r
+  // So the logic is updated to right shift (EndBit - StartBit) bits and compare the last bit directly.\r
   //\r
   ASSERT (RShiftU64 (AndData, EndBit - StartBit) == (RShiftU64 (AndData, EndBit - StartBit) & 1));\r
 \r