/** @file\r
Initialize Debug Agent in DXE by invoking Debug Agent Library.\r
\r
-Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include <Library/DebugAgentLib.h>\r
#include <Library/UefiLib.h>\r
\r
-EFI_EVENT mExitBootServiceEvent; \r
+EFI_EVENT mExitBootServiceEvent;\r
\r
/**\r
One notified function to disable Debug Timer interrupt when gBS->ExitBootServices() called.\r
#\r
# This DXE driver will invoke Debug Agent Library to initialize the debug agent.\r
#\r
-# Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
MODULE_UNI_FILE = DebugAgentDxe.uni\r
FILE_GUID = 9727502C-034E-472b-8E1B-67BB28C6CFDB\r
MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0 \r
+ VERSION_STRING = 1.0\r
ENTRY_POINT = DebugAgentDxeInitialize\r
UNLOAD_IMAGE = DebugAgentDxeUnload\r
\r
\r
[Sources]\r
DebugAgentDxe.c\r
- \r
+\r
[Packages]\r
MdePkg/MdePkg.dec\r
MdeModulePkg/MdeModulePkg.dec\r
[LibraryClasses]\r
UefiDriverEntryPoint\r
UefiBootServicesTableLib\r
- DebugAgentLib \r
+ DebugAgentLib\r
\r
[Guids]\r
gEfiEventExitBootServicesGuid ## SOMETIMES_CONSUMES ## Event\r
//\r
// This DXE driver will invoke Debug Agent Library to initialize the debug agent.\r
//\r
-// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
+// Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
// which accompanies this distribution. The full text of the license may be found at\r
// http://opensource.org/licenses/bsd-license.php\r
-// \r
+//\r
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
//\r
// /** @file\r
// DebugAgentDxe Localized Strings and Content\r
//\r
-// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
+// Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
//\r
// **/\r
\r
-#string STR_PROPERTIES_MODULE_NAME \r
-#language en-US \r
+#string STR_PROPERTIES_MODULE_NAME\r
+#language en-US\r
"Debug Agent DXE Driver"\r
\r
\r
/** @file\r
Initialize Debug Agent in PEI by invoking Debug Agent Library.\r
\r
-Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
This function is the Entry point of the CPU I/O PEIM which installs CpuIoPpi.\r
\r
@param[in] FileHandle Pointer to image file handle.\r
- @param[in] PeiServices Pointer to PEI Services Table \r
+ @param[in] PeiServices Pointer to PEI Services Table\r
\r
@retval EFI_SUCCESS Debug Agent successfully initialized.\r
@retval other Some error occurs when initialzed Debug Agent.\r
## @file\r
# Initialized Debug Agent in PEI phase.\r
#\r
-# This PEIM will invoke Debug Agent Library to initialize the debug agent in \r
+# This PEIM will invoke Debug Agent Library to initialize the debug agent in\r
# whole PEI phase.\r
#\r
-# Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
MODULE_UNI_FILE = DebugAgentPei.uni\r
FILE_GUID = D9D114EF-F40B-4d48-AAA0-A3DC99C9F5BD\r
MODULE_TYPE = PEIM\r
- VERSION_STRING = 1.0 \r
+ VERSION_STRING = 1.0\r
ENTRY_POINT = DebugAgentPeiInitialize\r
\r
#\r
\r
[Sources]\r
DebugAgentPei.c\r
- \r
+\r
[Packages]\r
MdePkg/MdePkg.dec\r
MdeModulePkg/MdeModulePkg.dec\r
// This PEIM will invoke Debug Agent Library to initialize the debug agent in\r
// whole PEI phase.\r
//\r
-// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
+// Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
// which accompanies this distribution. The full text of the license may be found at\r
// http://opensource.org/licenses/bsd-license.php\r
-// \r
+//\r
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
//\r
// /** @file\r
// DebugAgentPei Localized Strings and Content\r
//\r
-// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
+// Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
//\r
// **/\r
\r
-#string STR_PROPERTIES_MODULE_NAME \r
-#language en-US \r
+#string STR_PROPERTIES_MODULE_NAME\r
+#language en-US\r
"Debug Agent PEI Module"\r
\r
\r
UINT32 TimerRound;\r
UINT32 TimerFrequency;\r
UINT32 TimerCycle;\r
- \r
+\r
Begin = 0;\r
- TimeoutTicker = 0; \r
+ TimeoutTicker = 0;\r
TimerRound = 0;\r
TimerFrequency = GetMailboxPointer()->DebugTimerFrequency;\r
TimerCycle = GetApicTimerInitCount ();\r
while (Index < NumberOfBytes) {\r
if (DebugPortPollBuffer (Handle)) {\r
DebugPortReadBuffer (Handle, Buffer + Index, 1, 0);\r
- Index ++; \r
+ Index ++;\r
continue;\r
}\r
if (Timeout != 0) {\r
if (IS_REQUEST (DebugHeader)) {\r
if (DebugHeader->SequenceNo == (UINT8) (Mailbox->HostSequenceNo + 1)) {\r
//\r
- // Only updagte HostSequenceNo for new command packet \r
+ // Only updagte HostSequenceNo for new command packet\r
//\r
UpdateMailboxContent (Mailbox, DEBUG_MAILBOX_HOST_SEQUENCE_NO_INDEX, DebugHeader->SequenceNo);\r
return EFI_SUCCESS;\r
if (Send) {\r
DebugPortWriteBuffer (Handle, &LastChar, 1);\r
}\r
- \r
+\r
} else if (LastCharCount >= 2) {\r
CompressedIndex += 3;\r
LastCharCount -= 2;\r
/** @file\r
Command header of for Debug Agent library instance.\r
\r
- Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
//\r
UINT32 BreakOnNextSmi : 1; // 1: Break on next SMI\r
UINT32 PrintErrorLevel : 4; // Bitmask of print error level for debug message\r
- UINT32 BreakOnBootScript : 1; // 1: Break before executing boot script \r
+ UINT32 BreakOnBootScript : 1; // 1: Break before executing boot script\r
UINT32 Reserved2 : 26;\r
} Bits;\r
UINT64 Uint64;\r
\r
@param[in] ErrorLevel The error level of the debug message.\r
@param[in] Format Format string for the debug message to print.\r
- @param[in] ... Variable argument list whose contents are accessed \r
+ @param[in] ... Variable argument list whose contents are accessed\r
based on the format string specified by Format.\r
\r
**/\r
\r
/**\r
Find and report module image info to HOST.\r
- \r
+\r
@param[in] AlignSize Image aligned size.\r
- \r
+\r
**/\r
-VOID \r
+VOID\r
FindAndReportModuleImageInfo (\r
- IN UINTN AlignSize \r
+ IN UINTN AlignSize\r
);\r
\r
/**\r
@retval FALSE IDT entries were not setup by Debug Agent.\r
\r
**/\r
-BOOLEAN \r
+BOOLEAN\r
IsDebugAgentInitialzed (\r
VOID\r
);\r
@param[in] Mailbox Debug Agent Mailbox pointer.\r
\r
**/\r
-VOID \r
+VOID\r
VerifyMailboxChecksum (\r
IN DEBUG_AGENT_MAILBOX *Mailbox\r
);\r
@param[in] FlagValue Debug flag value.\r
\r
**/\r
-VOID \r
+VOID\r
SetDebugFlag (\r
IN UINT64 FlagMask,\r
- IN UINT32 FlagValue \r
+ IN UINT32 FlagValue\r
);\r
\r
/**\r
Get debug flag in mailbox.\r
\r
@param[in] FlagMask Debug flag mask value.\r
- \r
+\r
@return Debug flag value.\r
\r
**/\r
@param[in] Mailbox Debug Agent Mailbox pointer.\r
@param[in] Index Mailbox content index.\r
@param[in] Value Value to be set into mail box.\r
- \r
+\r
**/\r
VOID\r
-UpdateMailboxContent ( \r
+UpdateMailboxContent (\r
IN DEBUG_AGENT_MAILBOX *Mailbox,\r
IN UINTN Index,\r
IN UINT64 Value\r
Retrieve exception handler from IDT table by ExceptionNum.\r
\r
@param[in] ExceptionNum Exception number\r
- \r
+\r
@return Exception handler\r
\r
**/\r
Set exception handler in IDT table by ExceptionNum.\r
\r
@param[in] ExceptionNum Exception number\r
- @param[in] ExceptionHandler Exception Handler to be set \r
+ @param[in] ExceptionHandler Exception Handler to be set\r
\r
**/\r
VOID\r
/**\r
Prints a debug message to the debug output device if the specified error level is enabled.\r
\r
- If any bit in ErrorLevel is also set in DebugPrintErrorLevelLib function \r
- GetDebugPrintErrorLevel (), then print the message specified by Format and the \r
+ If any bit in ErrorLevel is also set in DebugPrintErrorLevelLib function\r
+ GetDebugPrintErrorLevel (), then print the message specified by Format and the\r
associated variable argument list to the debug output device.\r
\r
If Format is NULL, then ASSERT().\r
\r
@param[in] ErrorLevel The error level of the debug message.\r
@param[in] IsSend Flag of debug message to declare that the data is being sent or being received.\r
- @param[in] Data Variable argument list whose contents are accessed \r
+ @param[in] Data Variable argument list whose contents are accessed\r
@param[in] Length based on the format string specified by Format.\r
\r
**/\r
IN UINT8 ErrorLevel,\r
IN BOOLEAN IsSend,\r
IN UINT8 *Data,\r
- IN UINT8 Length \r
+ IN UINT8 Length\r
);\r
\r
/**\r
)\r
{\r
MSR_IA32_APIC_BASE_REGISTER MsrApicBase;\r
- \r
+\r
//\r
// If there are less than 2 CPUs detected, then the currently executing CPU\r
- // must be the BSP. This avoids an access to an MSR that may not be supported \r
+ // must be the BSP. This avoids an access to an MSR that may not be supported\r
// on single core CPUs.\r
//\r
if (mDebugCpuData.CpuCount < 2) {\r
FindNextPendingBreakCpu (\r
VOID\r
);\r
- \r
+\r
/**\r
Check if all processors are in running status.\r
\r
/**\r
Check if the current processor is the first breaking processor.\r
\r
- If yes, halt other processors. \r
- \r
+ If yes, halt other processors.\r
+\r
@param[in] ProcessorIndex Processor index value.\r
- \r
+\r
@return TRUE This processor is the first breaking processor.\r
@return FALSE This processor is not the first breaking processor.\r
- \r
+\r
**/\r
BOOLEAN\r
IsFirstBreakProcessor (\r
IN UINT32 ProcessorIndex\r
);\r
- \r
+\r
#endif\r
\r
/** @file\r
Supporting functions for IA32 architecture.\r
\r
- Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
IdtEntry[DEBUG_TIMER_VECTOR].Bits.OffsetHigh = (UINT16)((UINTN)InterruptHandler >> 16);\r
IdtEntry[DEBUG_TIMER_VECTOR].Bits.Selector = CodeSegment;\r
IdtEntry[DEBUG_TIMER_VECTOR].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
- \r
+\r
//\r
- // If the CPU supports Debug Extensions(CPUID:01 EDX:BIT2), then \r
+ // If the CPU supports Debug Extensions(CPUID:01 EDX:BIT2), then\r
// Set DE flag in CR4 to enable IO breakpoint\r
//\r
AsmCpuid (1, NULL, NULL, NULL, &RegEdx);\r
Retrieve exception handler from IDT table by ExceptionNum.\r
\r
@param[in] ExceptionNum Exception number\r
- \r
+\r
@return Exception handler\r
\r
**/\r
\r
return (VOID *) (((UINTN)IdtEntry[ExceptionNum].Bits.OffsetLow) |\r
(((UINTN)IdtEntry[ExceptionNum].Bits.OffsetHigh) << 16));\r
-} \r
+}\r
\r
/**\r
Set exception handler in IDT table by ExceptionNum.\r
\r
@param[in] ExceptionNum Exception number\r
- @param[in] ExceptionHandler Exception Handler to be set \r
+ @param[in] ExceptionHandler Exception Handler to be set\r
\r
**/\r
VOID\r
#------------------------------------------------------------------------------\r
#\r
-# Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
## insure FXSAVE/FXRSTOR is enabled in CR4...\r
## ... while we're at it, make sure DE is also enabled...\r
mov $1, %eax\r
- pushl %ebx # temporarily save value of ebx on stack \r
- cpuid # use CPUID to determine if FXSAVE/FXRESTOR \r
+ pushl %ebx # temporarily save value of ebx on stack\r
+ cpuid # use CPUID to determine if FXSAVE/FXRESTOR\r
# and DE are supported\r
popl %ebx # retore value of ebx that was overwritten\r
- # by CPUID \r
+ # by CPUID\r
movl %cr4, %eax\r
pushl %eax # push cr4 firstly\r
testl $BIT24, %edx # Test for FXSAVE/FXRESTOR support\r
jz L1\r
orl $BIT9, %eax # Set CR4.OSFXSR\r
-L1: \r
+L1:\r
testl $BIT2, %edx # Test for Debugging Extensions support\r
jz L2\r
orl $BIT3, %eax # Set CR4.DE\r
-L2: \r
+L2:\r
movl %eax, %cr4\r
movl %cr3, %eax\r
pushl %eax\r
# edx still contains result from CPUID above\r
jz L3\r
.byte 0x0f, 0xae, 0x07 # fxsave [edi]\r
-L3: \r
+L3:\r
\r
## save the exception data\r
pushl 8(%esp)\r
\r
## Clear Direction Flag\r
cld\r
- \r
+\r
## Prepare parameter and call C function\r
pushl %esp\r
pushl %ebx\r
testl $BIT24, %edx # Test for FXSAVE/FXRESTOR support\r
jz L4\r
.byte 0x0f, 0xae, 0x0e # fxrstor [esi]\r
-L4: \r
+L4:\r
addl $512,%esp\r
\r
## UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
popl %ebp\r
addl $8,%esp # skip eax\r
iretl\r
- \r
+\r
/** @file\r
Supporting functions for X64 architecture.\r
\r
- Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
IdtEntry[DEBUG_TIMER_VECTOR].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
\r
//\r
- // If the CPU supports Debug Extensions(CPUID:01 EDX:BIT2), then \r
+ // If the CPU supports Debug Extensions(CPUID:01 EDX:BIT2), then\r
// Set DE flag in CR4 to enable IO breakpoint\r
//\r
AsmCpuid (1, NULL, NULL, NULL, &RegEdx);\r
Retrieve exception handler from IDT table by ExceptionNum.\r
\r
@param[in] ExceptionNum Exception number\r
- \r
+\r
@return Exception handler\r
\r
**/\r
return (VOID *) (IdtEntry[ExceptionNum].Bits.OffsetLow |\r
(((UINTN)IdtEntry[ExceptionNum].Bits.OffsetHigh) << 16) |\r
(((UINTN)IdtEntry[ExceptionNum].Bits.OffsetUpper) << 32));\r
-} \r
+}\r
\r
/**\r
Set exception handler in IDT table by ExceptionNum.\r
\r
@param[in] ExceptionNum Exception number\r
- @param[in] ExceptionHandler Exception Handler to be set \r
+ @param[in] ExceptionHandler Exception Handler to be set\r
\r
**/\r
VOID\r
/** @file\r
Debug Agent library implementition for Dxe Core and Dxr modules.\r
\r
- Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
/**\r
Worker function to set up Debug Agent environment.\r
\r
- This function will set up IDT table and initialize the IDT entries and \r
+ This function will set up IDT table and initialize the IDT entries and\r
initialize CPU LOCAL APIC timer.\r
It also tries to connect HOST if Debug Agent was not initialized before.\r
\r
/** @file\r
Header file for Dxe Core Debug Agent Library instance.\r
\r
- Copyright (c) 2010 - 2013, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#include "DebugAgent.h"\r
\r
/**\r
- Install EFI Serial IO protocol based on Debug Communication Library. \r
+ Install EFI Serial IO protocol based on Debug Communication Library.\r
\r
**/\r
VOID\r
InstallSerialIo (\r
VOID\r
);\r
- \r
+\r
#endif\r
/** @file\r
Install Serial IO Protocol that layers on top of a Debug Communication Library instance.\r
\r
- Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
SerialReset (\r
IN EFI_SERIAL_IO_PROTOCOL *This\r
);\r
- \r
+\r
/**\r
Set new attributes to a serial device.\r
\r
\r
/**\r
Detect whether specific FIFO is empty or not.\r
- \r
+\r
@param[in] Fifo A pointer to the Data Structure DEBUG_SERIAL_FIFO.\r
\r
@return whether specific FIFO is empty or not.\r
}\r
\r
/**\r
- Install EFI Serial IO protocol based on Debug Communication Library. \r
+ Install EFI Serial IO protocol based on Debug Communication Library.\r
\r
**/\r
VOID\r
//\r
// The Debug Communication Library CAN NOT change communications parameters (if it has)\r
// actually. Because it also has no any idea on what parameters are based on, we cannot\r
- // check the input parameters (like BaudRate, Parity, DataBits and StopBits). \r
+ // check the input parameters (like BaudRate, Parity, DataBits and StopBits).\r
//\r
- \r
+\r
//\r
// Update the Timeout value in the mode structure based on the request.\r
- // The Debug Communication Library can not support a timeout on writes, but the timeout on \r
+ // The Debug Communication Library can not support a timeout on writes, but the timeout on\r
// reads can be provided by this module.\r
//\r
if (Timeout == 0) {\r
} else {\r
mSerialIoMode.Timeout = Timeout;\r
}\r
- \r
+\r
//\r
// Update the ReceiveFifoDepth value in the mode structure based on the request.\r
- // This module assumes that the Debug Communication Library uses a FIFO depth of \r
- // SERIAL_PORT_DEFAULT_RECEIVE_FIFO_DEPTH. The Debug Communication Library may actually be \r
+ // This module assumes that the Debug Communication Library uses a FIFO depth of\r
+ // SERIAL_PORT_DEFAULT_RECEIVE_FIFO_DEPTH. The Debug Communication Library may actually be\r
// using a larger FIFO, but there is no way to tell.\r
//\r
if (ReceiveFifoDepth == 0 || ReceiveFifoDepth >= SERIAL_PORT_DEFAULT_RECEIVE_FIFO_DEPTH) {\r
// Raise TPL to prevent recursion from EFI timer interrupts\r
//\r
Tpl = gBS->RaiseTPL (TPL_NOTIFY);\r
- \r
+\r
//\r
// Save and disable Debug Timer interrupt to avoid it to access Debug Port\r
//\r
DebugTimerInterruptState = SaveAndSetDebugTimerInterrupt (FALSE);\r
Handle = GetDebugPortHandle ();\r
- \r
+\r
//\r
// Always assume the output buffer is empty and the Debug Communication Library can process\r
// more write requests.\r
//\r
*Control = mSerialIoMode.ControlMask | EFI_SERIAL_OUTPUT_BUFFER_EMPTY;\r
- \r
+\r
//\r
- // Check to see if the Terminal FIFO is empty and \r
+ // Check to see if the Terminal FIFO is empty and\r
// check to see if the input buffer in the Debug Communication Library is empty\r
//\r
if (!IsDebugTermianlFifoEmpty (&mSerialFifoForTerminal) || DebugPortPollBuffer (Handle)) {\r
\r
//\r
// Restore Debug Timer interrupt\r
- // \r
+ //\r
SaveAndSetDebugTimerInterrupt (DebugTimerInterruptState);\r
- \r
+\r
//\r
// Restore to original TPL\r
//\r
gBS->RestoreTPL (Tpl);\r
- \r
+\r
return EFI_SUCCESS;\r
}\r
\r
// Raise TPL to prevent recursion from EFI timer interrupts\r
//\r
Tpl = gBS->RaiseTPL (TPL_NOTIFY);\r
- \r
+\r
//\r
// Save and disable Debug Timer interrupt to avoid it to access Debug Port\r
//\r
DebugTimerInterruptState = SaveAndSetDebugTimerInterrupt (FALSE);\r
Handle = GetDebugPortHandle ();\r
- \r
+\r
if ((mSerialIoMode.ControlMask & EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE) != 0) {\r
if (*BufferSize == 0) {\r
return EFI_SUCCESS;\r
\r
//\r
// Restore Debug Timer interrupt\r
- // \r
+ //\r
SaveAndSetDebugTimerInterrupt (DebugTimerInterruptState);\r
- \r
+\r
//\r
// Restore to original TPL\r
//\r
gBS->RestoreTPL (Tpl);\r
- \r
+\r
return EFI_SUCCESS;\r
}\r
\r
// Raise TPL to prevent recursion from EFI timer interrupts\r
//\r
Tpl = gBS->RaiseTPL (TPL_NOTIFY);\r
- \r
+\r
//\r
// Save and disable Debug Timer interrupt to avoid it to access Debug Port\r
//\r
DebugTimerInterruptState = SaveAndSetDebugTimerInterrupt (FALSE);\r
Handle = GetDebugPortHandle ();\r
- \r
+\r
Data8 = (UINT8 *) &DebugHeader;\r
Uint8Buffer = (UINT8 *)Buffer;\r
if ((mSerialIoMode.ControlMask & EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE) != 0) {\r
continue;\r
}\r
//\r
- // Read the input character from Debug Port \r
+ // Read the input character from Debug Port\r
//\r
if (!DebugPortPollBuffer (Handle)) {\r
break;\r
\r
//\r
// Restore Debug Timer interrupt\r
- // \r
+ //\r
SaveAndSetDebugTimerInterrupt (DebugTimerInterruptState);\r
- \r
+\r
//\r
// Restore to original TPL\r
//\r
gBS->RestoreTPL (Tpl);\r
- \r
+\r
return EFI_SUCCESS;\r
}\r
\r
DebugAgentMsgPrint (DEBUG_AGENT_INFO, "Debug Timer attach symbol received %x", *Data8);\r
*BreakSymbol = *Data8;\r
return EFI_SUCCESS;\r
- } \r
+ }\r
if (*Data8 == DEBUG_STARTING_SYMBOL_NORMAL) {\r
Status = ReadRemainingBreakPacket (Handle, &DebugHeader);\r
if (Status == EFI_SUCCESS) {\r
DebugTerminalFifoAdd (&mSerialFifoForTerminal, *Data8);\r
}\r
}\r
- \r
+\r
return EFI_NOT_FOUND;\r
}\r
\r
\r
[Protocols]\r
gEfiSerialIoProtocolGuid ## SOMETIMES_PRODUCES\r
- gEfiDevicePathProtocolGuid ## SOMETIMES_PRODUCES \r
+ gEfiDevicePathProtocolGuid ## SOMETIMES_PRODUCES\r
\r
[Pcd]\r
gEfiMdePkgTokenSpaceGuid.PcdFSBClock ## SOMETIMES_CONSUMES\r
/** @file\r
Debug Agent library implementition.\r
\r
- Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
)\r
{\r
EFI_HOB_GUID_TYPE *GuidHob;\r
- UINT64 *MailboxLocation; \r
+ UINT64 *MailboxLocation;\r
DEBUG_AGENT_MAILBOX *Mailbox;\r
\r
GuidHob = GetFirstGuidHob (&gEfiDebugAgentGuid);\r
MailboxLocation = (UINT64 *) (GET_GUID_HOB_DATA(GuidHob));\r
Mailbox = (DEBUG_AGENT_MAILBOX *)(UINTN)(*MailboxLocation);\r
VerifyMailboxChecksum (Mailbox);\r
- \r
+\r
return Mailbox;\r
}\r
\r
//\r
// Check if Debug Agent initialized in SEC/PEI phase\r
//\r
- Mailbox = GetMailboxFromHob (); \r
+ Mailbox = GetMailboxFromHob ();\r
if (Mailbox != NULL) {\r
mMailboxPointer = Mailbox;\r
break;\r
//\r
// Save original IDT entries\r
//\r
- AsmReadIdtr (&IdtDescriptor); \r
+ AsmReadIdtr (&IdtDescriptor);\r
CopyMem (&IdtEntry, (VOID *)IdtDescriptor.Base, 33 * sizeof(IA32_IDT_GATE_DESCRIPTOR));\r
//\r
// Initialized Debug Agent\r
}\r
//\r
// Find and report PE/COFF image info to HOST\r
- // \r
+ //\r
FindAndReportModuleImageInfo (SIZE_4KB);\r
//\r
// Restore saved IDT entries\r
- // \r
+ //\r
CopyMem ((VOID *)IdtDescriptor.Base, &IdtEntry, 33 * sizeof(IA32_IDT_GATE_DESCRIPTOR));\r
\r
break;\r
\r
default:\r
//\r
- // Only DEBUG_AGENT_INIT_PREMEM_SEC and DEBUG_AGENT_INIT_POSTMEM_SEC are allowed for this \r
+ // Only DEBUG_AGENT_INIT_PREMEM_SEC and DEBUG_AGENT_INIT_POSTMEM_SEC are allowed for this\r
// Debug Agent library instance.\r
//\r
DEBUG ((EFI_D_ERROR, "Debug Agent: The InitFlag value is not allowed!\n"));\r
CpuDeadLoop ();\r
- break; \r
+ break;\r
}\r
}\r
\r
/** @file\r
Debug Port Library implementation based on serial port.\r
\r
- Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
Status = SerialPortInitialize ();\r
if (RETURN_ERROR(Status)) {\r
- DEBUG ((EFI_D_ERROR, "Debug Serial Port: Initialization failed!\n")); \r
+ DEBUG ((EFI_D_ERROR, "Debug Serial Port: Initialization failed!\n"));\r
}\r
\r
if (Function != NULL) {\r
/** @file\r
Debug Port Library implementation based on usb debug port.\r
\r
- Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
VendorId = PciRead16 (PcdGet32(PcdUsbEhciPciAddress) + PCI_VENDOR_ID_OFFSET);\r
DeviceId = PciRead16 (PcdGet32(PcdUsbEhciPciAddress) + PCI_DEVICE_ID_OFFSET);\r
- \r
+\r
if ((VendorId == 0xFFFF) || (DeviceId == 0xFFFF)) {\r
return RETURN_UNSUPPORTED;\r
}\r
ProgInterface = PciRead8 (PcdGet32(PcdUsbEhciPciAddress) + PCI_CLASSCODE_OFFSET);\r
SubClassCode = PciRead8 (PcdGet32(PcdUsbEhciPciAddress) + PCI_CLASSCODE_OFFSET + 1);\r
BaseCode = PciRead8 (PcdGet32(PcdUsbEhciPciAddress) + PCI_CLASSCODE_OFFSET + 2);\r
- \r
+\r
if ((ProgInterface != PCI_IF_EHCI) || (SubClassCode != PCI_CLASS_SERIAL_USB) || (BaseCode != PCI_CLASS_SERIAL)) {\r
return RETURN_UNSUPPORTED;\r
}\r
return RETURN_DEVICE_ERROR;\r
}\r
}\r
- \r
+\r
//\r
// Clearing DONE bit by writing 1\r
//\r
return RETURN_DEVICE_ERROR;\r
}\r
}\r
- \r
+\r
//\r
// Clearing DONE bit by writing 1\r
//\r
Handle->Initialized = USBDBG_NO_DBG_CAB;\r
return Status;\r
}\r
- \r
+\r
Handle->Initialized = USBDBG_DBG_CAB;\r
}\r
\r
USB_DEBUG_PORT_HANDLE Handle;\r
\r
//\r
- // Validate the PCD PcdDebugPortHandleBufferSize value \r
+ // Validate the PCD PcdDebugPortHandleBufferSize value\r
//\r
ASSERT (PcdGet16 (PcdDebugPortHandleBufferSize) == sizeof (USB_DEBUG_PORT_HANDLE));\r
\r
**/\r
VOID\r
XhcSetR32Bit(\r
- IN OUT UINTN Register, \r
+ IN OUT UINTN Register,\r
IN UINT32 BitMask\r
)\r
{\r
**/\r
VOID\r
XhcClearR32Bit(\r
- IN OUT UINTN Register, \r
+ IN OUT UINTN Register,\r
IN UINT32 BitMask\r
)\r
{\r
)\r
{\r
EFI_PHYSICAL_ADDRESS DebugCapabilityBase;\r
- \r
+\r
DebugCapabilityBase = Handle->DebugCapabilityBase;\r
MmioWrite32 ((UINTN)(DebugCapabilityBase + Offset), Data);\r
- \r
+\r
return;\r
}\r
\r
{\r
UINT32 Data;\r
EFI_PHYSICAL_ADDRESS DebugCapabilityBase;\r
- \r
+\r
DebugCapabilityBase = Handle->DebugCapabilityBase;\r
Data = MmioRead32 ((UINTN)(DebugCapabilityBase + Offset));\r
\r
UINT32 Low;\r
UINT32 High;\r
EFI_PHYSICAL_ADDRESS XhciMmioBase;\r
- \r
+\r
Low = PciRead32 (PcdGet32(PcdUsbXhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET);\r
High = PciRead32 (PcdGet32(PcdUsbXhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET + 4);\r
XhciMmioBase = (EFI_PHYSICAL_ADDRESS) (LShiftU64 ((UINT64) High, 32) | Low);\r
\r
VendorId = PciRead16 (PcdGet32(PcdUsbXhciPciAddress) + PCI_VENDOR_ID_OFFSET);\r
DeviceId = PciRead16 (PcdGet32(PcdUsbXhciPciAddress) + PCI_DEVICE_ID_OFFSET);\r
- \r
+\r
if ((VendorId == 0xFFFF) || (DeviceId == 0xFFFF)) {\r
goto Done;\r
}\r
ProgInterface = PciRead8 (PcdGet32(PcdUsbXhciPciAddress) + PCI_CLASSCODE_OFFSET);\r
SubClassCode = PciRead8 (PcdGet32(PcdUsbXhciPciAddress) + PCI_CLASSCODE_OFFSET + 1);\r
BaseCode = PciRead8 (PcdGet32(PcdUsbXhciPciAddress) + PCI_CLASSCODE_OFFSET + 2);\r
- \r
+\r
if ((ProgInterface != PCI_IF_XHCI) || (SubClassCode != PCI_CLASS_SERIAL_USB) || (BaseCode != PCI_CLASS_SERIAL)) {\r
goto Done;\r
}\r
// Get capability pointer from HCCPARAMS at offset 0x10\r
//\r
CapabilityPointer = Handle->XhciMmioBase + (MmioRead32 ((UINTN)(Handle->XhciMmioBase + XHC_HCCPARAMS_OFFSET)) >> 16) * 4;\r
- \r
+\r
//\r
// Search XHCI debug capability\r
//\r
EVENT_RING_SEG_TABLE_ENTRY *ERSTBase;\r
\r
ASSERT (EventRing != NULL);\r
- \r
+\r
//\r
// Allocate Event Ring\r
//\r
EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;\r
EventRing->EventRingDequeue = (EFI_PHYSICAL_ADDRESS)(UINTN) EventRing->EventRingSeg0;\r
EventRing->EventRingEnqueue = (EFI_PHYSICAL_ADDRESS)(UINTN) EventRing->EventRingSeg0;\r
- \r
+\r
//\r
// Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'\r
// and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.\r
{\r
VOID *Buf;\r
LINK_TRB *EndTrb;\r
- \r
+\r
Buf = AllocateAlignBuffer (sizeof (TRB_TEMPLATE) * TrbNum);\r
ASSERT (Buf != NULL);\r
ASSERT (((UINTN) Buf & 0xF) == 0);\r
UINT8 *ManufacturerStrDesc;\r
UINT8 *ProductStrDesc;\r
UINT8 *SerialNumberStrDesc;\r
- \r
+\r
//\r
// Allocate debug device context\r
//\r
ASSERT (Buf != NULL);\r
ASSERT (((UINTN) Buf & 0xF) == 0);\r
ZeroMem (Buf, sizeof (XHC_DC_CONTEXT));\r
- \r
+\r
DebugCapabilityContext = (XHC_DC_CONTEXT *)(UINTN) Buf;\r
Handle->DebugCapabilityContext = (EFI_PHYSICAL_ADDRESS)(UINTN) DebugCapabilityContext;\r
- \r
+\r
//\r
// Initialize DbcInfoContext.\r
//\r
DebugCapabilityContext->EpOutContext.EPType = ED_BULK_OUT;\r
DebugCapabilityContext->EpOutContext.MaxPacketSize = XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE;\r
DebugCapabilityContext->EpOutContext.AverageTRBLength = 0x1000;\r
- \r
+\r
//\r
// Initialize EpInContext.\r
//\r
DebugCapabilityContext->EpInContext.EPType = ED_BULK_IN;\r
DebugCapabilityContext->EpInContext.MaxPacketSize = XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE;\r
DebugCapabilityContext->EpInContext.AverageTRBLength = 0x1000;\r
- \r
+\r
//\r
// Update string descriptor address\r
//\r
ZeroMem (String0Desc, STRING0_DESC_LEN + MANU_DESC_LEN + PRODUCT_DESC_LEN + SERIAL_DESC_LEN);\r
CopyMem (String0Desc, mString0Desc, STRING0_DESC_LEN);\r
DebugCapabilityContext->DbcInfoContext.String0DescAddress = (UINT64)(UINTN)String0Desc;\r
- \r
+\r
ManufacturerStrDesc = String0Desc + STRING0_DESC_LEN;\r
CopyMem (ManufacturerStrDesc, mManufacturerStrDesc, MANU_DESC_LEN);\r
DebugCapabilityContext->DbcInfoContext.ManufacturerStrDescAddress = (UINT64)(UINTN)ManufacturerStrDesc;\r
- \r
+\r
ProductStrDesc = ManufacturerStrDesc + MANU_DESC_LEN;\r
CopyMem (ProductStrDesc, mProductStrDesc, PRODUCT_DESC_LEN);\r
DebugCapabilityContext->DbcInfoContext.ProductStrDescAddress = (UINT64)(UINTN)ProductStrDesc;\r
- \r
+\r
SerialNumberStrDesc = ProductStrDesc + PRODUCT_DESC_LEN;\r
CopyMem (SerialNumberStrDesc, mSerialNumberStrDesc, SERIAL_DESC_LEN);\r
DebugCapabilityContext->DbcInfoContext.SerialNumberStrDescAddress = (UINT64)(UINTN)SerialNumberStrDesc;\r
- \r
+\r
//\r
// Allocate and initialize the Transfer Ring for the Input Endpoint Context.\r
//\r
return EFI_DEVICE_ERROR;\r
}\r
//\r
- // If XHCI supports debug capability, hardware resource has been allocated, \r
+ // If XHCI supports debug capability, hardware resource has been allocated,\r
// but it has not been enabled, try to enable again.\r
//\r
goto Enable;\r
\r
//\r
// Reset port to get debug device discovered\r
- // \r
+ //\r
for (Index = 0; Index < TotalUsb3Port; Index++) {\r
XhcSetR32Bit ((UINTN)XhciOpRegister + XHC_PORTSC_OFFSET + Index * 0x10, BIT4);\r
MicroSecondDelay (10 * 1000);\r
Handle->UrbIn.Data = (EFI_PHYSICAL_ADDRESS)(UINTN) Buffer;\r
Handle->Data = (EFI_PHYSICAL_ADDRESS)(UINTN) Buffer + XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE;\r
Handle->UrbOut.Data = Handle->UrbIn.Data + XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE * 2;\r
- \r
+\r
//\r
// Initialize event ring\r
//\r
ZeroMem (&Handle->EventRing, sizeof (EVENT_RING));\r
Status = CreateEventRing (Handle, &Handle->EventRing);\r
ASSERT_EFI_ERROR (Status);\r
- \r
+\r
//\r
// Init IN and OUT endpoint context\r
//\r
Status = CreateDebugCapabilityContext (Handle);\r
ASSERT_EFI_ERROR (Status);\r
- \r
+\r
//\r
// Init DCDDI1 and DCDDI2\r
//\r
Handle,\r
XHC_DC_DCDDI1,\r
(UINT32)((XHCI_DEBUG_DEVICE_VENDOR_ID << 16) | XHCI_DEBUG_DEVICE_PROTOCOL)\r
- ); \r
+ );\r
\r
XhcWriteDebugReg (\r
Handle,\r
Enable:\r
if ((Handle->Initialized == USB3DBG_NOT_ENABLED) && (!Handle->ChangePortPower)) {\r
//\r
- // If the first time detection is failed, turn port power off and on in order to \r
+ // If the first time detection is failed, turn port power off and on in order to\r
// reset port status this time, then try to check if debug device is ready again.\r
//\r
for (Index = 0; Index < TotalUsb3Port; Index++) {\r
// Set DCE bit and LSE bit to "1" in DCCTRL in first initialization\r
//\r
XhcSetDebugRegBit (Handle, XHC_DC_DCCTRL, BIT1|BIT31);\r
- \r
+\r
XhcDetectDebugCapabilityReady (Handle);\r
- \r
+\r
Status = RETURN_SUCCESS;\r
if (!Handle->Ready) {\r
Handle->Initialized = USB3DBG_NOT_ENABLED;\r
\r
@param[in] Instance Debug port instance.\r
\r
-**/ \r
+**/\r
VOID\r
SetUsb3DebugPortInstance (\r
IN USB3_DEBUG_PORT_HANDLE *Instance\r
/**\r
Return USB3 debug instance address.\r
\r
-**/ \r
+**/\r
USB3_DEBUG_PORT_HANDLE *\r
GetUsb3DebugPortInstance (\r
VOID\r
XhcDataTransfer (UsbDebugPortHandle, EfiUsbDataOut, Buffer + Total, &Sent, DATA_TRANSFER_WRITE_TIMEOUT);\r
Total += Sent;\r
}\r
- \r
+\r
return Total;\r
}\r
\r
USB3_DEBUG_PORT_HANDLE *UsbDebugPortHandle;\r
\r
//\r
- // Validate the PCD PcdDebugPortHandleBufferSize value \r
+ // Validate the PCD PcdDebugPortHandleBufferSize value\r
//\r
ASSERT (PcdGet16 (PcdDebugPortHandleBufferSize) == sizeof (USB3_DEBUG_PORT_HANDLE));\r
\r
);\r
if (!EFI_ERROR (Status) &&\r
(PciIoHandleBuffer != NULL) &&\r
- (PciIoHandleCount != 0)) { \r
+ (PciIoHandleCount != 0)) {\r
for (Index = 0; Index < PciIoHandleCount; Index++) {\r
Status = gBS->HandleProtocol (\r
PciIoHandleBuffer[Index],\r
/**\r
Return USB3 debug instance address pointer.\r
\r
-**/ \r
+**/\r
EFI_PHYSICAL_ADDRESS *\r
GetUsb3DebugPortInstanceAddrPtr (\r
VOID\r
Allocate aligned memory for XHC's usage.\r
\r
@param BufferSize The size, in bytes, of the Buffer.\r
- \r
+\r
@return A pointer to the allocated buffer or NULL if allocation fails.\r
\r
**/\r
EFI_PHYSICAL_ADDRESS TmpAddr;\r
EFI_STATUS Status;\r
VOID *Buf;\r
- \r
+\r
Buf = NULL;\r
- \r
+\r
if (gBS != NULL) {\r
if (mUsb3PciIo != NULL) {\r
Usb3AllocateDmaBuffer (\r
# The format of pci address please refer to SourceLevelDebugPkg.dec\r
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdUsbXhciPciAddress ## CONSUMES\r
\r
- # Per XHCI spec, software shall impose a timeout between the detection of the Debug Host \r
+ # Per XHCI spec, software shall impose a timeout between the detection of the Debug Host\r
# connection and the DbC Run transition to 1. This PCD specifies the timeout value in microsecond.\r
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdUsbXhciDebugDetectTimeout ## SOMETIMES_CONSUMES\r
\r
UINT32 RsvdZ5; // Reserved\r
UINT32 RsvdZ6;\r
UINT32 RsvdZ7;\r
- \r
+\r
UINT32 RsvdZ8;\r
UINT32 RsvdZ9;\r
UINT32 RsvdZ10;\r
UINT32 RsvdZ11;\r
- \r
+\r
UINT32 RsvdZ12;\r
UINT32 RsvdZ13;\r
UINT32 RsvdZ14;\r
UINT64 RsvdZ1:32;\r
UINT64 RsvdZ2;\r
UINT64 RsvdZ3;\r
- UINT64 RsvdZ4; \r
+ UINT64 RsvdZ4;\r
} DBC_INFO_CONTEXT;\r
\r
//\r
// The flag indicates debug capability is supported\r
//\r
BOOLEAN DebugSupport;\r
- \r
+\r
//\r
// The flag indicates debug device is ready\r
//\r
\r
//\r
// The flag indicates if USB 3.0 ports has been turn off/on power\r
- // \r
+ //\r
BOOLEAN ChangePortPower;\r
\r
//\r
\r
//\r
// XHCI OP RegisterBase address\r
- // \r
+ //\r
EFI_PHYSICAL_ADDRESS XhciOpRegister;\r
- \r
+\r
//\r
// XHCI Debug Register Base Address\r
//\r
EFI_PHYSICAL_ADDRESS DebugCapabilityBase;\r
- \r
+\r
//\r
// XHCI Debug Capability offset\r
//\r
- UINT64 DebugCapabilityOffset; \r
- \r
+ UINT64 DebugCapabilityOffset;\r
+\r
//\r
// XHCI Debug Context Address\r
//\r
EFI_PHYSICAL_ADDRESS DebugCapabilityContext;\r
- \r
+\r
//\r
// Transfer Ring\r
//\r
// EventRing\r
//\r
EVENT_RING EventRing;\r
- \r
+\r
//\r
// URB - Read\r
//\r
IN UINT32 Offset,\r
IN UINT32 Bit\r
);\r
- \r
+\r
/**\r
Write the data to the debug register.\r
\r
@param Offset The offset of the debug register.\r
@param Data The data to write.\r
\r
-**/ \r
+**/\r
VOID\r
XhcWriteDebugReg (\r
IN USB3_DEBUG_PORT_HANDLE *Handle,\r
@param[in] BitMask 32-bit mask\r
\r
@return BOOLEAN - TRUE if all bits specified by the mask are enabled.\r
- - FALSE even if one of the bits specified by the mask \r
+ - FALSE even if one of the bits specified by the mask\r
is not enabled.\r
**/\r
BOOLEAN\r
XhcIsBitSet(\r
- UINTN Register, \r
+ UINTN Register,\r
UINT32 BitMask\r
);\r
\r
**/\r
VOID\r
XhcSetR32Bit(\r
- UINTN Register, \r
+ UINTN Register,\r
UINT32 BitMask\r
);\r
\r
**/\r
VOID\r
XhcClearR32Bit(\r
- IN OUT UINTN Register, \r
+ IN OUT UINTN Register,\r
IN UINT32 BitMask\r
);\r
\r
/**\r
Initialize USB3 debug port.\r
- \r
+\r
This method invokes various internal functions to facilitate\r
detection and initialization of USB3 debug port.\r
\r
Allocate aligned memory for XHC's usage.\r
\r
@param BufferSize The size, in bytes, of the Buffer.\r
- \r
+\r
@return A pointer to the allocated buffer or NULL if allocation fails.\r
\r
**/\r
\r
/**\r
The real function to initialize USB3 debug port.\r
- \r
+\r
This method invokes various internal functions to facilitate\r
detection and initialization of USB3 debug port.\r
\r
/**\r
Return USB3 debug instance address pointer.\r
\r
-**/ \r
+**/\r
EFI_PHYSICAL_ADDRESS *\r
GetUsb3DebugPortInstanceAddrPtr (\r
VOID\r
/**\r
Return USB3 debug instance address.\r
\r
-**/ \r
+**/\r
USB3_DEBUG_PORT_HANDLE *\r
GetUsb3DebugPortInstance (\r
VOID\r
/**\r
Return USB3 debug instance address pointer.\r
\r
-**/ \r
+**/\r
EFI_PHYSICAL_ADDRESS *\r
GetUsb3DebugPortInstanceAddrPtr (\r
VOID\r
Allocate aligned memory for XHC's usage.\r
\r
@param BufferSize The size, in bytes, of the Buffer.\r
- \r
+\r
@return A pointer to the allocated buffer or NULL if allocation fails.\r
\r
**/\r
# The format of pci address please refer to SourceLevelDebugPkg.dec\r
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdUsbXhciPciAddress ## CONSUMES\r
\r
- # Per XHCI spec, software shall impose a timeout between the detection of the Debug Host \r
+ # Per XHCI spec, software shall impose a timeout between the detection of the Debug Host\r
# connection and the DbC Run transition to 1. This PCD specifies the timeout value in microsecond.\r
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdUsbXhciDebugDetectTimeout ## SOMETIMES_CONSUMES\r
\r
TrsTrb = (TRB_TEMPLATE *)(UINTN) TrsRing->RingEnqueue;\r
\r
ASSERT (TrsTrb != NULL);\r
- \r
+\r
for (Index = 0; Index < TrsRing->TrbNumber; Index++) {\r
if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {\r
break;\r
{\r
TRB_TEMPLATE *CheckedTrb;\r
UINTN Index;\r
- \r
+\r
CheckedTrb = (TRB_TEMPLATE *)(UINTN) Ring->RingSeg0;\r
- \r
+\r
ASSERT (Ring->TrbNumber == TR_RING_TRB_NUMBER);\r
\r
for (Index = 0; Index < Ring->TrbNumber; Index++) {\r
UINT64 XhcDequeue;\r
UINT32 High;\r
UINT32 Low;\r
- \r
+\r
ASSERT ((Handle != NULL) && (Urb != NULL));\r
\r
if (Urb->Finished) {\r
}\r
\r
EvtTrb = NULL;\r
- \r
+\r
//\r
// Traverse the event ring to find out all new events from the previous check.\r
//\r
XhcSyncEventRing (Handle, &Handle->EventRing);\r
- \r
+\r
for (Index = 0; Index < Handle->EventRing.TrbNumber; Index++) {\r
\r
Status = XhcCheckNewEvent (Handle, &Handle->EventRing, ((TRB_TEMPLATE **)&EvtTrb));\r
//\r
goto EXIT;\r
}\r
- \r
+\r
if ((EvtTrb->Type != TRB_TYPE_COMMAND_COMPLT_EVENT) && (EvtTrb->Type != TRB_TYPE_TRANS_EVENT)) {\r
continue;\r
}\r
- \r
+\r
TRBPtr = (TRB_TEMPLATE *)(UINTN)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));\r
- \r
+\r
if (IsTrbInTrsRing ((TRANSFER_RING *)(UINTN)(Urb->Ring), TRBPtr)) {\r
CheckedUrb = Urb;\r
} else if (IsTrbInTrsRing ((TRANSFER_RING *)(UINTN)(Handle->UrbIn.Ring), TRBPtr)) {\r
} else {\r
continue;\r
}\r
- \r
+\r
if ((EvtTrb->Completecode == TRB_COMPLETION_SHORT_PACKET) ||\r
(EvtTrb->Completecode == TRB_COMPLETION_SUCCESS)) {\r
//\r
\r
//\r
// 7.6.8.2 DCDB Register\r
- // \r
+ //\r
Dcdb = (Urb->Direction == EfiUsbDataIn) ? 0x100 : 0x0;\r
- \r
+\r
XhcWriteDebugReg (\r
Handle,\r
XHC_DC_DCDB,\r
// If time out occurs.\r
//\r
Urb->Result |= EFI_USB_ERR_TIMEOUT;\r
- } \r
+ }\r
//\r
// If URB transfer is error, restore transfer ring to original value before URB transfer\r
// This will make the current transfer TRB is always at the latest unused one in transfer ring.\r
} else {\r
EPRing = &Handle->TransferRingOut;\r
}\r
- \r
+\r
Urb->Ring = (EFI_PHYSICAL_ADDRESS)(UINTN) EPRing;\r
XhcSyncTrsRing (Handle, EPRing);\r
\r
Trb->TrbNormal.ISP = 1;\r
Trb->TrbNormal.IOC = 1;\r
Trb->TrbNormal.Type = TRB_TYPE_NORMAL;\r
- \r
+\r
//\r
// Update the cycle bit to indicate this TRB has been consumed.\r
//\r
Trb->TrbNormal.CycleBit = EPRing->RingPCS & BIT0;\r
- \r
+\r
return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS Status;\r
URB *Urb;\r
EFI_PHYSICAL_ADDRESS UrbData;\r
- \r
+\r
if (Direction == EfiUsbDataIn) {\r
Urb = &Handle->UrbIn;\r
} else {\r
}\r
\r
UrbData = Urb->Data;\r
- \r
+\r
ZeroMem (Urb, sizeof (URB));\r
Urb->Direction = Direction;\r
- \r
+\r
//\r
// Allocate memory to move data from CAR or SMRAM to normal memory\r
// to make XHCI DMA successfully\r
// re-use the pre-allocate buffer in PEI to avoid DXE memory service or gBS are not ready\r
//\r
Urb->Data = UrbData;\r
- \r
+\r
if (Direction == EfiUsbDataIn) {\r
//\r
// Do not break URB data in buffer as it may contain the data which were just put in via DMA by XHC\r
CopyMem ((VOID*)(UINTN) Urb->Data, Data, DataLen);\r
Urb->DataLen = (UINT32) DataLen;\r
}\r
- \r
+\r
Status = XhcCreateTransferTrb (Handle, Urb);\r
ASSERT_EFI_ERROR (Status);\r
\r
{\r
URB *Urb;\r
EFI_STATUS Status;\r
- \r
+\r
//\r
// Validate the parameters\r
//\r
if (Urb->Result == EFI_USB_NOERROR) {\r
Status = EFI_SUCCESS;\r
}\r
- \r
+\r
if (Direction == EfiUsbDataIn) {\r
//\r
// Move data from internal buffer to outside buffer (outside buffer may be in SMRAM...)\r
/** @file\r
Ia32 arch functions to access IDT vector.\r
\r
- Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
@retval FALSE IDT entries were not setuo by Debug Agent.\r
\r
**/\r
-BOOLEAN \r
+BOOLEAN\r
CheckDebugAgentHandler (\r
IN IA32_DESCRIPTOR *IdtDescriptor,\r
IN UINTN InterruptType\r
}\r
\r
/**\r
- Save IDT entry for INT1 and update it. \r
+ Save IDT entry for INT1 and update it.\r
\r
@param[in] IdtDescriptor Pointer to IDT Descriptor.\r
@param[out] SavedIdtEntry Original IDT entry returned.\r
IA32_IDT_GATE_DESCRIPTOR *IdtEntry;\r
UINT16 CodeSegment;\r
UINTN InterruptHandler;\r
- \r
+\r
IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) IdtDescriptor->Base;\r
CopyMem (SavedIdtEntry, &IdtEntry[1], sizeof (IA32_IDT_GATE_DESCRIPTOR));\r
\r
}\r
\r
/**\r
- Restore IDT entry for INT1. \r
+ Restore IDT entry for INT1.\r
\r
@param[in] IdtDescriptor Pointer to IDT Descriptor.\r
@param[in] RestoredIdtEntry IDT entry to be restored.\r
)\r
{\r
IA32_IDT_GATE_DESCRIPTOR *IdtEntry;\r
- \r
+\r
IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) IdtDescriptor->Base;\r
CopyMem (&IdtEntry[1], RestoredIdtEntry, sizeof (IA32_IDT_GATE_DESCRIPTOR));\r
}\r
/** @file\r
PE/Coff Extra Action library instances.\r
\r
- Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
/**\r
Check if the hardware breakpoint in Drx is enabled by checking the Lx and Gx bit in Dr7.\r
- \r
+\r
It assumes that DebugAgent will set both Lx and Gx bit when setting up the hardware breakpoint.\r
\r
\r
Common routine to report the PE/COFF image loading/relocating or unloading event.\r
\r
If ImageContext is NULL, then ASSERT().\r
- \r
+\r
@param ImageContext Pointer to the image context structure that describes the\r
PE/COFF image.\r
@param Signature IMAGE_LOAD_SIGNATURE or IMAGE_UNLOAD_SIGNATURE.\r
if (LoadImageMethod == DEBUG_LOAD_IMAGE_METHOD_IO_HW_BREAKPOINT) {\r
//\r
// If the CPU does not support Debug Extensions(CPUID:01 EDX:BIT2)\r
- // then force use of DEBUG_LOAD_IMAGE_METHOD_SOFT_INT3 \r
+ // then force use of DEBUG_LOAD_IMAGE_METHOD_SOFT_INT3\r
//\r
AsmCpuid (1, NULL, NULL, NULL, &RegEdx);\r
if ((RegEdx & BIT2) == 0) {\r
IdtEntryHooked = TRUE;\r
}\r
}\r
- \r
+\r
//\r
// Save Debug Register State\r
//\r
\r
//\r
// Restore Debug Register State only when Host didn't change it inside exception handler.\r
- // E.g.: User halts the target and sets the HW breakpoint while target is \r
+ // E.g.: User halts the target and sets the HW breakpoint while target is\r
// in the above exception handler\r
//\r
NewDr7 = AsmReadDr7 () | BIT10; // H/w sets bit 10, some simulators don't\r
/** @file\r
PE/Coff Extra Action library instances, it will report image debug info.\r
\r
- Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
@retval FALSE IDT entries were not setuo by Debug Agent.\r
\r
**/\r
-BOOLEAN \r
+BOOLEAN\r
CheckDebugAgentHandler (\r
IN IA32_DESCRIPTOR *IdtDescriptor,\r
IN UINTN InterruptType\r
);\r
\r
/**\r
- Save IDT entry for INT1 and update it. \r
+ Save IDT entry for INT1 and update it.\r
\r
@param[in] IdtDescriptor Pointer to IDT Descriptor.\r
@param[out] SavedIdtEntry Original IDT entry returned.\r
);\r
\r
/**\r
- Restore IDT entry for INT1. \r
+ Restore IDT entry for INT1.\r
\r
@param[in] IdtDescriptor Pointer to IDT Descriptor.\r
@param[in] RestoredIdtEntry IDT entry to be restored.\r
/** @file\r
X64 arch function to access IDT vector.\r
\r
- Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
@retval FALSE IDT entries were not setuo by Debug Agent.\r
\r
**/\r
-BOOLEAN \r
+BOOLEAN\r
CheckDebugAgentHandler (\r
IN IA32_DESCRIPTOR *IdtDescriptor,\r
IN UINTN InterruptType\r
}\r
\r
InterruptHandler = IdtEntry[InterruptType].Bits.OffsetLow +\r
- (((UINTN)IdtEntry[InterruptType].Bits.OffsetHigh) << 16) + \r
+ (((UINTN)IdtEntry[InterruptType].Bits.OffsetHigh) << 16) +\r
(((UINTN)IdtEntry[InterruptType].Bits.OffsetUpper) << 32);\r
if (InterruptHandler >= sizeof (UINT32) && *(UINT32 *)(InterruptHandler - sizeof (UINT32)) == AGENT_HANDLER_SIGNATURE) {\r
return TRUE;\r
}\r
\r
/**\r
- Save IDT entry for INT1 and update it. \r
+ Save IDT entry for INT1 and update it.\r
\r
@param[in] IdtDescriptor Pointer to IDT Descriptor.\r
@param[out] SavedIdtEntry Original IDT entry returned.\r
IA32_IDT_GATE_DESCRIPTOR *IdtEntry;\r
UINT16 CodeSegment;\r
UINTN InterruptHandler;\r
- \r
+\r
IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) IdtDescriptor->Base;\r
CopyMem (SavedIdtEntry, &IdtEntry[1], sizeof (IA32_IDT_GATE_DESCRIPTOR));\r
\r
}\r
\r
/**\r
- Restore IDT entry for INT1. \r
+ Restore IDT entry for INT1.\r
\r
@param[in] IdtDescriptor Pointer to IDT Descriptor.\r
@param[in] RestoredIdtEntry IDT entry to be restored.\r
)\r
{\r
IA32_IDT_GATE_DESCRIPTOR *IdtEntry;\r
- \r
+\r
IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) IdtDescriptor->Base;\r
CopyMem (&IdtEntry[1], RestoredIdtEntry, sizeof (IA32_IDT_GATE_DESCRIPTOR));\r
}\r
# etc.\r
#\r
# Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials are licensed and made available under \r
-# the terms and conditions of the BSD License that accompanies this distribution. \r
+# This program and the accompanying materials are licensed and made available under\r
+# the terms and conditions of the BSD License that accompanies this distribution.\r
# The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php. \r
-# \r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
##\r
\r
# @Expression 0x80000001 | (gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdUsbEhciPciAddress & 0xF0000FFF) == 0\r
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdUsbEhciPciAddress|0x000EF000|UINT32|0x00000003\r
\r
- ## The mask of exception numbers whose handlers would be ignored and cannot be replaced or \r
+ ## The mask of exception numbers whose handlers would be ignored and cannot be replaced or\r
# hooked by Debug Agent Library. Masking INT1/INT3 is invalid.\r
# @Prompt Configure exception numbers not to be hooked by Debug Agent.\r
# @Expression 0x80000001 | (gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdExceptionsIgnoredByDebugger & 0xA) == 0\r
## Note that the memory BAR address is only used before Pci bus resource allocation.\r
# @Prompt Configure xhci host controller memory BAR.\r
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdUsbXhciMemorySpaceBase|0xD0000000|UINT64|0x00000007\r
- \r
+\r
## The pci address of xhci host controller, in which usb debug feature is enabled.\r
# The format of pci address is :<BR>\r
# -----------------------------------------------------------------------<BR>\r
# @Prompt Configure xhci host controller pci address.\r
# @Expression 0x80000001 | (gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdUsbXhciPciAddress & 0xF0000FFF) == 0\r
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdUsbXhciPciAddress|0x000A0000|UINT32|0x00000008\r
- \r
- ## Per XHCI spec, software shall impose a timeout between the detection of the Debug Host \r
+\r
+ ## Per XHCI spec, software shall impose a timeout between the detection of the Debug Host\r
## connection and the DbC Run transition to 1. This PCD specifies the timeout value in microsecond.\r
# @Prompt Configure debug device detection timeout value.\r
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdUsbXhciDebugDetectTimeout|3000000|UINT64|0x00000009\r
## @file\r
# Source Level Debug Package.\r
#\r
-# Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
\r
[LibraryClasses.common]\r
DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
- DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf \r
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf\r
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf\r
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf\r
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
// the terms and conditions of the BSD License that accompanies this distribution.\r
// The full text of the license may be found at\r
// http://opensource.org/licenses/bsd-license.php.\r
-// \r
+//\r
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
//\r
// /** @file\r
// SourceLevelDebug Package Localized Strings and Content.\r
//\r
-// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
+// Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials are licensed and made available under\r
// the terms and conditions of the BSD License that accompanies this distribution.\r
//\r
// **/\r
\r
-#string STR_PROPERTIES_PACKAGE_NAME \r
-#language en-US \r
+#string STR_PROPERTIES_PACKAGE_NAME\r
+#language en-US\r
"SourceLevelDebug package"\r
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