#include <Library/ArmGicLib.h>\r
#include <Library/IoLib.h>\r
\r
+#include "GicV2/ArmGicV2Lib.h"\r
+\r
UINTN\r
EFIAPI\r
ArmGicGetInterfaceIdentification (\r
IN UINTN GicInterruptInterfaceBase\r
)\r
{\r
- // Read the Interrupt Acknowledge Register\r
- return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
+ return ArmGicV2AcknowledgeInterrupt (GicInterruptInterfaceBase);\r
}\r
\r
VOID\r
IN UINTN Source\r
)\r
{\r
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source);\r
+ ArmGicV2EndOfInterrupt (GicInterruptInterfaceBase, Source);\r
}\r
\r
VOID\r
// Disable Gic Distributor\r
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x0);\r
}\r
+
+VOID\r
+EFIAPI\r
+ArmGicEnableInterruptInterface (\r
+ IN INTN GicInterruptInterfaceBase\r
+ )\r
+{\r
+ return ArmGicV2EnableInterruptInterface (GicInterruptInterfaceBase);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicDisableInterruptInterface (\r
+ IN INTN GicInterruptInterfaceBase\r
+ )\r
+{\r
+ return ArmGicV2DisableInterruptInterface (GicInterruptInterfaceBase);\r
+}\r
ArmGicLib.c\r
ArmGicNonSecLib.c\r
\r
+ GicV2/ArmGicV2Lib.c\r
+ GicV2/ArmGicV2NonSecLib.c\r
+\r
[LibraryClasses]\r
IoLib\r
\r
#include <Library/IoLib.h>\r
#include <Library/ArmGicLib.h>\r
\r
-\r
-VOID\r
-EFIAPI\r
-ArmGicEnableInterruptInterface (\r
- IN INTN GicInterruptInterfaceBase\r
- )\r
-{ \r
- /*\r
- * Enable the CPU interface in Non-Secure world\r
- * Note: The ICCICR register is banked when Security extensions are implemented\r
- */\r
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1);\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmGicDisableInterruptInterface (\r
- IN INTN GicInterruptInterfaceBase\r
- )\r
-{\r
- // Disable Gic Interface\r
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x0);\r
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x0);\r
-}\r
-\r
VOID\r
EFIAPI\r
ArmGicEnableDistributor (\r
/** @file\r
*\r
-* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-* \r
-* This program and the accompanying materials \r
-* are licensed and made available under the terms and conditions of the BSD License \r
-* which accompanies this distribution. The full text of the license may be found at \r
-* http://opensource.org/licenses/bsd-license.php \r
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#include <Base.h>\r
-#include <Library/ArmLib.h>\r
-#include <Library/ArmPlatformLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/ArmGicLib.h>\r
\r
-/*\r
- * This function configures the all interrupts to be Non-secure.\r
- *\r
- */\r
-VOID\r
-EFIAPI\r
-ArmGicSetupNonSecure (\r
- IN UINTN MpId,\r
- IN INTN GicDistributorBase,\r
- IN INTN GicInterruptInterfaceBase\r
- )\r
-{\r
- UINTN InterruptId;\r
- UINTN CachedPriorityMask;\r
- UINTN Index;\r
-\r
- CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);\r
-\r
- // Set priority Mask so that no interrupts get through to CPU\r
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);\r
-\r
- InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
-\r
- // Only try to clear valid interrupts. Ignore spurious interrupts.\r
- while ((InterruptId & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase)) {\r
- // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
- ArmGicEndOfInterrupt (GicInterruptInterfaceBase, InterruptId);\r
-\r
- // Next\r
- InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
- }\r
-\r
- // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).\r
- if (ArmPlatformIsPrimaryCore (MpId)) {\r
- // Ensure all GIC interrupts are Non-Secure\r
- for (Index = 0; Index < (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32); Index++) {\r
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);\r
- }\r
- } else {\r
- // The secondary cores only set the Non Secure bit to their banked PPIs\r
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);\r
- }\r
-\r
- // Ensure all interrupts can get through the priority mask\r
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);\r
-}\r
+#include "GicV2/ArmGicV2Lib.h"\r
\r
/*\r
* This function configures the interrupts set by the mask to be secure.\r
\r
VOID\r
EFIAPI\r
-ArmGicEnableInterruptInterface (\r
- IN INTN GicInterruptInterfaceBase\r
+ArmGicEnableDistributor (\r
+ IN INTN GicDistributorBase\r
)\r
{\r
- // Set Priority Mask to allow interrupts\r
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);\r
-\r
- // Enable CPU interface in Secure world\r
- // Enable CPU interface in Non-secure World\r
- // Signal Secure Interrupts to CPU using FIQ line *\r
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,\r
- ARM_GIC_ICCICR_ENABLE_SECURE |\r
- ARM_GIC_ICCICR_ENABLE_NS |\r
- ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);\r
+ // Turn on the GIC distributor\r
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);\r
}\r
\r
VOID\r
EFIAPI\r
-ArmGicDisableInterruptInterface (\r
+ArmGicSetupNonSecure (\r
+ IN UINTN MpId,\r
+ IN INTN GicDistributorBase,\r
IN INTN GicInterruptInterfaceBase\r
)\r
{\r
- UINT32 ControlValue;\r
-\r
- // Disable CPU interface in Secure world and Non-secure World\r
- ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);\r
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmGicEnableDistributor (\r
- IN INTN GicDistributorBase\r
- )\r
-{\r
- // Turn on the GIC distributor\r
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);\r
+ ArmGicV2SetupNonSecure (MpId, GicDistributorBase, GicInterruptInterfaceBase);\r
}\r
ArmGicLib.c\r
ArmGicSecLib.c\r
\r
+ GicV2/ArmGicV2Lib.c\r
+ GicV2/ArmGicV2SecLib.c\r
+\r
[Packages]\r
ArmPkg/ArmPkg.dec\r
ArmPlatformPkg/ArmPlatformPkg.dec\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Library/ArmGicLib.h>\r
+#include <Library/IoLib.h>\r
+\r
+UINTN\r
+EFIAPI\r
+ArmGicV2AcknowledgeInterrupt (\r
+ IN UINTN GicInterruptInterfaceBase\r
+ )\r
+{\r
+ // Read the Interrupt Acknowledge Register\r
+ return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV2EndOfInterrupt (\r
+ IN UINTN GicInterruptInterfaceBase,\r
+ IN UINTN Source\r
+ )\r
+{\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source);\r
+}\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#ifndef _ARM_GIC_V2_H_\r
+#define _ARM_GIC_V2_H_\r
+\r
+//\r
+// GIC definitions\r
+//\r
+\r
+//\r
+// GIC Distributor\r
+//\r
+#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register\r
+#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register\r
+#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register\r
+\r
+// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BITS (see GIC spec)\r
+#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers\r
+#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers\r
+#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers\r
+#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers\r
+#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers\r
+#define ARM_GIC_ICDABR 0x300 // Active Bit Registers\r
+\r
+// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BYTES\r
+#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers\r
+\r
+// Each reg base below repeats for VE_NUM_ARM_GIC_INTERRUPTS\r
+#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers\r
+#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers\r
+\r
+#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register\r
+\r
+// just one of these\r
+#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register\r
+\r
+//\r
+// GIC Cpu interface\r
+//\r
+#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register\r
+#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register\r
+#define ARM_GIC_ICCBPR 0x08 // Binary Point Register\r
+#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register\r
+#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register\r
+#define ARM_GIC_ICCRPR 0x14 // Running Priority Register\r
+#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register\r
+#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register\r
+#define ARM_GIC_ICCIIDR 0xFC // Identification Register\r
+\r
+// Bit Mask for\r
+#define ARM_GIC_ICCIAR_ACKINTID 0x3FF\r
+\r
+// Interrupts from 1020 to 1023 are considered as special interrupts (eg: spurious interrupts)\r
+#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) (((Interrupt) >= 1020) && ((Interrupt) <= 1023))\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV2SetupNonSecure (\r
+ IN UINTN MpId,\r
+ IN INTN GicDistributorBase,\r
+ IN INTN GicInterruptInterfaceBase\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV2EnableInterruptInterface (\r
+ IN INTN GicInterruptInterfaceBase\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV2DisableInterruptInterface (\r
+ IN INTN GicInterruptInterfaceBase\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmGicV2AcknowledgeInterrupt (\r
+ IN UINTN GicInterruptInterfaceBase\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV2EndOfInterrupt (\r
+ IN UINTN GicInterruptInterfaceBase,\r
+ IN UINTN Source\r
+ );\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Uefi.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/ArmGicLib.h>\r
+\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV2EnableInterruptInterface (\r
+ IN INTN GicInterruptInterfaceBase\r
+ )\r
+{\r
+ /*\r
+ * Enable the CPU interface in Non-Secure world\r
+ * Note: The ICCICR register is banked when Security extensions are implemented\r
+ */\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV2DisableInterruptInterface (\r
+ IN INTN GicInterruptInterfaceBase\r
+ )\r
+{\r
+ // Disable Gic Interface\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x0);\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x0);\r
+}\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Base.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/ArmGicLib.h>\r
+\r
+/*\r
+ * This function configures the all interrupts to be Non-secure.\r
+ *\r
+ */\r
+VOID\r
+EFIAPI\r
+ArmGicV2SetupNonSecure (\r
+ IN UINTN MpId,\r
+ IN INTN GicDistributorBase,\r
+ IN INTN GicInterruptInterfaceBase\r
+ )\r
+{\r
+ UINTN InterruptId;\r
+ UINTN CachedPriorityMask;\r
+ UINTN Index;\r
+ UINTN MaxInterrupts;\r
+\r
+ CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);\r
+\r
+ // Set priority Mask so that no interrupts get through to CPU\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);\r
+\r
+ InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
+ MaxInterrupts = ArmGicGetMaxNumInterrupts (GicDistributorBase);\r
+\r
+ // Only try to clear valid interrupts. Ignore spurious interrupts.\r
+ while ((InterruptId & 0x3FF) < MaxInterrupts) {\r
+ // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
+ ArmGicEndOfInterrupt (GicInterruptInterfaceBase, InterruptId);\r
+\r
+ // Next\r
+ InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
+ }\r
+\r
+ // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).\r
+ if (ArmPlatformIsPrimaryCore (MpId)) {\r
+ // Ensure all GIC interrupts are Non-Secure\r
+ for (Index = 0; Index < (MaxInterrupts / 32); Index++) {\r
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);\r
+ }\r
+ } else {\r
+ // The secondary cores only set the Non Secure bit to their banked PPIs\r
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);\r
+ }\r
+\r
+ // Ensure all interrupts can get through the priority mask\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV2EnableInterruptInterface (\r
+ IN INTN GicInterruptInterfaceBase\r
+ )\r
+{\r
+ // Set Priority Mask to allow interrupts\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);\r
+\r
+ // Enable CPU interface in Secure world\r
+ // Enable CPU interface in Non-secure World\r
+ // Signal Secure Interrupts to CPU using FIQ line *\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,\r
+ ARM_GIC_ICCICR_ENABLE_SECURE |\r
+ ARM_GIC_ICCICR_ENABLE_NS |\r
+ ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV2DisableInterruptInterface (\r
+ IN INTN GicInterruptInterfaceBase\r
+ )\r
+{\r
+ UINT32 ControlValue;\r
+\r
+ // Disable CPU interface in Secure world and Non-secure World\r
+ ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));\r
+}\r
#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)\r
#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)\r
\r
-// Bit Mask for\r
-#define ARM_GIC_ICCIAR_ACKINTID 0x3FF\r
-\r
UINTN\r
EFIAPI\r
ArmGicGetInterfaceIdentification (\r
projects / mirror_edk2.git / commitdiff