ArmPkg/PrePeiCore: adhere to architectural stack alignment requirement

Instead of using fuzzy arithmetic with a hardcoded stack alignment value
of 0x4, use the symbolic constant CPU_STACK_ALIGNMENT (which is at least
8 bytes, btw) to round the temporary stack base and size.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19163 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
index a86f739fd15575b45910e22324f892a38c889b05..46f5806f1d7509f1a5c886e090822a34f43f3b2c 100644 (file)
--- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c
+++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
@@ -130,14 +130,10 @@ PrimaryMain (
 \r
   // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at\r
   // the base of the primary core stack\r
-  PpiListSize = ALIGN_VALUE(PpiListSize, 0x4);\r
+  PpiListSize = ALIGN_VALUE(PpiListSize, CPU_STACK_ALIGNMENT);\r
   TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;\r
   TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;\r
 \r
-  // Make sure the size is 8-byte aligned. Once divided by 2, the size should be 4-byte aligned\r
-  // to ensure the stack pointer is 4-byte aligned.\r
-  TemporaryRamSize = TemporaryRamSize - (TemporaryRamSize & (0x8-1));\r
-\r
   //\r
   // Bind this information into the SEC hand-off state\r
   // Note: this must be in sync with the stuff in the asm file\r
@@ -149,8 +145,8 @@ PrimaryMain (
   SecCoreData.TemporaryRamBase       = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)\r
   SecCoreData.TemporaryRamSize       = TemporaryRamSize;\r
   SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;\r
-  SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize / 2;\r
-  SecCoreData.StackBase              = (VOID *)ALIGN_VALUE((UINTN)(SecCoreData.TemporaryRamBase) + SecCoreData.PeiTemporaryRamSize, 0x4);\r
+  SecCoreData.PeiTemporaryRamSize    = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);\r
+  SecCoreData.StackBase              = SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize;\r
   SecCoreData.StackSize              = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;\r
 \r
   // Jump to PEI core entry point\r

diff --git a/ArmPlatformPkg/PrePeiCore/MainUniCore.c b/ArmPlatformPkg/PrePeiCore/MainUniCore.c
index 6317f178cae578517eed9e3a86ff44b63c086e1e..e4bbca4cb4aa8740ca3ec45933d89ca521c48911 100644 (file)
--- a/ArmPlatformPkg/PrePeiCore/MainUniCore.c
+++ b/ArmPlatformPkg/PrePeiCore/MainUniCore.c
@@ -39,14 +39,10 @@ PrimaryMain (
 \r
   // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at\r
   // the base of the primary core stack\r
-  PpiListSize = ALIGN_VALUE(PpiListSize, 0x4);\r
+  PpiListSize = ALIGN_VALUE(PpiListSize, CPU_STACK_ALIGNMENT);\r
   TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;\r
   TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;\r
 \r
-  // Make sure the size is 8-byte aligned. Once divided by 2, the size should be 4-byte aligned\r
-  // to ensure the stack pointer is 4-byte aligned.\r
-  TemporaryRamSize = TemporaryRamSize - (TemporaryRamSize & (0x8-1));\r
-\r
   //\r
   // Bind this information into the SEC hand-off state\r
   // Note: this must be in sync with the stuff in the asm file\r
@@ -58,8 +54,8 @@ PrimaryMain (
   SecCoreData.TemporaryRamBase       = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)\r
   SecCoreData.TemporaryRamSize       = TemporaryRamSize;\r
   SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;\r
-  SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize / 2;\r
-  SecCoreData.StackBase              = (VOID *)ALIGN_VALUE((UINTN)(SecCoreData.TemporaryRamBase) + SecCoreData.PeiTemporaryRamSize, 0x4);\r
+  SecCoreData.PeiTemporaryRamSize    = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);\r
+  SecCoreData.StackBase              = SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize;\r
   SecCoreData.StackSize              = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;\r
 \r
   // Jump to PEI core entry point\r