ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI\r
ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI\r
S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state\r
- 0xE2, // PState control\r
+ 0, // PState control\r
PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk\r
PM1b_EVT_BLK, // Port address of Power Mgt 1b Event Reg Blk\r
PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk\r
GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk\r
GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk\r
GPE1_BASE, // offset in gpe model where gpe1 events start\r
- 0xE3, // _CST support\r
+ 0, // _CST support\r
P_LVL2_LAT, // worst case HW latency to enter/exit C2 state\r
P_LVL3_LAT, // worst case HW latency to enter/exit C3 state\r
FLUSH_SIZE, // Size of area read to flush caches\r
\r
#define INT_MODEL 0x01\r
#define SCI_INT_VECTOR 0x0009\r
-#define SMI_CMD_IO_PORT 0 // If SMM was supported, then this would be 0xB2\r
-#define ACPI_ENABLE 0\r
-#define ACPI_DISABLE 0\r
+#define SMI_CMD_IO_PORT 0xB2\r
+#define ACPI_ENABLE 0xF1\r
+#define ACPI_DISABLE 0xF0\r
#define S4BIOS_REQ 0x00\r
#define PM1a_EVT_BLK 0x0000b000\r
#define PM1b_EVT_BLK 0x00000000\r