Add core SMBIOS 2.7.0 and 2.7.1 support.

Signed-off-by: lzeng14
Reviewed-by: li-elvin
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11689 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdePkg/Include/IndustryStandard/SmBios.h b/MdePkg/Include/IndustryStandard/SmBios.h
index 834bb4092cb72c274fe616d3cb0634d48466615b..c9eb8f7ba1107f49011064ec9003c592c12186d7 100644 (file)
--- a/MdePkg/Include/IndustryStandard/SmBios.h
+++ b/MdePkg/Include/IndustryStandard/SmBios.h
@@ -1,7 +1,7 @@
 /** @file\r
-  Industry Standard Definitions of SMBIOS Table Specification v2.6.1\r
+  Industry Standard Definitions of SMBIOS Table Specification v2.7.1\r
 \r
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials are licensed and made available under \r
 the terms and conditions of the BSD License that accompanies this distribution.  \r
 The full text of the license may be found at\r
@@ -22,9 +22,19 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 ///\r
 #define SMBIOS_HANDLE_RESERVED_BEGIN 0xFF00\r
 \r
+///\r
+/// Reference SMBIOS 2.7, chapter 6.1.2.\r
+/// The UEFI Platform Initialization Specification reserves handle number FFFEh for its\r
+/// EFI_SMBIOS_PROTOCOL.Add() function to mean "assign an unused handle number automatically."\r
+/// This number is not used for any other purpose by the SMBIOS specification.\r
+///\r
+#define SMBIOS_HANDLE_PI_RESERVED 0xFFFE\r
+\r
 ///\r
 /// Reference SMBIOS 2.6, chapter 3.1.3.\r
 /// Each text string is limited to 64 significant characters due to system MIF limitations.\r
+/// Reference SMBIOS 2.7, chapter 6.1.3.\r
+/// It will have no limit on the length of each individual text string.\r
 ///\r
 #define SMBIOS_STRING_MAX_LENGTH     64\r
 \r
@@ -77,14 +87,14 @@ typedef struct {
 typedef UINT8 SMBIOS_TABLE_STRING;\r
 \r
 ///\r
-/// BIOS Characteristics  \r
-/// Defines which functions the BIOS supports. PCI, PCMCIA, Flash, etc. \r
+/// BIOS Characteristics\r
+/// Defines which functions the BIOS supports. PCI, PCMCIA, Flash, etc.\r
 ///\r
 typedef struct {\r
   UINT32  Reserved                          :2;  ///< Bits 0-1.\r
-  UINT32  Unknown                           :1; \r
-  UINT32  BiosCharacteristicsNotSupported   :1; \r
-  UINT32  IsaIsSupported                    :1;  \r
+  UINT32  Unknown                           :1;\r
+  UINT32  BiosCharacteristicsNotSupported   :1;\r
+  UINT32  IsaIsSupported                    :1;\r
   UINT32  McaIsSupported                    :1;\r
   UINT32  EisaIsSupported                   :1;\r
   UINT32  PciIsSupported                    :1;\r
@@ -117,14 +127,14 @@ typedef struct {
 } MISC_BIOS_CHARACTERISTICS;\r
 \r
 ///\r
-/// BIOS Characteristics Extension Byte 1 .\r
-/// This information, available for SMBIOS version 2.1 and later, appears at offset 12h \r
-/// within the BIOS Information  structure.\r
+/// BIOS Characteristics Extension Byte 1.\r
+/// This information, available for SMBIOS version 2.1 and later, appears at offset 12h\r
+/// within the BIOS Information structure.\r
 ///\r
 typedef struct {\r
   UINT8  AcpiIsSupported                   :1;\r
-  UINT8  UsbLegacyIsSupported              :1; \r
-  UINT8  AgpIsSupported                    :1; \r
+  UINT8  UsbLegacyIsSupported              :1;\r
+  UINT8  AgpIsSupported                    :1;\r
   UINT8  I20BootIsSupported                :1;\r
   UINT8  Ls120BootIsSupported              :1;\r
   UINT8  AtapiZipDriveBootIsSupported      :1;\r
@@ -134,14 +144,16 @@ typedef struct {
 \r
 ///\r
 /// BIOS Characteristics Extension Byte 2.\r
-/// This information, available for SMBIOS version 2.3 and later, appears at offset 13h \r
+/// This information, available for SMBIOS version 2.3 and later, appears at offset 13h\r
 /// within the BIOS Information structure.\r
 ///\r
 typedef struct {\r
   UINT8  BiosBootSpecIsSupported              :1;\r
-  UINT8  FunctionKeyNetworkBootIsSupported    :1; \r
-  UINT8  TargetContentDistributionEnabled     :1; \r
-  UINT8  ExtensionByte2Reserved               :1;\r
+  UINT8  FunctionKeyNetworkBootIsSupported    :1;\r
+  UINT8  TargetContentDistributionEnabled     :1;\r
+  UINT8  UefiSpecificationSupported           :1;\r
+  UINT8  VirtualMachineSupported              :1;\r
+  UINT8  ExtensionByte2Reserved               :3;\r
 } MBCE_SYSTEM_RESERVED;\r
 \r
 ///\r
@@ -150,7 +162,6 @@ typedef struct {
 typedef struct {\r
   MBCE_BIOS_RESERVED    BiosReserved;\r
   MBCE_SYSTEM_RESERVED  SystemReserved;\r
-  UINT8                 Reserved;\r
 } MISC_BIOS_CHARACTERISTICS_EXTENSION;\r
 \r
 ///\r
@@ -421,12 +432,23 @@ typedef enum {
   ProcessorFamilyAlpha21164a            = 0x35,\r
   ProcessorFamilyAlpha21264             = 0x36,\r
   ProcessorFamilyAlpha21364             = 0x37,\r
+  ProcessorFamilyAmdTurionIIUltraDualCoreMobileM    = 0x38,\r
+  ProcessorFamilyAmdTurionIIDualCoreMobileM         = 0x39,\r
+  ProcessorFamilyAmdAthlonIIDualCoreM   = 0x3A,\r
+  ProcessorFamilyAmdOpteron6100Series   = 0x3B,\r
+  ProcessorFamilyAmdOpteron4100Series   = 0x3C,\r
+  ProcessorFamilyAmdOpteron6200Series   = 0x3D,\r
+  ProcessorFamilyAmdOpteron4200Series   = 0x3E,\r
   ProcessorFamilyMips                   = 0x40,\r
   ProcessorFamilyMIPSR4000              = 0x41,\r
   ProcessorFamilyMIPSR4200              = 0x42,\r
   ProcessorFamilyMIPSR4400              = 0x43,\r
   ProcessorFamilyMIPSR4600              = 0x44,\r
   ProcessorFamilyMIPSR10000             = 0x45,\r
+  ProcessorFamilyAmdCSeries             = 0x46,\r
+  ProcessorFamilyAmdESeries             = 0x47,\r
+  ProcessorFamilyAmdSSeries             = 0x48,\r
+  ProcessorFamilyAmdGSeries             = 0x49,\r
   ProcessorFamilySparc                  = 0x50,\r
   ProcessorFamilySuperSparc             = 0x51,\r
   ProcessorFamilymicroSparcII           = 0x52,\r
@@ -513,6 +535,8 @@ typedef enum {
   ProcessorFamilyG5                     = 0xCA,\r
   ProcessorFamilyG6                     = 0xCB,\r
   ProcessorFamilyzArchitectur           = 0xCC,\r
+  ProcessorFamilyIntelCoreI5            = 0xCD,\r
+  ProcessorFamilyIntelCoreI3            = 0xCE,\r
   ProcessorFamilyViaC7M                 = 0xD2,\r
   ProcessorFamilyViaC7D                 = 0xD3,\r
   ProcessorFamilyViaC7                  = 0xD4,\r
@@ -520,17 +544,23 @@ typedef enum {
   ProcessorFamilyMultiCoreIntelXeon           = 0xD6,\r
   ProcessorFamilyDualCoreIntelXeon3Series     = 0xD7,\r
   ProcessorFamilyQuadCoreIntelXeon3Series     = 0xD8,\r
+  ProcessorFamilyViaNano                      = 0xD9,\r
   ProcessorFamilyDualCoreIntelXeon5Series     = 0xDA,\r
   ProcessorFamilyQuadCoreIntelXeon5Series     = 0xDB,\r
   ProcessorFamilyDualCoreIntelXeon7Series     = 0xDD,\r
   ProcessorFamilyQuadCoreIntelXeon7Series     = 0xDE,\r
   ProcessorFamilyMultiCoreIntelXeon7Series    = 0xDF,\r
+  ProcessorFamilyMultiCoreIntelXeon3400Series = 0xE0,\r
   ProcessorFamilyEmbeddedAmdOpteronQuadCore   = 0xE6,\r
   ProcessorFamilyAmdPhenomTripleCore          = 0xE7,\r
   ProcessorFamilyAmdTurionUltraDualCoreMobile = 0xE8,\r
   ProcessorFamilyAmdTurionDualCoreMobile      = 0xE9,\r
   ProcessorFamilyAmdAthlonDualCore            = 0xEA,\r
   ProcessorFamilyAmdSempronSI                 = 0xEB,\r
+  ProcessorFamilyAmdPhenomII                  = 0xEC,\r
+  ProcessorFamilyAmdAthlonII                  = 0xED,\r
+  ProcessorFamilySixCoreAmdOpteron            = 0xEE,\r
+  ProcessorFamilyAmdSempronM                  = 0xEF,\r
   ProcessorFamilyi860                   = 0xFA,\r
   ProcessorFamilyi960                   = 0xFB,\r
   ProcessorFamilyIndicatorFamily2       = 0xFE,\r
@@ -577,7 +607,24 @@ typedef enum {
   ProcessorUpgradeSocketS1      = 0x16,\r
   ProcessorUpgradeAM2           = 0x17,\r
   ProcessorUpgradeF1207         = 0x18,\r
-  ProcessorSocketLGA1366        = 0x19\r
+  ProcessorSocketLGA1366        = 0x19,\r
+  ProcessorUpgradeSocketG34     = 0x1A,\r
+  ProcessorUpgradeSocketAM3     = 0x1B,\r
+  ProcessorUpgradeSocketC32     = 0x1C,\r
+  ProcessorUpgradeSocketLGA1156 = 0x1D,\r
+  ProcessorUpgradeSocketLGA1567 = 0x1E,\r
+  ProcessorUpgradeSocketPGA988A = 0x1F,\r
+  ProcessorUpgradeSocketBGA1288 = 0x20,\r
+  ProcessorUpgradeSocketrPGA988B = 0x21,\r
+  ProcessorUpgradeSocketBGA1023 = 0x22,\r
+  ProcessorUpgradeSocketBGA1224 = 0x23,\r
+  ProcessorUpgradeSocketBGA1155 = 0x24,\r
+  ProcessorUpgradeSocketLGA1356 = 0x25,\r
+  ProcessorUpgradeSocketLGA2011 = 0x26,\r
+  ProcessorUpgradeSocketFS1     = 0x27,\r
+  ProcessorUpgradeSocketFS2     = 0x28,\r
+  ProcessorUpgradeSocketFM1     = 0x29,\r
+  ProcessorUpgradeSocketFM2     = 0x2A\r
 } PROCESSOR_UPGRADE;\r
 \r
 ///\r
@@ -854,7 +901,8 @@ typedef enum {
   CacheAssociativity24Way        = 0x0A,\r
   CacheAssociativity32Way        = 0x0B,\r
   CacheAssociativity48Way        = 0x0C,\r
-  CacheAssociativity64Way        = 0x0D\r
+  CacheAssociativity64Way        = 0x0D,\r
+  CacheAssociativity20Way        = 0x0E\r
 } CACHE_ASSOCIATIVITY_DATA;\r
 \r
 ///\r
@@ -1021,7 +1069,13 @@ typedef enum {
   SlotTypePciExpressGen2X2             = 0xAD,\r
   SlotTypePciExpressGen2X4             = 0xAE,\r
   SlotTypePciExpressGen2X8             = 0xAF,\r
-  SlotTypePciExpressGen2X16            = 0xB0\r
+  SlotTypePciExpressGen2X16            = 0xB0,\r
+  SlotTypePciExpressGen3               = 0xB1,\r
+  SlotTypePciExpressGen3X1             = 0xB2,\r
+  SlotTypePciExpressGen3X2             = 0xB3,\r
+  SlotTypePciExpressGen3X4             = 0xB4,\r
+  SlotTypePciExpressGen3X8             = 0xB5,\r
+  SlotTypePciExpressGen3X16            = 0xB6\r
 } MISC_SLOT_TYPE;\r
 \r
 ///\r
@@ -1342,6 +1396,10 @@ typedef struct {
   UINT32                    MaximumCapacity;\r
   UINT16                    MemoryErrorInformationHandle;\r
   UINT16                    NumberOfMemoryDevices;\r
+  //\r
+  // Add for smbios 2.7\r
+  //\r
+  UINT64                    ExtendedMaximumCapacity;\r
 } SMBIOS_TABLE_TYPE16;\r
 \r
 ///\r
@@ -1407,7 +1465,9 @@ typedef struct {
   UINT16    WindowDram      :1;\r
   UINT16    CacheDram       :1;\r
   UINT16    Nonvolatile     :1;\r
-  UINT16    Reserved1       :3;\r
+  UINT16    Registered      :1;\r
+  UINT16    Unbuffered      :1;\r
+  UINT16    Reserved1       :1;\r
 } MEMORY_DEVICE_TYPE_DETAIL;\r
 \r
 ///\r
@@ -1440,7 +1500,12 @@ typedef struct {
   //\r
   // Add for smbios 2.6\r
   //  \r
-  UINT8                 Attributes;\r
+  UINT8                     Attributes;\r
+  //\r
+  // Add for smbios 2.7\r
+  //\r
+  UINT32                    ExtendedSize;\r
+  UINT16                    ConfiguredMemoryClockSpeed;\r
 } SMBIOS_TABLE_TYPE17;\r
 \r
 ///\r
@@ -1513,6 +1578,11 @@ typedef struct {
   UINT32                EndingAddress;\r
   UINT16                MemoryArrayHandle;\r
   UINT8                 PartitionWidth;\r
+  //\r
+  // Add for smbios 2.7\r
+  //\r
+  UINT64                ExtendedStartingAddress;\r
+  UINT64                ExtendedEndingAddress;\r
 } SMBIOS_TABLE_TYPE19;\r
 \r
 ///\r
@@ -1530,6 +1600,11 @@ typedef struct {
   UINT8                 PartitionRowPosition;\r
   UINT8                 InterleavePosition;\r
   UINT8                 InterleavedDataDepth;\r
+  //\r
+  // Add for smbios 2.7\r
+  //\r
+  UINT64                ExtendedStartingAddress;\r
+  UINT64                ExtendedEndingAddress;\r
 } SMBIOS_TABLE_TYPE20;\r
 \r
 ///\r
@@ -1711,6 +1786,10 @@ typedef struct {
   UINT8                             CoolingUnitGroup;\r
   UINT32                            OEMDefined;\r
   UINT16                            NominalSpeed;\r
+  //\r
+  // Add for smbios 2.7\r
+  //\r
+  SMBIOS_TABLE_STRING               Description;\r
 } SMBIOS_TABLE_TYPE27;\r
 \r
 ///\r
@@ -1970,9 +2049,14 @@ typedef enum {
 ///\r
 /// IPMI Device Information (Type 38).\r
 ///\r
-/// The information in this structure defines the attributes of an \r
+/// The information in this structure defines the attributes of an\r
 /// Intelligent Platform Management Interface (IPMI) Baseboard Management Controller (BMC).\r
-/// \r
+///\r
+/// The Type 42 structure can also be used to describe a physical management controller\r
+/// host interface and one or more protocols that share that interface. If IPMI is not\r
+/// shared with other protocols, either the Type 38 or Type 42 structures can be used.\r
+/// Providing Type 38 is recommended for backward compatibility.\r
+///\r
 typedef struct {\r
   SMBIOS_STRUCTURE      Hdr;\r
   UINT8                 InterfaceType;              ///< The enumeration value from BMC_INTERFACE_TYPE.\r
@@ -2000,8 +2084,8 @@ typedef struct {
 ///\r
 /// System Power Supply (Type 39).\r
 ///\r
-/// This structure identifies attributes of a system power supply.  One instance\r
-/// of this record is present for each possible power supply in a system.  \r
+/// This structure identifies attributes of a system power supply. One instance\r
+/// of this record is present for each possible power supply in a system.\r
 ///\r
 typedef struct {\r
   SMBIOS_STRUCTURE                  Hdr;\r
@@ -2074,9 +2158,32 @@ typedef struct {
   UINT8                             DeviceTypeInstance;\r
   UINT16                            SegmentGroupNum;\r
   UINT8                             BusNum;\r
-  UINT8                             DevFuncNum;  \r
+  UINT8                             DevFuncNum;\r
 } SMBIOS_TABLE_TYPE41;\r
 \r
+///\r
+/// Management Controller Host Interface (Type 42).\r
+///\r
+/// The information in this structure defines the attributes of a Management\r
+/// Controller Host Interface that is not discoverable by "Plug and Play" mechanisms.\r
+///\r
+/// Type 42 should be used for management controller host interfaces that use protocols\r
+/// other than IPMI or that use multiple protocols on a single host interface type.\r
+///\r
+/// This structure should also be provided if IPMI is shared with other protocols\r
+/// over the same interface hardware. If IPMI is not shared with other protocols,\r
+/// either the Type 38 or Type 42 structures can be used. Providing Type 38 is\r
+/// recommended for backward compatibility. The structures are not required to\r
+/// be mutually exclusive. Type 38 and Type 42 structures may be implemented\r
+/// simultaneously to provide backward compatibility with IPMI applications or drivers\r
+/// that do not yet recognize the Type 42 structure.\r
+///\r
+typedef struct {\r
+  SMBIOS_STRUCTURE                  Hdr;\r
+  UINT8                             InterfaceType;\r
+  UINT8                             MCHostInterfaceData[1]; ///< This field has a minimum of four bytes\r
+} SMBIOS_TABLE_TYPE42;\r
+\r
 ///\r
 /// Inactive (Type 126)\r
 ///\r