UefiCpuPkg/PiSmmCpu: Change variable names and comments to follow SDM

Per SDM, for IA-32e 4-KByte paging, there are four layers in the page
table structure:
1. PML4
2. Page-Directory-Pointer Table (PDPT)
3. Page-Directory (PD)
4. Page Table (PT)

The patch changes the local variable names and comments to use
"PML4", "PDPT", "PD", "PT" to better align to terms used in SDM.

There is no functionality impact for this change.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
index 3b2f967355d4aaaa763e9b9f04f6ab311b94dfcb..e2b6a2d9b27ad8a77a9a2badeffdaf3bdb2a4406 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
@@ -535,15 +535,15 @@ InitPaging (
   )\r
 {\r
   UINT64                            *Pml4;\r
-  UINT64                            *Pde;\r
-  UINT64                            *Pte;\r
+  UINT64                            *Pdpt;\r
+  UINT64                            *Pd;\r
   UINT64                            *Pt;\r
   UINTN                             Address;\r
-  UINTN                             Level1;\r
-  UINTN                             Level2;\r
-  UINTN                             Level3;\r
-  UINTN                             Level4;\r
-  UINTN                             NumberOfPdpEntries;\r
+  UINTN                             Pml4Index;\r
+  UINTN                             PdptIndex;\r
+  UINTN                             PdIndex;\r
+  UINTN                             PtIndex;\r
+  UINTN                             NumberOfPdptEntries;\r
   UINTN                             NumberOfPml4Entries;\r
   UINTN                             SizeOfMemorySpace;\r
   BOOLEAN                           Nx;\r
@@ -556,143 +556,143 @@ InitPaging (
     //\r
     if (SizeOfMemorySpace <= 39 ) {\r
       NumberOfPml4Entries = 1;\r
-      NumberOfPdpEntries = (UINT32)LShiftU64 (1, (SizeOfMemorySpace - 30));\r
+      NumberOfPdptEntries = (UINT32)LShiftU64 (1, (SizeOfMemorySpace - 30));\r
     } else {\r
       NumberOfPml4Entries = (UINT32)LShiftU64 (1, (SizeOfMemorySpace - 39));\r
-      NumberOfPdpEntries = 512;\r
+      NumberOfPdptEntries = 512;\r
     }\r
   } else {\r
     NumberOfPml4Entries = 1;\r
-    NumberOfPdpEntries  = 4;\r
+    NumberOfPdptEntries  = 4;\r
   }\r
 \r
   //\r
   // Go through page table and change 2MB-page into 4KB-page.\r
   //\r
-  for (Level1 = 0; Level1 < NumberOfPml4Entries; Level1++) {\r
+  for (Pml4Index = 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) {\r
     if (sizeof (UINTN) == sizeof (UINT64)) {\r
-      if ((Pml4[Level1] & IA32_PG_P) == 0) {\r
+      if ((Pml4[Pml4Index] & IA32_PG_P) == 0) {\r
         //\r
-        // If Pml4 entry does not exist, skip it\r
+        // If PML4 entry does not exist, skip it\r
         //\r
         continue;\r
       }\r
-      Pde = (UINT64 *)(UINTN)(Pml4[Level1] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
+      Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
     } else {\r
-      Pde = (UINT64*)(UINTN)mSmmProfileCr3;\r
+      Pdpt = (UINT64*)(UINTN)mSmmProfileCr3;\r
     }\r
-    for (Level2 = 0; Level2 < NumberOfPdpEntries; Level2++, Pde++) {\r
-      if ((*Pde & IA32_PG_P) == 0) {\r
+    for (PdptIndex = 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, Pdpt++) {\r
+      if ((*Pdpt & IA32_PG_P) == 0) {\r
         //\r
-        // If PDE entry does not exist, skip it\r
+        // If PDPT entry does not exist, skip it\r
         //\r
         continue;\r
       }\r
-      if ((*Pde & IA32_PG_PS) != 0) {\r
+      if ((*Pdpt & IA32_PG_PS) != 0) {\r
         //\r
         // This is 1G entry, skip it\r
         //\r
         continue;\r
       }\r
-      Pte = (UINT64 *)(UINTN)(*Pde & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
-      if (Pte == 0) {\r
+      Pd = (UINT64 *)(UINTN)(*Pdpt & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
+      if (Pd == 0) {\r
         continue;\r
       }\r
-      for (Level3 = 0; Level3 < SIZE_4KB / sizeof (*Pte); Level3++, Pte++) {\r
-        if ((*Pte & IA32_PG_P) == 0) {\r
+      for (PdIndex = 0; PdIndex < SIZE_4KB / sizeof (*Pd); PdIndex++, Pd++) {\r
+        if ((*Pd & IA32_PG_P) == 0) {\r
           //\r
-          // If PTE entry does not exist, skip it\r
+          // If PD entry does not exist, skip it\r
           //\r
           continue;\r
         }\r
-        Address = (((Level2 << 9) + Level3) << 21);\r
+        Address = (((PdptIndex << 9) + PdIndex) << 21);\r
 \r
         //\r
         // If it is 2M page, check IsAddressSplit()\r
         //\r
-        if (((*Pte & IA32_PG_PS) != 0) && IsAddressSplit (Address)) {\r
+        if (((*Pd & IA32_PG_PS) != 0) && IsAddressSplit (Address)) {\r
           //\r
           // Based on current page table, create 4KB page table for split area.\r
           //\r
-          ASSERT (Address == (*Pte & PHYSICAL_ADDRESS_MASK));\r
+          ASSERT (Address == (*Pd & PHYSICAL_ADDRESS_MASK));\r
 \r
           Pt = AllocatePageTableMemory (1);\r
           ASSERT (Pt != NULL);\r
 \r
           // Split it\r
-          for (Level4 = 0; Level4 < SIZE_4KB / sizeof(*Pt); Level4++) {\r
-            Pt[Level4] = Address + ((Level4 << 12) | mAddressEncMask | PAGE_ATTRIBUTE_BITS);\r
+          for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof(*Pt); PtIndex++) {\r
+            Pt[PtIndex] = Address + ((PtIndex << 12) | mAddressEncMask | PAGE_ATTRIBUTE_BITS);\r
           } // end for PT\r
-          *Pte = (UINT64)(UINTN)Pt | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
+          *Pd = (UINT64)(UINTN)Pt | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
         } // end if IsAddressSplit\r
-      } // end for PTE\r
-    } // end for PDE\r
-  }\r
+      } // end for PD\r
+    } // end for PDPT\r
+  } // end for PML4\r
 \r
   //\r
   // Go through page table and set several page table entries to absent or execute-disable.\r
   //\r
   DEBUG ((EFI_D_INFO, "Patch page table start ...\n"));\r
-  for (Level1 = 0; Level1 < NumberOfPml4Entries; Level1++) {\r
+  for (Pml4Index = 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) {\r
     if (sizeof (UINTN) == sizeof (UINT64)) {\r
-      if ((Pml4[Level1] & IA32_PG_P) == 0) {\r
+      if ((Pml4[Pml4Index] & IA32_PG_P) == 0) {\r
         //\r
-        // If Pml4 entry does not exist, skip it\r
+        // If PML4 entry does not exist, skip it\r
         //\r
         continue;\r
       }\r
-      Pde = (UINT64 *)(UINTN)(Pml4[Level1] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
+      Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
     } else {\r
-      Pde = (UINT64*)(UINTN)mSmmProfileCr3;\r
+      Pdpt = (UINT64*)(UINTN)mSmmProfileCr3;\r
     }\r
-    for (Level2 = 0; Level2 < NumberOfPdpEntries; Level2++, Pde++) {\r
-      if ((*Pde & IA32_PG_P) == 0) {\r
+    for (PdptIndex = 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, Pdpt++) {\r
+      if ((*Pdpt & IA32_PG_P) == 0) {\r
         //\r
-        // If PDE entry does not exist, skip it\r
+        // If PDPT entry does not exist, skip it\r
         //\r
         continue;\r
       }\r
-      if ((*Pde & IA32_PG_PS) != 0) {\r
+      if ((*Pdpt & IA32_PG_PS) != 0) {\r
         //\r
         // This is 1G entry, set NX bit and skip it\r
         //\r
         if (mXdSupported) {\r
-          *Pde = *Pde | IA32_PG_NX;\r
+          *Pdpt = *Pdpt | IA32_PG_NX;\r
         }\r
         continue;\r
       }\r
-      Pte = (UINT64 *)(UINTN)(*Pde & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
-      if (Pte == 0) {\r
+      Pd = (UINT64 *)(UINTN)(*Pdpt & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
+      if (Pd == 0) {\r
         continue;\r
       }\r
-      for (Level3 = 0; Level3 < SIZE_4KB / sizeof (*Pte); Level3++, Pte++) {\r
-        if ((*Pte & IA32_PG_P) == 0) {\r
+      for (PdIndex = 0; PdIndex < SIZE_4KB / sizeof (*Pd); PdIndex++, Pd++) {\r
+        if ((*Pd & IA32_PG_P) == 0) {\r
           //\r
-          // If PTE entry does not exist, skip it\r
+          // If PD entry does not exist, skip it\r
           //\r
           continue;\r
         }\r
-        Address = (((Level2 << 9) + Level3) << 21);\r
+        Address = (((PdptIndex << 9) + PdIndex) << 21);\r
 \r
-        if ((*Pte & IA32_PG_PS) != 0) {\r
+        if ((*Pd & IA32_PG_PS) != 0) {\r
           // 2MB page\r
 \r
           if (!IsAddressValid (Address, &Nx)) {\r
             //\r
             // Patch to remove Present flag and RW flag\r
             //\r
-            *Pte = *Pte & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r
+            *Pd = *Pd & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r
           }\r
           if (Nx && mXdSupported) {\r
-            *Pte = *Pte | IA32_PG_NX;\r
+            *Pd = *Pd | IA32_PG_NX;\r
           }\r
         } else {\r
           // 4KB page\r
-          Pt = (UINT64 *)(UINTN)(*Pte & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
+          Pt = (UINT64 *)(UINTN)(*Pd & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
           if (Pt == 0) {\r
             continue;\r
           }\r
-          for (Level4 = 0; Level4 < SIZE_4KB / sizeof(*Pt); Level4++, Pt++) {\r
+          for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof(*Pt); PtIndex++, Pt++) {\r
             if (!IsAddressValid (Address, &Nx)) {\r
               *Pt = *Pt & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r
             }\r
@@ -702,9 +702,9 @@ InitPaging (
             Address += SIZE_4KB;\r
           } // end for PT\r
         } // end if PS\r
-      } // end for PTE\r
-    } // end for PDE\r
-  }\r
+      } // end for PD\r
+    } // end for PDPT\r
+  } // end for PML4\r
 \r
   //\r
   // Flush TLB\r