ArmPkg: apply Cortex-A57 errata

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c
index 135bd6b86d74f7cf78df530a10f0472c1d7f5c0c..3d39acd50c044e63f15220aaa69963cda940bd9c 100644 (file)
--- a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c
+++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c
@@ -40,12 +40,15 @@ ArmCpuSetup (
   }\r
 \r
   //\r
-  // If CPU is CortexA57 r0p0 apply Errata: 806969\r
+  // If CPU is CortexA57 r0p0 apply Errata workarounds\r
   //\r
   if ((ArmReadMidr () & ((ARM_CPU_TYPE_MASK << 4) | ARM_CPU_REV_MASK)) ==\r
                          ((ARM_CPU_TYPE_A57 << 4) | ARM_CPU_REV(0,0))) {\r
-    // DisableLoadStoreWB\r
-    ArmSetCpuActlrBit (1ULL << 49);\r
+\r
+    // Errata 806969: DisableLoadStoreWB (1ULL << 49)\r
+    // Errata 813420: Execute Data Cache clean as Data Cache clean/invalidate  (1ULL << 44)\r
+    // Errata 814670: disable DMB nullification (1ULL << 58)\r
+    ArmSetCpuActlrBit ( (1ULL << 49) | (1ULL << 44) | (1ULL << 58) );\r
   }\r
 }\r
 \r