UefiCpuPkg/PiSmmCpuDxeSmm: Save SMM ranges info into global variables

v2:
  Add #define SMRR_MAX_ADDRESS to clarify SMRR requirement.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index d06148263c8e565a2081f044a0234ef6df1873b2..47cba100e7653e23311993a62d837f65068c4320 100755 (executable)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -108,6 +108,12 @@ UINT64                   mAddressEncMask = 0;
 //\r
 SPIN_LOCK                *mConfigSmmCodeAccessCheckLock = NULL;\r
 \r
+//\r
+// Saved SMM ranges information\r
+//\r
+EFI_SMRAM_DESCRIPTOR     *mSmmCpuSmramRanges;\r
+UINTN                    mSmmCpuSmramRangeCount;\r
+\r
 /**\r
   Initialize IDT to setup exception handlers for SMM.\r
 \r
@@ -971,8 +977,6 @@ FindSmramInfo (
   UINTN                             Size;\r
   EFI_SMM_ACCESS2_PROTOCOL          *SmmAccess;\r
   EFI_SMRAM_DESCRIPTOR              *CurrentSmramRange;\r
-  EFI_SMRAM_DESCRIPTOR              *SmramRanges;\r
-  UINTN                             SmramRangeCount;\r
   UINTN                             Index;\r
   UINT64                            MaxSize;\r
   BOOLEAN                           Found;\r
@@ -990,31 +994,31 @@ FindSmramInfo (
   Status = SmmAccess->GetCapabilities (SmmAccess, &Size, NULL);\r
   ASSERT (Status == EFI_BUFFER_TOO_SMALL);\r
 \r
-  SmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size);\r
-  ASSERT (SmramRanges != NULL);\r
+  mSmmCpuSmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size);\r
+  ASSERT (mSmmCpuSmramRanges != NULL);\r
 \r
-  Status = SmmAccess->GetCapabilities (SmmAccess, &Size, SmramRanges);\r
+  Status = SmmAccess->GetCapabilities (SmmAccess, &Size, mSmmCpuSmramRanges);\r
   ASSERT_EFI_ERROR (Status);\r
 \r
-  SmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR);\r
+  mSmmCpuSmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR);\r
 \r
   //\r
   // Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size\r
   //\r
   CurrentSmramRange = NULL;\r
-  for (Index = 0, MaxSize = SIZE_256KB - EFI_PAGE_SIZE; Index < SmramRangeCount; Index++) {\r
+  for (Index = 0, MaxSize = SIZE_256KB - EFI_PAGE_SIZE; Index < mSmmCpuSmramRangeCount; Index++) {\r
     //\r
     // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization\r
     //\r
-    if ((SmramRanges[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) {\r
+    if ((mSmmCpuSmramRanges[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) {\r
       continue;\r
     }\r
 \r
-    if (SmramRanges[Index].CpuStart >= BASE_1MB) {\r
-      if ((SmramRanges[Index].CpuStart + SmramRanges[Index].PhysicalSize) <= BASE_4GB) {\r
-        if (SmramRanges[Index].PhysicalSize >= MaxSize) {\r
-          MaxSize = SmramRanges[Index].PhysicalSize;\r
-          CurrentSmramRange = &SmramRanges[Index];\r
+    if (mSmmCpuSmramRanges[Index].CpuStart >= BASE_1MB) {\r
+      if ((mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize) <= SMRR_MAX_ADDRESS) {\r
+        if (mSmmCpuSmramRanges[Index].PhysicalSize >= MaxSize) {\r
+          MaxSize = mSmmCpuSmramRanges[Index].PhysicalSize;\r
+          CurrentSmramRange = &mSmmCpuSmramRanges[Index];\r
         }\r
       }\r
     }\r
@@ -1027,19 +1031,19 @@ FindSmramInfo (
 \r
   do {\r
     Found = FALSE;\r
-    for (Index = 0; Index < SmramRangeCount; Index++) {\r
-      if (SmramRanges[Index].CpuStart < *SmrrBase && *SmrrBase == (SmramRanges[Index].CpuStart + SmramRanges[Index].PhysicalSize)) {\r
-        *SmrrBase = (UINT32)SmramRanges[Index].CpuStart;\r
-        *SmrrSize = (UINT32)(*SmrrSize + SmramRanges[Index].PhysicalSize);\r
+    for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {\r
+      if (mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase &&\r
+          *SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize)) {\r
+        *SmrrBase = (UINT32)mSmmCpuSmramRanges[Index].CpuStart;\r
+        *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);\r
         Found = TRUE;\r
-      } else if ((*SmrrBase + *SmrrSize) == SmramRanges[Index].CpuStart && SmramRanges[Index].PhysicalSize > 0) {\r
-        *SmrrSize = (UINT32)(*SmrrSize + SmramRanges[Index].PhysicalSize);\r
+      } else if ((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart && mSmmCpuSmramRanges[Index].PhysicalSize > 0) {\r
+        *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);\r
         Found = TRUE;\r
       }\r
     }\r
   } while (Found);\r
 \r
-  FreePool (SmramRanges);\r
   DEBUG ((EFI_D_INFO, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase, *SmrrSize));\r
 }\r
 \r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index 71af2f17759560c3a4a24bcfb628bf669864e8d2..fc9b06e972ae1bcd9111eadef4c6b6930c8bf15b 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -1,7 +1,7 @@
 /** @file\r
 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r
 \r
-Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
 \r
 This program and the accompanying materials\r
@@ -105,6 +105,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull\r
 #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r
 \r
+#define SMRR_MAX_ADDRESS       BASE_4GB\r
+\r
 typedef enum {\r
   PageNone,\r
   Page4K,\r
@@ -415,6 +417,8 @@ extern UINTN                               mSemaphoreSize;
 extern SPIN_LOCK                           *mPFLock;\r
 extern SPIN_LOCK                           *mConfigSmmCodeAccessCheckLock;\r
 extern SPIN_LOCK                           *mMemoryMappedLock;\r
+extern EFI_SMRAM_DESCRIPTOR                *mSmmCpuSmramRanges;\r
+extern UINTN                               mSmmCpuSmramRangeCount;\r
 \r
 //\r
 // Copy of the PcdPteMemoryEncryptionAddressOrMask\r