Support ResetSystem Runtime call using PSCI calls\r
\r
Note: A similar library is implemented in\r
- ArmPlatformPkg/ArmVirtualizationPkg/Library/ArmVirtualizationPsciResetSystemLib\r
+ ArmVirtPkg/Library/ArmVirtualizationPsciResetSystemLib\r
So similar issues might exist in this implementation too.\r
\r
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
- Copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>\r
+ Copyright (c) 2013-2015, ARM Ltd. All rights reserved.<BR>\r
Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
+++ /dev/null
-#\r
-# Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
-# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-\r
-[Defines]\r
- DEFINE DEBUG_PRINT_ERROR_LEVEL = 0x8000004F\r
-\r
-[LibraryClasses.common]\r
-!if $(TARGET) == RELEASE\r
- DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf\r
- UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf\r
-!else\r
- DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
- UncachedMemoryAllocationLib|ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf\r
-!endif\r
- DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf\r
-\r
- BaseLib|MdePkg/Library/BaseLib/BaseLib.inf\r
- SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf\r
- PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf\r
- PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf\r
- PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
- PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
- IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf\r
- UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf\r
- CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf\r
-\r
- UefiLib|MdePkg/Library/UefiLib/UefiLib.inf\r
- HobLib|ArmPlatformPkg/ArmVirtualizationPkg/Library/ArmVirtualizationDxeHobLib/ArmVirtualizationDxeHobLib.inf\r
- UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
- DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
- UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf\r
- DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf\r
- UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf\r
- UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf\r
- HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf\r
- UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf\r
-\r
- UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf\r
- OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf\r
-\r
- #\r
- # Allow dynamic PCDs\r
- #\r
- PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
-\r
- # 1/123 faster than Stm or Vstm version\r
- #BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf\r
- BaseMemoryLib|ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf\r
-\r
- # Networking Requirements\r
- NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf\r
- DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf\r
- UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf\r
- IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf\r
-\r
- # ARM Architectural Libraries\r
- CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf\r
- DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf\r
- CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf\r
- ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf\r
- DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf\r
- ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf\r
- ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf\r
- ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf\r
- ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf\r
- ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.inf\r
-\r
- PlatformPeiLib|ArmPlatformPkg/ArmVirtualizationPkg/Library/PlatformPeiLib/PlatformPeiLib.inf\r
- MemoryInitPeiLib|ArmPlatformPkg/ArmVirtualizationPkg/Library/ArmVirtualizationMemoryInitPeiLib/ArmVirtualizationMemoryInitPeiLib.inf\r
- EfiResetSystemLib|ArmPlatformPkg/ArmVirtualizationPkg/Library/ArmVirtualizationPsciResetSystemLib/ArmVirtualizationPsciResetSystemLib.inf\r
-\r
- # ARM PL031 RTC Driver\r
- RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf\r
- # ARM PL011 UART Driver\r
- PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf\r
- SerialPortLib|ArmPlatformPkg/ArmVirtualizationPkg/Library/FdtPL011SerialPortLib/FdtPL011SerialPortLib.inf\r
- SerialPortExtLib|EmbeddedPkg/Library/SerialPortExtLibNull/SerialPortExtLibNull.inf\r
-\r
- #\r
- # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window\r
- # in the debugger will show load and unload commands for symbols. You can cut and paste this\r
- # into the command window to load symbols. We should be able to use a script to do this, but\r
- # the version of RVD I have does not support scripts accessing system memory.\r
- #\r
- #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf\r
- PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf\r
- #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf\r
-\r
- DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf\r
- DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf\r
-\r
- # BDS Libraries\r
- BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf\r
- FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf\r
-\r
- # PCI Libraries\r
- PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf\r
- PciExpressLib|ArmPlatformPkg/ArmVirtualizationPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpressLib.inf\r
-\r
- # USB Libraries\r
- UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf\r
-\r
- XenIoMmioLib|OvmfPkg/Library/XenIoMmioLib/XenIoMmioLib.inf\r
-\r
- #\r
- # Secure Boot dependencies\r
- #\r
-!if $(SECURE_BOOT_ENABLE) == TRUE\r
- IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf\r
- OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf\r
- TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf\r
- BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf\r
-\r
- # re-use the UserPhysicalPresent() dummy implementation from the ovmf tree\r
- PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf\r
-!endif\r
-\r
-[LibraryClasses.common.SEC]\r
- PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
- ArmPlatformSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf\r
- ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Sec/SecArmPlatformGlobalVariableLib.inf\r
-\r
- DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf\r
- DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf\r
- SerialPortLib|ArmPlatformPkg/ArmVirtualizationPkg/Library/FdtPL011SerialPortLib/EarlyFdtPL011SerialPortLib.inf\r
- HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
- PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf\r
- PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf\r
- MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
-\r
-[LibraryClasses.common.PEI_CORE]\r
- PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf\r
- HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
- PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf\r
- MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
- PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf\r
- PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf\r
- ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf\r
- OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf\r
- PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
- UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf\r
- ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf\r
-\r
- ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.inf\r
- PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf\r
- SerialPortLib|ArmPlatformPkg/ArmVirtualizationPkg/Library/FdtPL011SerialPortLib/EarlyFdtPL011SerialPortLib.inf\r
-\r
-[LibraryClasses.common.PEIM]\r
- PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf\r
- HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
- PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf\r
- MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
- PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf\r
- PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf\r
- ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf\r
- OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf\r
- PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
- PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf\r
- UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf\r
- ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf\r
-\r
- ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.inf\r
- PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf\r
- SerialPortLib|ArmPlatformPkg/ArmVirtualizationPkg/Library/FdtPL011SerialPortLib/EarlyFdtPL011SerialPortLib.inf\r
-\r
-[LibraryClasses.common.DXE_CORE]\r
- HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf\r
- MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf\r
- DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf\r
- ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
- ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
- UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf\r
- DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf\r
- PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf\r
-\r
-[LibraryClasses.common.DXE_DRIVER]\r
- ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
- DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf\r
- SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf\r
- PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf\r
- MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
- ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Dxe/DxeArmPlatformGlobalVariableLib.inf\r
-\r
-[LibraryClasses.common.UEFI_APPLICATION]\r
- UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf\r
- PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf\r
- MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
- HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf\r
-\r
-[LibraryClasses.common.UEFI_DRIVER]\r
- ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
- UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf\r
- ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
- PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf\r
- DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf\r
- MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
-\r
-[LibraryClasses.common.DXE_RUNTIME_DRIVER]\r
- MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
- ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
- CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf\r
-\r
-!if $(SECURE_BOOT_ENABLE) == TRUE\r
- BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf\r
-!endif\r
-\r
-[LibraryClasses.ARM]\r
- #\r
- # It is not possible to prevent the ARM compiler for generic intrinsic functions.\r
- # This library provides the instrinsic functions generate by a given compiler.\r
- # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.\r
- #\r
- NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf\r
-\r
- # Add support for GCC stack protector\r
- NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf\r
-\r
-[LibraryClasses.AARCH64]\r
- NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf\r
-\r
-\r
-[BuildOptions]\r
- RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG\r
-\r
- GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG\r
-\r
-################################################################################\r
-#\r
-# Pcd Section - list of all EDK II PCD Entries defined by this Platform\r
-#\r
-################################################################################\r
-\r
-[PcdsFeatureFlag.common]\r
- gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE\r
- gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE\r
- gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE\r
- gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE\r
-\r
- #\r
- # Control what commands are supported from the UI\r
- # Turn these on and off to add features or save size\r
- #\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE\r
-\r
- gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE\r
-\r
- # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress\r
- gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE\r
-\r
- gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE\r
-\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE\r
-\r
-[PcdsFixedAtBuild.common]\r
- gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Virtualization Platform"\r
-\r
- gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000\r
- gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000\r
- gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000\r
- gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000\r
- gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF\r
- gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1\r
- gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0\r
- gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320\r
-\r
- # DEBUG_ASSERT_ENABLED 0x01\r
- # DEBUG_PRINT_ENABLED 0x02\r
- # DEBUG_CODE_ENABLED 0x04\r
- # CLEAR_MEMORY_ENABLED 0x08\r
- # ASSERT_BREAKPOINT_ENABLED 0x10\r
- # ASSERT_DEADLOOP_ENABLED 0x20\r
-!if $(TARGET) == RELEASE\r
- gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21\r
-!else\r
- gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f\r
-!endif\r
-\r
- # DEBUG_INIT 0x00000001 // Initialization\r
- # DEBUG_WARN 0x00000002 // Warnings\r
- # DEBUG_LOAD 0x00000004 // Load events\r
- # DEBUG_FS 0x00000008 // EFI File system\r
- # DEBUG_POOL 0x00000010 // Alloc & Free's\r
- # DEBUG_PAGE 0x00000020 // Alloc & Free's\r
- # DEBUG_INFO 0x00000040 // Informational debug messages\r
- # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers\r
- # DEBUG_VARIABLE 0x00000100 // Variable\r
- # DEBUG_BM 0x00000400 // Boot Manager\r
- # DEBUG_BLKIO 0x00001000 // BlkIo Driver\r
- # DEBUG_NET 0x00004000 // SNI Driver\r
- # DEBUG_UNDI 0x00010000 // UNDI Driver\r
- # DEBUG_LOADFILE 0x00020000 // UNDI Driver\r
- # DEBUG_EVENT 0x00080000 // Event messages\r
- # DEBUG_GCD 0x00100000 // Global Coherency Database changes\r
- # DEBUG_CACHE 0x00200000 // Memory range cachability changes\r
- # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may\r
- # // significantly impact boot performance\r
- # DEBUG_ERROR 0x80000000 // Error\r
- gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|$(DEBUG_PRINT_ERROR_LEVEL)\r
-\r
- gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07\r
-\r
- #\r
- # Optional feature to help prevent EFI memory map fragments\r
- # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob\r
- # Values are in EFI Pages (4K). DXE Core will make sure that\r
- # at least this much of each type of memory can be allocated\r
- # from a single memory range. This way you only end up with\r
- # maximum of two fragements for each type in the memory map\r
- # (the memory used, and the free memory that was prereserved\r
- # but not used).\r
- #\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|50\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|20\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0\r
-\r
- #\r
- # ARM Pcds\r
- #\r
- gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000000000000\r
-\r
-!if $(SECURE_BOOT_ENABLE) == TRUE\r
- # override the default values from SecurityPkg to ensure images from all sources are verified in secure boot\r
- gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04\r
- gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04\r
- gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04\r
-!endif\r
-\r
-[Components.common]\r
- #\r
- # Networking stack\r
- #\r
- MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf\r
- MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf\r
- MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf\r
- MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf\r
- MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf\r
- MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf\r
- MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf\r
- MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf\r
- MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf\r
- MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf\r
- MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf\r
- MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf\r
-\r
- #\r
- # UEFI application (Shell Embedded Boot Loader)\r
- #\r
- ShellPkg/Application/Shell/Shell.inf {\r
- <LibraryClasses>\r
- ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf\r
- NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf\r
- NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf\r
- NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf\r
- NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf\r
- NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf\r
- NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf\r
- NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf\r
- HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf\r
- ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf\r
- FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf\r
- SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf\r
- PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf\r
- BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf\r
-\r
- <PcdsFixedAtBuild>\r
- gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF\r
- gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE\r
- gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000\r
- }\r
+++ /dev/null
-#/** @file\r
-#\r
-# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#**/\r
-\r
-[Defines]\r
- DEC_SPECIFICATION = 0x00010005\r
- PACKAGE_NAME = ArmVirtualizationPkg\r
- PACKAGE_GUID = A0B31216-508E-4025-BEAB-56D836C66F0A\r
- PACKAGE_VERSION = 0.1\r
-\r
-################################################################################\r
-#\r
-# Include Section - list of Include Paths that are provided by this package.\r
-# Comments are used for Keywords and Module Types.\r
-#\r
-# Supported Module Types:\r
-# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
-#\r
-################################################################################\r
-[Includes.common]\r
- Include # Root include for the package\r
-\r
-[Guids.common]\r
- gArmVirtualizationTokenSpaceGuid = { 0x0B6F5CA7, 0x4F53, 0x445A, { 0xB7, 0x6E, 0x2E, 0x36, 0x5B, 0x80, 0x63, 0x66 } }\r
- gEarlyPL011BaseAddressGuid = { 0xB199DEA9, 0xFD5C, 0x4A84, { 0x80, 0x82, 0x2F, 0x41, 0x70, 0x78, 0x03, 0x05 } }\r
-\r
-[PcdsFixedAtBuild, PcdsPatchableInModule]\r
- #\r
- # This is the physical address where the device tree is expected to be stored\r
- # upon first entry into UEFI. This needs to be a FixedAtBuild PCD, so that we\r
- # can do a first pass over the device tree in the SEC phase to discover the\r
- # UART base address.\r
- #\r
- gArmVirtualizationTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x0|UINT64|0x00000001\r
-\r
- #\r
- # Padding in bytes to add to the device tree allocation, so that the DTB can\r
- # be modified in place (default: 256 bytes)\r
- #\r
- gArmVirtualizationTokenSpaceGuid.PcdDeviceTreeAllocationPadding|256|UINT32|0x00000002\r
-\r
-[PcdsDynamic, PcdsFixedAtBuild]\r
- #\r
- # ARM PSCI function invocations can be done either through hypervisor\r
- # calls (HVC) or secure monitor calls (SMC).\r
- # PcdArmPsciMethod == 1 : use HVC\r
- # PcdArmPsciMethod == 2 : use SMC\r
- #\r
- gArmVirtualizationTokenSpaceGuid.PcdArmPsciMethod|0|UINT32|0x00000003\r
-\r
- gArmVirtualizationTokenSpaceGuid.PcdFwCfgSelectorAddress|0x0|UINT64|0x00000004\r
- gArmVirtualizationTokenSpaceGuid.PcdFwCfgDataAddress|0x0|UINT64|0x00000005\r
-\r
-[PcdsFeatureFlag]\r
- #\r
- # "Map PCI MMIO as Cached"\r
- #\r
- # Due to the way Stage1 and Stage2 mappings are combined on Aarch64, and\r
- # because KVM -- for the time being -- does not try to interfere with the\r
- # Stage1 mappings, we must not set EFI_MEMORY_UC for emulated PCI MMIO\r
- # regions.\r
- #\r
- # EFI_MEMORY_UC is mapped to Device-nGnRnE, and that Stage1 attribute would\r
- # direct guest writes to host DRAM immediately, bypassing the cache\r
- # regardless of Stage2 attributes. However, QEMU's reads of the same range\r
- # can easily be served from the (stale) CPU cache.\r
- #\r
- # Setting this PCD to TRUE will use EFI_MEMORY_WB for mapping PCI MMIO\r
- # regions, which ensures that guest writes to such regions go through the CPU\r
- # cache. Strictly speaking this is wrong, but it is needed as a temporary\r
- # workaround for emulated PCI devices. Setting the PCD to FALSE results in\r
- # the theoretically correct EFI_MEMORY_UC mapping, and should be the long\r
- # term choice, especially with assigned devices.\r
- #\r
- # The default is to turn off the kludge; DSC's can selectively enable it.\r
- #\r
- gArmVirtualizationTokenSpaceGuid.PcdKludgeMapPciMmioAsCached|FALSE|BOOLEAN|0x00000006\r
+++ /dev/null
-#\r
-# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-\r
-################################################################################\r
-#\r
-# Defines Section - statements that will be processed to create a Makefile.\r
-#\r
-################################################################################\r
-[Defines]\r
- PLATFORM_NAME = ArmVirtualizationQemu\r
- PLATFORM_GUID = 37d7e986-f7e9-45c2-8067-e371421a626c\r
- PLATFORM_VERSION = 0.1\r
- DSC_SPECIFICATION = 0x00010005\r
- OUTPUT_DIRECTORY = Build/ArmVirtualizationQemu-$(ARCH)\r
- SUPPORTED_ARCHITECTURES = AARCH64|ARM\r
- BUILD_TARGETS = DEBUG|RELEASE\r
- SKUID_IDENTIFIER = DEFAULT\r
- FLASH_DEFINITION = ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationQemu.fdf\r
-\r
- #\r
- # Defines for default states. These can be changed on the command line.\r
- # -D FLAG=VALUE\r
- #\r
- DEFINE SECURE_BOOT_ENABLE = FALSE\r
-\r
-!include ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualization.dsc.inc\r
-\r
-[LibraryClasses.AARCH64]\r
- ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf\r
- ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexAEMv8Lib/ArmCortexAEMv8Lib.inf\r
-\r
-[LibraryClasses.ARM]\r
- ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
- ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf\r
-\r
-[LibraryClasses.common]\r
- # Virtio Support\r
- VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf\r
- VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDeviceLib.inf\r
- QemuFwCfgLib|ArmPlatformPkg/ArmVirtualizationPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf\r
-\r
- ArmPlatformLib|ArmPlatformPkg/ArmVirtualizationPkg/Library/ArmVirtualizationPlatformLib/ArmVirtualizationPlatformLib.inf\r
- ArmPlatformSysConfigLib|ArmPlatformPkg/Library/ArmPlatformSysConfigLibNull/ArmPlatformSysConfigLibNull.inf\r
-\r
- TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf\r
- NorFlashPlatformLib|ArmPlatformPkg/ArmVirtualizationPkg/Library/NorFlashQemuLib/NorFlashQemuLib.inf\r
-\r
-!ifdef INTEL_BDS\r
- CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf\r
- GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf\r
- PlatformBdsLib|ArmPlatformPkg/ArmVirtualizationPkg/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf\r
- CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf\r
- QemuBootOrderLib|OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.inf\r
-!endif\r
-\r
-[LibraryClasses.common.UEFI_DRIVER]\r
- UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf\r
-\r
-[LibraryClasses.AARCH64.SEC]\r
- ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf\r
-\r
-[LibraryClasses.ARM.SEC]\r
- ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf\r
-\r
-[BuildOptions]\r
- RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A15 -I$(WORKSPACE)/ArmPlatformPkg/ArmVirtualizationPkg/Include\r
- GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a15 -I$(WORKSPACE)/ArmPlatformPkg/ArmVirtualizationPkg/Include\r
- *_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/ArmVirtualizationPkg/Include\r
-\r
-\r
-################################################################################\r
-#\r
-# Pcd Section - list of all EDK II PCD Entries defined by this Platform\r
-#\r
-################################################################################\r
-\r
-[PcdsFeatureFlag.common]\r
- gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE\r
- gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|TRUE\r
-\r
- ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.\r
- # It could be set FALSE to save size.\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE\r
-\r
- # Activate KVM workaround for now.\r
- gArmVirtualizationTokenSpaceGuid.PcdKludgeMapPciMmioAsCached|TRUE\r
-\r
-[PcdsFixedAtBuild.common]\r
- gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"QEMU"\r
-\r
- gArmPlatformTokenSpaceGuid.PcdCoreCount|1\r
-!if $(ARCH) == AARCH64\r
- gArmTokenSpaceGuid.PcdVFPEnabled|1\r
-!endif\r
-\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x4007c000\r
- gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000\r
-\r
- # Size of the region used by UEFI in permanent memory (Reserved 64MB)\r
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000\r
-\r
- #\r
- # ARM Pcds\r
- #\r
- gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000\r
-\r
- ## Trustzone enable (to make the transition from EL3 to EL2 in ArmPlatformPkg/Sec)\r
- gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE\r
-\r
- #\r
- # ARM PrimeCell\r
- #\r
-\r
- ## PL011 - Serial Terminal\r
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400\r
-\r
- #\r
- # ARM OS Loader\r
- #\r
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux (EFI stub) on virtio31:hd0:part0"\r
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(837DCA9E-E874-4D82-B29A-23FE0E23D1E2,003E000A00000000)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/Image"\r
- gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"root=/dev/vda2 console=ttyAMA0 earlycon uefi_debug"\r
- gArmPlatformTokenSpaceGuid.PcdDefaultBootType|0\r
-\r
- #\r
- # Settings for ARM BDS -- use the serial console (ConIn & ConOut).\r
- #\r
- gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenVt100()"\r
- gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenVt100()"\r
- gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3\r
-\r
- #\r
- # ARM Virtual Architectural Timer -- fetch frequency from QEMU (TCG) or KVM\r
- #\r
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0\r
-\r
- #\r
- # NV Storage PCDs. Use base of 0x04000000 for NOR1\r
- #\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x04000000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00040000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x04040000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00040000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x04080000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00040000\r
-\r
- # System Memory Base -- fixed at 0x4000_0000\r
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x40000000\r
-\r
- # initial location of the device tree blob passed by QEMU -- base of DRAM\r
- gArmVirtualizationTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x40000000\r
-\r
-!ifdef INTEL_BDS\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE\r
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }\r
-!endif\r
-\r
- #\r
- # The maximum physical I/O addressability of the processor, set with\r
- # BuildCpuHob().\r
- #\r
- gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16\r
-\r
-[PcdsDynamicDefault.common]\r
- ## If TRUE, OvmfPkg/AcpiPlatformDxe will not wait for PCI\r
- # enumeration to complete before installing ACPI tables.\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE\r
-\r
- # System Memory Size -- 1 MB initially, actual size will be fetched from DT\r
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x00100000\r
-\r
- gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|0x0\r
- gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|0x0\r
- gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|0x0\r
- gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|0x0\r
-\r
- #\r
- # ARM General Interrupt Controller\r
- #\r
- gArmTokenSpaceGuid.PcdGicDistributorBase|0x0\r
- gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x0\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x0\r
-\r
- ## PL031 RealTimeClock\r
- gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0\r
-\r
- gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0\r
- gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0\r
- gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0\r
- gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0\r
- gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0\r
- gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0\r
- gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0\r
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x0\r
-\r
- gArmVirtualizationTokenSpaceGuid.PcdArmPsciMethod|0\r
-\r
- gArmVirtualizationTokenSpaceGuid.PcdFwCfgSelectorAddress|0x0\r
- gArmVirtualizationTokenSpaceGuid.PcdFwCfgDataAddress|0x0\r
-\r
- #\r
- # Set video resolution for boot options and for text setup.\r
- # PlatformDxe can set the former at runtime.\r
- #\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480\r
-\r
-################################################################################\r
-#\r
-# Components Section - list of all EDK II Modules needed by this Platform\r
-#\r
-################################################################################\r
-[Components.common]\r
- #\r
- # PEI Phase modules\r
- #\r
- ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf {\r
- <LibraryClasses>\r
- ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.inf\r
- }\r
- MdeModulePkg/Core/Pei/PeiMain.inf\r
- MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
- ArmPlatformPkg/PlatformPei/PlatformPeim.inf\r
- ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf\r
- ArmPkg/Drivers/CpuPei/CpuPei.inf\r
-\r
-!if $(SECURE_BOOT_ENABLE) == TRUE\r
- SecurityPkg/VariableAuthenticated/Pei/VariablePei.inf {\r
- <LibraryClasses>\r
- BaseCryptLib|CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf\r
- }\r
-!else\r
- MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
-!endif\r
-\r
- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {\r
- <LibraryClasses>\r
- NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf\r
- }\r
-\r
- #\r
- # DXE\r
- #\r
- MdeModulePkg/Core/Dxe/DxeMain.inf {\r
- <LibraryClasses>\r
- NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf\r
- }\r
- MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
-\r
- #\r
- # Architectural Protocols\r
- #\r
- ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
- MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
-!if $(SECURE_BOOT_ENABLE) == TRUE\r
- MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {\r
- <LibraryClasses>\r
- NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf\r
- }\r
- SecurityPkg/VariableAuthenticated/RuntimeDxe/VariableRuntimeDxe.inf {\r
- <LibraryClasses>\r
- BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf\r
- OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf\r
- }\r
- SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf\r
-!else\r
- MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
- MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
-!endif\r
- MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
- MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
- MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
- EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
- EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
- EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
-\r
- MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
- MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
- MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
- MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
- EmbeddedPkg/SerialDxe/SerialDxe.inf\r
-\r
- MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
-\r
- ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
- ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
-!if $(SECURE_BOOT_ENABLE) == TRUE\r
- ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashAuthenticatedDxe.inf\r
-!else\r
- ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
-!endif\r
- MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
-\r
- #\r
- # Platform Driver\r
- #\r
- ArmPlatformPkg/ArmVirtualizationPkg/VirtFdtDxe/VirtFdtDxe.inf\r
- OvmfPkg/VirtioBlkDxe/VirtioBlk.inf\r
- OvmfPkg/VirtioScsiDxe/VirtioScsi.inf\r
- OvmfPkg/VirtioNetDxe/VirtioNet.inf\r
-\r
- #\r
- # FAT filesystem + GPT/MBR partitioning\r
- #\r
- MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
- MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
- MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
-\r
- #\r
- # Bds\r
- #\r
- MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
-!ifdef INTEL_BDS\r
- MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf\r
- MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
- IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf\r
-!else\r
- ArmPlatformPkg/Bds/Bds.inf\r
-!endif\r
-\r
- #\r
- # SCSI Bus and Disk Driver\r
- #\r
- MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf\r
- MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf\r
-\r
- #\r
- # ACPI Support\r
- #\r
- MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf\r
- OvmfPkg/AcpiPlatformDxe/QemuFwCfgAcpiPlatformDxe.inf\r
-\r
- #\r
- # PCI support\r
- #\r
- ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf\r
- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf\r
- OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf\r
-\r
- #\r
- # Video support\r
- #\r
- OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf {\r
- <LibraryClasses>\r
- BltLib|OptionRomPkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf\r
- }\r
- OvmfPkg/PlatformDxe/Platform.inf\r
-\r
- #\r
- # USB Support\r
- #\r
- MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf\r
- MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf\r
- MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf\r
- MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf\r
- MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf\r
+++ /dev/null
-#\r
-# Copyright (c) 2011, 2013, ARM Limited. All rights reserved.\r
-# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-\r
-################################################################################\r
-#\r
-# FD Section\r
-# The [FD] Section is made up of the definition statements and a\r
-# description of what goes into the Flash Device Image. Each FD section\r
-# defines one flash "device" image. A flash device image may be one of\r
-# the following: Removable media bootable image (like a boot floppy\r
-# image,) an Option ROM image (that would be "flashed" into an add-in\r
-# card,) a System "Flash" image (that would be burned into a system's\r
-# flash) or an Update ("Capsule") image that will be used to update and\r
-# existing system flash.\r
-#\r
-################################################################################\r
-\r
-[FD.QEMU_EFI]\r
-BaseAddress = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress # QEMU assigns 0 - 0x8000000 for a BootROM\r
-Size = 0x00200000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device\r
-ErasePolarity = 1\r
-\r
-# This one is tricky, it must be: BlockSize * NumBlocks = Size\r
-BlockSize = 0x00001000\r
-NumBlocks = 0x200\r
-\r
-################################################################################\r
-#\r
-# Following are lists of FD Region layout which correspond to the locations of different\r
-# images within the flash device.\r
-#\r
-# Regions must be defined in ascending order and may not overlap.\r
-#\r
-# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by\r
-# the pipe "|" character, followed by the size of the region, also in hex with the leading\r
-# "0x" characters. Like:\r
-# Offset|Size\r
-# PcdOffsetCName|PcdSizeCName\r
-# RegionType <FV, DATA, or FILE>\r
-#\r
-################################################################################\r
-\r
-#\r
-# UEFI has trouble dealing with FVs that reside at physical address 0x0.\r
-# So instead, put a hardcoded 'jump to 0x1000' at offset 0x0, and put the\r
-# real FV at offset 0x1000\r
-#\r
-0x00000000|0x00001000\r
-DATA = {\r
-!if $(ARCH) == AARCH64\r
- 0x00, 0x04, 0x00, 0x14 # 'b 0x1000' in AArch64 ASM\r
-!else\r
- 0xfe, 0x03, 0x00, 0xea # 'b 0x1000' in AArch32 ASM\r
-!endif\r
-}\r
-\r
-0x00001000|0x001ff000\r
-gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize\r
-FV = FVMAIN_COMPACT\r
-\r
-\r
-################################################################################\r
-#\r
-# FV Section\r
-#\r
-# [FV] section is used to define what components or modules are placed within a flash\r
-# device file. This section also defines order the components and modules are positioned\r
-# within the image. The [FV] section consists of define statements, set statements and\r
-# module statements.\r
-#\r
-################################################################################\r
-\r
-[FV.FvMain]\r
-BlockSize = 0x40\r
-NumBlocks = 0 # This FV gets compressed so make it just big enough\r
-FvAlignment = 16 # FV alignment and FV attributes setting.\r
-ERASE_POLARITY = 1\r
-MEMORY_MAPPED = TRUE\r
-STICKY_WRITE = TRUE\r
-LOCK_CAP = TRUE\r
-LOCK_STATUS = TRUE\r
-WRITE_DISABLED_CAP = TRUE\r
-WRITE_ENABLED_CAP = TRUE\r
-WRITE_STATUS = TRUE\r
-WRITE_LOCK_CAP = TRUE\r
-WRITE_LOCK_STATUS = TRUE\r
-READ_DISABLED_CAP = TRUE\r
-READ_ENABLED_CAP = TRUE\r
-READ_STATUS = TRUE\r
-READ_LOCK_CAP = TRUE\r
-READ_LOCK_STATUS = TRUE\r
-\r
- APRIORI DXE {\r
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
- INF ArmPlatformPkg/ArmVirtualizationPkg/VirtFdtDxe/VirtFdtDxe.inf\r
- }\r
- INF MdeModulePkg/Core/Dxe/DxeMain.inf\r
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
- INF ArmPlatformPkg/ArmVirtualizationPkg/VirtFdtDxe/VirtFdtDxe.inf\r
-\r
- #\r
- # PI DXE Drivers producing Architectural Protocols (EFI Services)\r
- #\r
- INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
- INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
- INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
- INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
- INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
-!if $(SECURE_BOOT_ENABLE) == TRUE\r
- INF SecurityPkg/VariableAuthenticated/RuntimeDxe/VariableRuntimeDxe.inf\r
- INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf\r
-!else\r
- INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
-!endif\r
- INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
- INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
- INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
- INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
- INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
-\r
- #\r
- # Multiple Console IO support\r
- #\r
- INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
- INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
- INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
- INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
- INF EmbeddedPkg/SerialDxe/SerialDxe.inf\r
-\r
- INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
- INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
-!if $(SECURE_BOOT_ENABLE) == TRUE\r
- INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashAuthenticatedDxe.inf\r
-!else\r
- INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
-!endif\r
- INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
-\r
- #\r
- # FAT filesystem + GPT/MBR partitioning\r
- #\r
- INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
- INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
- INF FatBinPkg/EnhancedFatDxe/Fat.inf\r
- INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
-\r
- #\r
- # Platform Driver\r
- #\r
- INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf\r
- INF OvmfPkg/VirtioNetDxe/VirtioNet.inf\r
- INF OvmfPkg/VirtioScsiDxe/VirtioScsi.inf\r
-\r
- #\r
- # UEFI application (Shell Embedded Boot Loader)\r
- #\r
- INF ShellPkg/Application/Shell/Shell.inf\r
-\r
- #\r
- # Bds\r
- #\r
- INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
-!ifdef INTEL_BDS\r
- INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf\r
- INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
- INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf\r
-!else\r
- INF ArmPlatformPkg/Bds/Bds.inf\r
-!endif\r
-\r
- #\r
- # Networking stack\r
- #\r
- INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf\r
- INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf\r
- INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf\r
- INF MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf\r
- INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf\r
- INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf\r
- INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf\r
- INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf\r
- INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf\r
- INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf\r
- INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf\r
- INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf\r
-\r
- #\r
- # SCSI Bus and Disk Driver\r
- #\r
- INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf\r
- INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf\r
-\r
- #\r
- # ACPI Support\r
- #\r
- INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf\r
- INF OvmfPkg/AcpiPlatformDxe/QemuFwCfgAcpiPlatformDxe.inf\r
-\r
- #\r
- # PCI support\r
- #\r
- INF ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf\r
- INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf\r
- INF OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf\r
-\r
- #\r
- # Video support\r
- #\r
- INF OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf\r
- INF OvmfPkg/PlatformDxe/Platform.inf\r
-\r
- #\r
- # USB Support\r
- #\r
- INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf\r
- INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf\r
- INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf\r
- INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf\r
- INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf\r
-\r
-!ifdef INTEL_BDS\r
- #\r
- # TianoCore logo (splash screen)\r
- #\r
- FILE FREEFORM = PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile) {\r
- SECTION RAW = MdeModulePkg/Logo/Logo.bmp\r
- }\r
-!endif\r
-\r
-[FV.FVMAIN_COMPACT]\r
-FvAlignment = 16\r
-ERASE_POLARITY = 1\r
-MEMORY_MAPPED = TRUE\r
-STICKY_WRITE = TRUE\r
-LOCK_CAP = TRUE\r
-LOCK_STATUS = TRUE\r
-WRITE_DISABLED_CAP = TRUE\r
-WRITE_ENABLED_CAP = TRUE\r
-WRITE_STATUS = TRUE\r
-WRITE_LOCK_CAP = TRUE\r
-WRITE_LOCK_STATUS = TRUE\r
-READ_DISABLED_CAP = TRUE\r
-READ_ENABLED_CAP = TRUE\r
-READ_STATUS = TRUE\r
-READ_LOCK_CAP = TRUE\r
-READ_LOCK_STATUS = TRUE\r
-\r
- APRIORI PEI {\r
- INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
- }\r
- INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf\r
- INF MdeModulePkg/Core/Pei/PeiMain.inf\r
- INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf\r
- INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf\r
- INF ArmPkg/Drivers/CpuPei/CpuPei.inf\r
- INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
-!if $(SECURE_BOOT_ENABLE) == TRUE\r
- INF SecurityPkg/VariableAuthenticated/Pei/VariablePei.inf\r
-!else\r
- INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
-!endif\r
- INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf\r
-\r
- FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {\r
- SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {\r
- SECTION FV_IMAGE = FVMAIN\r
- }\r
- }\r
-\r
-\r
-################################################################################\r
-#\r
-# Rules are use with the [FV] section's module INF type to define\r
-# how an FFS file is created for a given INF file. The following Rule are the default\r
-# rules for the different module type. User can add the customized rules to define the\r
-# content of the FFS file.\r
-#\r
-################################################################################\r
-\r
-\r
-############################################################################\r
-# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #\r
-############################################################################\r
-#\r
-#[Rule.Common.DXE_DRIVER]\r
-# FILE DRIVER = $(NAMED_GUID) {\r
-# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
-# COMPRESS PI_STD {\r
-# GUIDED {\r
-# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
-# UI STRING="$(MODULE_NAME)" Optional\r
-# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
-# }\r
-# }\r
-# }\r
-#\r
-############################################################################\r
-\r
-[Rule.Common.SEC]\r
- FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {\r
- TE TE Align = 128 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- }\r
-\r
-[Rule.Common.PEI_CORE]\r
- FILE PEI_CORE = $(NAMED_GUID) {\r
- TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING ="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.PEIM]\r
- FILE PEIM = $(NAMED_GUID) {\r
- PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.PEIM.TIANOCOMPRESSED]\r
- FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {\r
- PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
- }\r
-\r
-[Rule.Common.DXE_CORE]\r
- FILE DXE_CORE = $(NAMED_GUID) {\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.UEFI_DRIVER]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.DXE_DRIVER]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.DXE_RUNTIME_DRIVER]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.UEFI_APPLICATION]\r
- FILE APPLICATION = $(NAMED_GUID) {\r
- UI STRING ="$(MODULE_NAME)" Optional\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- }\r
-\r
-[Rule.Common.UEFI_DRIVER.BINARY]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional |.depex\r
- PE32 PE32 |.efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
- }\r
-\r
-[Rule.Common.UEFI_APPLICATION.BINARY]\r
- FILE APPLICATION = $(NAMED_GUID) {\r
- PE32 PE32 |.efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
- }\r
-\r
-[Rule.Common.USER_DEFINED.ACPITABLE]\r
- FILE FREEFORM = $(NAMED_GUID) {\r
- RAW ACPI |.acpi\r
- RAW ASL |.aml\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
+++ /dev/null
-#\r
-# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-\r
-################################################################################\r
-#\r
-# Defines Section - statements that will be processed to create a Makefile.\r
-#\r
-################################################################################\r
-[Defines]\r
- PLATFORM_NAME = ArmVirtualizationXen\r
- PLATFORM_GUID = d1c43be3-3373-4a06-86fb-d1cb3083a207\r
- PLATFORM_VERSION = 0.1\r
- DSC_SPECIFICATION = 0x00010005\r
- OUTPUT_DIRECTORY = Build/ArmVirtualizationXen-$(ARCH)\r
- SUPPORTED_ARCHITECTURES = AARCH64\r
- BUILD_TARGETS = DEBUG|RELEASE\r
- SKUID_IDENTIFIER = DEFAULT\r
- FLASH_DEFINITION = ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationXen.fdf\r
-\r
-!include ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualization.dsc.inc\r
-\r
-[LibraryClasses]\r
- SerialPortLib|OvmfPkg/Library/XenConsoleSerialPortLib/XenConsoleSerialPortLib.inf\r
- RealTimeClockLib|ArmPlatformPkg/ArmVirtualizationPkg/Library/XenRealTimeClockLib/XenRealTimeClockLib.inf\r
- XenHypercallLib|OvmfPkg/Library/XenHypercallLib/XenHypercallLib.inf\r
-\r
-[LibraryClasses.AARCH64]\r
- ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf\r
- ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexAEMv8Lib/ArmCortexAEMv8Lib.inf\r
-\r
-[LibraryClasses.ARM]\r
- ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
- ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf\r
-\r
-[LibraryClasses.common]\r
- # Virtio Support\r
- VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf\r
- VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDeviceLib.inf\r
-\r
- ArmPlatformLib|ArmPlatformPkg/ArmVirtualizationPkg/Library/ArmXenRelocatablePlatformLib/ArmXenRelocatablePlatformLib.inf\r
- ArmPlatformSysConfigLib|ArmPlatformPkg/Library/ArmPlatformSysConfigLibNull/ArmPlatformSysConfigLibNull.inf\r
-\r
- TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf\r
-\r
- CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf\r
- GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf\r
- PlatformBdsLib|ArmPlatformPkg/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf\r
- CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf\r
-\r
-[LibraryClasses.common.UEFI_DRIVER]\r
- UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf\r
-\r
-[LibraryClasses.AARCH64.SEC]\r
- ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf\r
-\r
-[LibraryClasses.ARM.SEC]\r
- ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf\r
-\r
-[BuildOptions]\r
- RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A15 -I$(WORKSPACE)/ArmPlatformPkg/ArmVirtualizationPkg/Include\r
- GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a15 -I$(WORKSPACE)/ArmPlatformPkg/ArmVirtualizationPkg/Include\r
- GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/ArmVirtualizationPkg/Include\r
-\r
-################################################################################\r
-#\r
-# Pcd Section - list of all EDK II PCD Entries defined by this Platform\r
-#\r
-################################################################################\r
-\r
-[PcdsFixedAtBuild.common]\r
- gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"XEN-UEFI"\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"\r
-\r
- gArmPlatformTokenSpaceGuid.PcdCoreCount|1\r
-!if $(ARCH) == AARCH64\r
- gArmTokenSpaceGuid.PcdVFPEnabled|1\r
-!endif\r
-\r
- gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000\r
-\r
- # Size of the region used by UEFI in permanent memory (Reserved 64MB)\r
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000\r
-\r
- #\r
- # ARM Virtual Architectural Timer\r
- #\r
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0\r
-\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE\r
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }\r
-\r
-[PcdsPatchableInModule.common]\r
- #\r
- # This will be overridden in the code\r
- #\r
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0\r
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x0\r
- gArmVirtualizationTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x0\r
-\r
- gArmTokenSpaceGuid.PcdFdBaseAddress|0x0\r
- gArmTokenSpaceGuid.PcdFvBaseAddress|0x0\r
-\r
-[PcdsDynamicDefault.common]\r
- ## If TRUE, OvmfPkg/AcpiPlatformDxe will not wait for PCI\r
- # enumeration to complete before installing ACPI tables.\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE\r
-\r
- gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|0x0\r
- gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|0x0\r
- gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|0x0\r
- gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|0x0\r
-\r
- #\r
- # ARM General Interrupt Controller\r
- #\r
- gArmTokenSpaceGuid.PcdGicDistributorBase|0x0\r
- gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x0\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x0\r
-\r
- ## PL031 RealTimeClock\r
- gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0\r
-\r
- gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0\r
- gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0\r
- gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0\r
- gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0\r
- gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0\r
- gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0\r
- gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0\r
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x0\r
-\r
- gArmVirtualizationTokenSpaceGuid.PcdFwCfgSelectorAddress|0x0\r
- gArmVirtualizationTokenSpaceGuid.PcdFwCfgDataAddress|0x0\r
-\r
- gArmVirtualizationTokenSpaceGuid.PcdArmPsciMethod|0\r
-\r
- gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3\r
-\r
-################################################################################\r
-#\r
-# Components Section - list of all EDK II Modules needed by this Platform\r
-#\r
-################################################################################\r
-[Components.common]\r
- #\r
- # PEI Phase modules\r
- #\r
- ArmPlatformPkg/ArmVirtualizationPkg/PrePi/ArmVirtPrePiUniCoreRelocatable.inf {\r
- <LibraryClasses>\r
- ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf\r
- LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf\r
- PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf\r
- HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf\r
- PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf\r
- ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibPrePi.inf\r
- MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf\r
- ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf\r
- SerialPortLib|OvmfPkg/Library/XenConsoleSerialPortLib/XenConsoleSerialPortLib.inf\r
- }\r
-\r
- #\r
- # DXE\r
- #\r
- MdeModulePkg/Core/Dxe/DxeMain.inf {\r
- <LibraryClasses>\r
- NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf\r
- }\r
- MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
-\r
- #\r
- # Architectural Protocols\r
- #\r
- ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
- MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
- MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
- MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
-\r
- MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf\r
-\r
- MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
- EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
- EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
- EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
-\r
- MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
- MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
- EmbeddedPkg/SerialDxe/SerialDxe.inf\r
-\r
- MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
-\r
- ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
- ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
- MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
-\r
- #\r
- # Platform Driver\r
- #\r
- ArmPlatformPkg/ArmVirtualizationPkg/VirtFdtDxe/VirtFdtDxe.inf\r
-\r
- #\r
- # FAT filesystem + GPT/MBR partitioning\r
- #\r
- MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
- MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
- MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
-\r
- #\r
- # Bds\r
- #\r
- MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
- MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf\r
- MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
- IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf\r
-\r
- OvmfPkg/XenBusDxe/XenBusDxe.inf\r
- OvmfPkg/XenPvBlkDxe/XenPvBlkDxe.inf\r
+++ /dev/null
-#\r
-# Copyright (c) 2011, 2013, ARM Limited. All rights reserved.\r
-# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-\r
-################################################################################\r
-#\r
-# FD Section\r
-# The [FD] Section is made up of the definition statements and a\r
-# description of what goes into the Flash Device Image. Each FD section\r
-# defines one flash "device" image. A flash device image may be one of\r
-# the following: Removable media bootable image (like a boot floppy\r
-# image,) an Option ROM image (that would be "flashed" into an add-in\r
-# card,) a System "Flash" image (that would be burned into a system's\r
-# flash) or an Update ("Capsule") image that will be used to update and\r
-# existing system flash.\r
-#\r
-################################################################################\r
-\r
-[FD.XEN_EFI]\r
-BaseAddress = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress\r
-Size = 0x00200000|gArmTokenSpaceGuid.PcdFdSize\r
-ErasePolarity = 1\r
-\r
-# This one is tricky, it must be: BlockSize * NumBlocks = Size\r
-BlockSize = 0x00001000\r
-NumBlocks = 0x200\r
-\r
-################################################################################\r
-#\r
-# Following are lists of FD Region layout which correspond to the locations of different\r
-# images within the flash device.\r
-#\r
-# Regions must be defined in ascending order and may not overlap.\r
-#\r
-# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by\r
-# the pipe "|" character, followed by the size of the region, also in hex with the leading\r
-# "0x" characters. Like:\r
-# Offset|Size\r
-# PcdOffsetCName|PcdSizeCName\r
-# RegionType <FV, DATA, or FILE>\r
-#\r
-################################################################################\r
-\r
-#\r
-# Implement the Linux kernel header layout so that the Xen loader will identify\r
-# it as something bootable, and execute it with a FDT pointer in x0. This area\r
-# will be reused to store a copy of the FDT so round it up to 8 KB.\r
-#\r
-0x00000000|0x00002000\r
-DATA = {\r
- 0x01, 0x00, 0x00, 0x10, # code0: adr x1, .\r
- 0xff, 0x07, 0x00, 0x14, # code1: b 0x2000\r
- 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, # text_offset: 512 KB\r
- 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, # image_size: 2 MB\r
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # flags\r
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res2\r
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res3\r
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res4\r
- 0x41, 0x52, 0x4d, 0x64, # magic: "ARM\x64"\r
- 0x00, 0x00, 0x00, 0x00 # res5\r
-}\r
-\r
-0x00002000|0x001fe000\r
-gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize\r
-FV = FVMAIN_COMPACT\r
-\r
-\r
-################################################################################\r
-#\r
-# FV Section\r
-#\r
-# [FV] section is used to define what components or modules are placed within a flash\r
-# device file. This section also defines order the components and modules are positioned\r
-# within the image. The [FV] section consists of define statements, set statements and\r
-# module statements.\r
-#\r
-################################################################################\r
-\r
-[FV.FvMain]\r
-BlockSize = 0x40\r
-NumBlocks = 0 # This FV gets compressed so make it just big enough\r
-FvAlignment = 16 # FV alignment and FV attributes setting.\r
-ERASE_POLARITY = 1\r
-MEMORY_MAPPED = TRUE\r
-STICKY_WRITE = TRUE\r
-LOCK_CAP = TRUE\r
-LOCK_STATUS = TRUE\r
-WRITE_DISABLED_CAP = TRUE\r
-WRITE_ENABLED_CAP = TRUE\r
-WRITE_STATUS = TRUE\r
-WRITE_LOCK_CAP = TRUE\r
-WRITE_LOCK_STATUS = TRUE\r
-READ_DISABLED_CAP = TRUE\r
-READ_ENABLED_CAP = TRUE\r
-READ_STATUS = TRUE\r
-READ_LOCK_CAP = TRUE\r
-READ_LOCK_STATUS = TRUE\r
-\r
- APRIORI DXE {\r
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
- INF ArmPlatformPkg/ArmVirtualizationPkg/VirtFdtDxe/VirtFdtDxe.inf\r
- }\r
- INF MdeModulePkg/Core/Dxe/DxeMain.inf\r
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
- INF ArmPlatformPkg/ArmVirtualizationPkg/VirtFdtDxe/VirtFdtDxe.inf\r
-\r
- #\r
- # PI DXE Drivers producing Architectural Protocols (EFI Services)\r
- #\r
- INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
- INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
- INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
- INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
-\r
- INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf\r
-\r
- INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
- INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
- INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
- INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
- INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
-\r
- #\r
- # Multiple Console IO support\r
- #\r
- INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
- INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
- INF EmbeddedPkg/SerialDxe/SerialDxe.inf\r
-\r
- INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
- INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
- INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
-\r
- #\r
- # FAT filesystem + GPT/MBR partitioning\r
- #\r
- INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
- INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
- INF FatBinPkg/EnhancedFatDxe/Fat.inf\r
- INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
-\r
- #\r
- # UEFI application (Shell Embedded Boot Loader)\r
- #\r
- INF ShellPkg/Application/Shell/Shell.inf\r
-\r
- #\r
- # Bds\r
- #\r
- INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
- INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf\r
- INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
- INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf\r
-\r
- INF OvmfPkg/XenBusDxe/XenBusDxe.inf\r
- INF OvmfPkg/XenPvBlkDxe/XenPvBlkDxe.inf\r
-\r
-[FV.FVMAIN_COMPACT]\r
-FvAlignment = 16\r
-ERASE_POLARITY = 1\r
-MEMORY_MAPPED = TRUE\r
-STICKY_WRITE = TRUE\r
-LOCK_CAP = TRUE\r
-LOCK_STATUS = TRUE\r
-WRITE_DISABLED_CAP = TRUE\r
-WRITE_ENABLED_CAP = TRUE\r
-WRITE_STATUS = TRUE\r
-WRITE_LOCK_CAP = TRUE\r
-WRITE_LOCK_STATUS = TRUE\r
-READ_DISABLED_CAP = TRUE\r
-READ_ENABLED_CAP = TRUE\r
-READ_STATUS = TRUE\r
-READ_LOCK_CAP = TRUE\r
-READ_LOCK_STATUS = TRUE\r
-\r
- INF ArmPlatformPkg/ArmVirtualizationPkg/PrePi/ArmVirtPrePiUniCoreRelocatable.inf\r
-\r
- FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {\r
- SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {\r
- SECTION FV_IMAGE = FVMAIN\r
- }\r
- }\r
-\r
-\r
-################################################################################\r
-#\r
-# Rules are use with the [FV] section's module INF type to define\r
-# how an FFS file is created for a given INF file. The following Rule are the default\r
-# rules for the different module type. User can add the customized rules to define the\r
-# content of the FFS file.\r
-#\r
-################################################################################\r
-\r
-\r
-############################################################################\r
-# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #\r
-############################################################################\r
-#\r
-#[Rule.Common.DXE_DRIVER]\r
-# FILE DRIVER = $(NAMED_GUID) {\r
-# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
-# COMPRESS PI_STD {\r
-# GUIDED {\r
-# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
-# UI STRING="$(MODULE_NAME)" Optional\r
-# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
-# }\r
-# }\r
-# }\r
-#\r
-############################################################################\r
-\r
-[Rule.Common.SEC]\r
- FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {\r
- TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- }\r
-\r
-[Rule.Common.PEI_CORE]\r
- FILE PEI_CORE = $(NAMED_GUID) {\r
- TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING ="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.PEIM]\r
- FILE PEIM = $(NAMED_GUID) {\r
- PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.PEIM.TIANOCOMPRESSED]\r
- FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {\r
- PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
- }\r
-\r
-[Rule.Common.DXE_CORE]\r
- FILE DXE_CORE = $(NAMED_GUID) {\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.UEFI_DRIVER]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.DXE_DRIVER]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.DXE_RUNTIME_DRIVER]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.UEFI_APPLICATION]\r
- FILE APPLICATION = $(NAMED_GUID) {\r
- UI STRING ="$(MODULE_NAME)" Optional\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- }\r
-\r
-[Rule.Common.UEFI_DRIVER.BINARY]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional |.depex\r
- PE32 PE32 |.efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
- }\r
-\r
-[Rule.Common.UEFI_APPLICATION.BINARY]\r
- FILE APPLICATION = $(NAMED_GUID) {\r
- PE32 PE32 |.efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
- }\r
-\r
-[Rule.Common.USER_DEFINED.ACPITABLE]\r
- FILE FREEFORM = $(NAMED_GUID) {\r
- RAW ACPI |.acpi\r
- RAW ASL |.aml\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
+++ /dev/null
-/** @file\r
-* Header defining platform constants (Base addresses, sizes, flags)\r
-*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
-* Copyright (c) 2014, Linaro Limited\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#ifndef __PLATFORM_H__\r
-#define __PLATFORM_H__\r
-\r
-//\r
-// We don't care about this value, but the PL031 driver depends on the macro\r
-// to exist: it will pass it on to our ArmPlatformSysConfigLib:ConfigGet()\r
-// function, which just returns EFI_UNSUPPORTED.\r
-//\r
-#define SYS_CFG_RTC 0x0\r
-\r
-#define QEMU_NOR_BLOCK_SIZE SIZE_256KB\r
-#define QEMU_NOR0_BASE 0x0\r
-#define QEMU_NOR0_SIZE SIZE_64MB\r
-#define QEMU_NOR1_BASE 0x04000000\r
-#define QEMU_NOR1_SIZE SIZE_64MB\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- GUID for the HOB that caches the base address of the PL011 serial port, for\r
- when PCD access is not available.\r
-\r
- Copyright (C) 2014, Red Hat, Inc.\r
-\r
- This program and the accompanying materials are licensed and made available\r
- under the terms and conditions of the BSD License that accompanies this\r
- distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
- WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#ifndef __EARLY_PL011_BASE_ADDRESS_H__\r
-#define __EARLY_PL011_BASE_ADDRESS_H__\r
-\r
-#define EARLY_PL011_BASE_ADDRESS_GUID { \\r
- 0xB199DEA9, 0xFD5C, 0x4A84, \\r
- { 0x80, 0x82, 0x2F, 0x41, 0x70, 0x78, 0x03, 0x05 } \\r
- }\r
-\r
-extern EFI_GUID gEarlyPL011BaseAddressGuid;\r
-\r
-#endif\r
+++ /dev/null
-## @file\r
-# Instance of HOB Library using HOB list from EFI Configuration Table, with\r
-# DebugLib dependency removed\r
-#\r
-# HOB Library implementation that retrieves the HOB List\r
-# from the System Configuration Table in the EFI System Table.\r
-#\r
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
-# Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-##\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = ArmVirtualizationDxeHobLib\r
- FILE_GUID = 3CD90EEC-EBF3-425D-AAE8-B16215AC4F50\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = HobLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER SMM_CORE DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
- CONSTRUCTOR = HobLibConstructor\r
-\r
-[Sources]\r
- HobLib.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
-\r
-[LibraryClasses]\r
- BaseMemoryLib\r
-\r
-[Guids]\r
- gEfiHobListGuid ## CONSUMES ## SystemTable\r
+++ /dev/null
-/** @file\r
- HOB Library implemenation for Dxe Phase with DebugLib dependency removed\r
-\r
-Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
-Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#define ASSERT(Expression) \\r
- do { \\r
- if (!(Expression)) { \\r
- CpuDeadLoop (); \\r
- } \\r
- } while (FALSE)\r
-\r
-#include <PiDxe.h>\r
-\r
-#include <Guid/HobList.h>\r
-\r
-#include <Library/HobLib.h>\r
-#include <Library/UefiLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
-\r
-VOID *mHobList = NULL;\r
-\r
-/**\r
- The constructor function caches the pointer to HOB list.\r
-\r
- The constructor function gets the start address of HOB list from system configuration table.\r
-\r
- @param ImageHandle The firmware allocated handle for the EFI image.\r
- @param SystemTable A pointer to the EFI System Table.\r
-\r
- @retval EFI_SUCCESS The constructor successfully gets HobList.\r
- @retval Other value The constructor can't get HobList.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-HobLibConstructor (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-{\r
- UINTN Index;\r
-\r
- for (Index = 0; Index < SystemTable->NumberOfTableEntries; Index++) {\r
- if (CompareGuid (&gEfiHobListGuid, &(SystemTable->ConfigurationTable[Index].VendorGuid))) {\r
- mHobList = SystemTable->ConfigurationTable[Index].VendorTable;\r
- return EFI_SUCCESS;\r
- }\r
- }\r
-\r
- return EFI_NOT_FOUND;\r
-}\r
-\r
-/**\r
- Returns the pointer to the HOB list.\r
-\r
- This function returns the pointer to first HOB in the list.\r
- For PEI phase, the PEI service GetHobList() can be used to retrieve the pointer\r
- to the HOB list. For the DXE phase, the HOB list pointer can be retrieved through\r
- the EFI System Table by looking up theHOB list GUID in the System Configuration Table.\r
- Since the System Configuration Table does not exist that the time the DXE Core is\r
- launched, the DXE Core uses a global variable from the DXE Core Entry Point Library\r
- to manage the pointer to the HOB list.\r
-\r
- If the pointer to the HOB list is NULL, then ASSERT().\r
-\r
- @return The pointer to the HOB list.\r
-\r
-**/\r
-VOID *\r
-EFIAPI\r
-GetHobList (\r
- VOID\r
- )\r
-{\r
- ASSERT (mHobList != NULL);\r
- return mHobList;\r
-}\r
-\r
-/**\r
- Returns the next instance of a HOB type from the starting HOB.\r
-\r
- This function searches the first instance of a HOB type from the starting HOB pointer.\r
- If there does not exist such HOB type from the starting HOB pointer, it will return NULL.\r
- In contrast with macro GET_NEXT_HOB(), this function does not skip the starting HOB pointer\r
- unconditionally: it returns HobStart back if HobStart itself meets the requirement;\r
- caller is required to use GET_NEXT_HOB() if it wishes to skip current HobStart.\r
-\r
- If HobStart is NULL, then ASSERT().\r
-\r
- @param Type The HOB type to return.\r
- @param HobStart The starting HOB pointer to search from.\r
-\r
- @return The next instance of a HOB type from the starting HOB.\r
-\r
-**/\r
-VOID *\r
-EFIAPI\r
-GetNextHob (\r
- IN UINT16 Type,\r
- IN CONST VOID *HobStart\r
- )\r
-{\r
- EFI_PEI_HOB_POINTERS Hob;\r
-\r
- ASSERT (HobStart != NULL);\r
-\r
- Hob.Raw = (UINT8 *) HobStart;\r
- //\r
- // Parse the HOB list until end of list or matching type is found.\r
- //\r
- while (!END_OF_HOB_LIST (Hob)) {\r
- if (Hob.Header->HobType == Type) {\r
- return Hob.Raw;\r
- }\r
- Hob.Raw = GET_NEXT_HOB (Hob);\r
- }\r
- return NULL;\r
-}\r
-\r
-/**\r
- Returns the first instance of a HOB type among the whole HOB list.\r
-\r
- This function searches the first instance of a HOB type among the whole HOB list.\r
- If there does not exist such HOB type in the HOB list, it will return NULL.\r
-\r
- If the pointer to the HOB list is NULL, then ASSERT().\r
-\r
- @param Type The HOB type to return.\r
-\r
- @return The next instance of a HOB type from the starting HOB.\r
-\r
-**/\r
-VOID *\r
-EFIAPI\r
-GetFirstHob (\r
- IN UINT16 Type\r
- )\r
-{\r
- VOID *HobList;\r
-\r
- HobList = GetHobList ();\r
- return GetNextHob (Type, HobList);\r
-}\r
-\r
-/**\r
- Returns the next instance of the matched GUID HOB from the starting HOB.\r
-\r
- This function searches the first instance of a HOB from the starting HOB pointer.\r
- Such HOB should satisfy two conditions:\r
- its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to the input Guid.\r
- If there does not exist such HOB from the starting HOB pointer, it will return NULL.\r
- Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_SIZE ()\r
- to extract the data section and its size information, respectively.\r
- In contrast with macro GET_NEXT_HOB(), this function does not skip the starting HOB pointer\r
- unconditionally: it returns HobStart back if HobStart itself meets the requirement;\r
- caller is required to use GET_NEXT_HOB() if it wishes to skip current HobStart.\r
-\r
- If Guid is NULL, then ASSERT().\r
- If HobStart is NULL, then ASSERT().\r
-\r
- @param Guid The GUID to match with in the HOB list.\r
- @param HobStart A pointer to a Guid.\r
-\r
- @return The next instance of the matched GUID HOB from the starting HOB.\r
-\r
-**/\r
-VOID *\r
-EFIAPI\r
-GetNextGuidHob (\r
- IN CONST EFI_GUID *Guid,\r
- IN CONST VOID *HobStart\r
- )\r
-{\r
- EFI_PEI_HOB_POINTERS GuidHob;\r
-\r
- GuidHob.Raw = (UINT8 *) HobStart;\r
- while ((GuidHob.Raw = GetNextHob (EFI_HOB_TYPE_GUID_EXTENSION, GuidHob.Raw)) != NULL) {\r
- if (CompareGuid (Guid, &GuidHob.Guid->Name)) {\r
- break;\r
- }\r
- GuidHob.Raw = GET_NEXT_HOB (GuidHob);\r
- }\r
- return GuidHob.Raw;\r
-}\r
-\r
-/**\r
- Returns the first instance of the matched GUID HOB among the whole HOB list.\r
-\r
- This function searches the first instance of a HOB among the whole HOB list.\r
- Such HOB should satisfy two conditions:\r
- its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to the input Guid.\r
- If there does not exist such HOB from the starting HOB pointer, it will return NULL.\r
- Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_SIZE ()\r
- to extract the data section and its size information, respectively.\r
-\r
- If the pointer to the HOB list is NULL, then ASSERT().\r
- If Guid is NULL, then ASSERT().\r
-\r
- @param Guid The GUID to match with in the HOB list.\r
-\r
- @return The first instance of the matched GUID HOB among the whole HOB list.\r
-\r
-**/\r
-VOID *\r
-EFIAPI\r
-GetFirstGuidHob (\r
- IN CONST EFI_GUID *Guid\r
- )\r
-{\r
- VOID *HobList;\r
-\r
- HobList = GetHobList ();\r
- return GetNextGuidHob (Guid, HobList);\r
-}\r
-\r
-/**\r
- Get the system boot mode from the HOB list.\r
-\r
- This function returns the system boot mode information from the\r
- PHIT HOB in HOB list.\r
-\r
- If the pointer to the HOB list is NULL, then ASSERT().\r
-\r
- @param VOID\r
-\r
- @return The Boot Mode.\r
-\r
-**/\r
-EFI_BOOT_MODE\r
-EFIAPI\r
-GetBootModeHob (\r
- VOID\r
- )\r
-{\r
- EFI_HOB_HANDOFF_INFO_TABLE *HandOffHob;\r
-\r
- HandOffHob = (EFI_HOB_HANDOFF_INFO_TABLE *) GetHobList ();\r
-\r
- return HandOffHob->BootMode;\r
-}\r
-\r
-/**\r
- Builds a HOB for a loaded PE32 module.\r
-\r
- This function builds a HOB for a loaded PE32 module.\r
- It can only be invoked during PEI phase;\r
- for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
-\r
- If ModuleName is NULL, then ASSERT().\r
- If there is no additional space for HOB creation, then ASSERT().\r
-\r
- @param ModuleName The GUID File Name of the module.\r
- @param MemoryAllocationModule The 64 bit physical address of the module.\r
- @param ModuleLength The length of the module in bytes.\r
- @param EntryPoint The 64 bit physical address of the module entry point.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-BuildModuleHob (\r
- IN CONST EFI_GUID *ModuleName,\r
- IN EFI_PHYSICAL_ADDRESS MemoryAllocationModule,\r
- IN UINT64 ModuleLength,\r
- IN EFI_PHYSICAL_ADDRESS EntryPoint\r
- )\r
-{\r
- //\r
- // PEI HOB is read only for DXE phase\r
- //\r
- ASSERT (FALSE);\r
-}\r
-\r
-/**\r
- Builds a HOB that describes a chunk of system memory.\r
-\r
- This function builds a HOB that describes a chunk of system memory.\r
- It can only be invoked during PEI phase;\r
- for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
-\r
- If there is no additional space for HOB creation, then ASSERT().\r
-\r
- @param ResourceType The type of resource described by this HOB.\r
- @param ResourceAttribute The resource attributes of the memory described by this HOB.\r
- @param PhysicalStart The 64 bit physical address of memory described by this HOB.\r
- @param NumberOfBytes The length of the memory described by this HOB in bytes.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-BuildResourceDescriptorHob (\r
- IN EFI_RESOURCE_TYPE ResourceType,\r
- IN EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute,\r
- IN EFI_PHYSICAL_ADDRESS PhysicalStart,\r
- IN UINT64 NumberOfBytes\r
- )\r
-{\r
- //\r
- // PEI HOB is read only for DXE phase\r
- //\r
- ASSERT (FALSE);\r
-}\r
-\r
-/**\r
- Builds a customized HOB tagged with a GUID for identification and returns\r
- the start address of GUID HOB data.\r
-\r
- This function builds a customized HOB tagged with a GUID for identification\r
- and returns the start address of GUID HOB data so that caller can fill the customized data.\r
- The HOB Header and Name field is already stripped.\r
- It can only be invoked during PEI phase;\r
- for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
-\r
- If Guid is NULL, then ASSERT().\r
- If there is no additional space for HOB creation, then ASSERT().\r
- If DataLength > (0xFFF8 - sizeof (EFI_HOB_GUID_TYPE)), then ASSERT().\r
- HobLength is UINT16 and multiples of 8 bytes, so the max HobLength is 0xFFF8.\r
-\r
- @param Guid The GUID to tag the customized HOB.\r
- @param DataLength The size of the data payload for the GUID HOB.\r
-\r
- @retval NULL The GUID HOB could not be allocated.\r
- @retval others The start address of GUID HOB data.\r
-\r
-**/\r
-VOID *\r
-EFIAPI\r
-BuildGuidHob (\r
- IN CONST EFI_GUID *Guid,\r
- IN UINTN DataLength\r
- )\r
-{\r
- //\r
- // PEI HOB is read only for DXE phase\r
- //\r
- ASSERT (FALSE);\r
- return NULL;\r
-}\r
-\r
-/**\r
- Builds a customized HOB tagged with a GUID for identification, copies the input data to the HOB\r
- data field, and returns the start address of the GUID HOB data.\r
-\r
- This function builds a customized HOB tagged with a GUID for identification and copies the input\r
- data to the HOB data field and returns the start address of the GUID HOB data. It can only be\r
- invoked during PEI phase; for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
- The HOB Header and Name field is already stripped.\r
- It can only be invoked during PEI phase;\r
- for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
-\r
- If Guid is NULL, then ASSERT().\r
- If Data is NULL and DataLength > 0, then ASSERT().\r
- If there is no additional space for HOB creation, then ASSERT().\r
- If DataLength > (0xFFF8 - sizeof (EFI_HOB_GUID_TYPE)), then ASSERT().\r
- HobLength is UINT16 and multiples of 8 bytes, so the max HobLength is 0xFFF8.\r
-\r
- @param Guid The GUID to tag the customized HOB.\r
- @param Data The data to be copied into the data field of the GUID HOB.\r
- @param DataLength The size of the data payload for the GUID HOB.\r
-\r
- @retval NULL The GUID HOB could not be allocated.\r
- @retval others The start address of GUID HOB data.\r
-\r
-**/\r
-VOID *\r
-EFIAPI\r
-BuildGuidDataHob (\r
- IN CONST EFI_GUID *Guid,\r
- IN VOID *Data,\r
- IN UINTN DataLength\r
- )\r
-{\r
- //\r
- // PEI HOB is read only for DXE phase\r
- //\r
- ASSERT (FALSE);\r
- return NULL;\r
-}\r
-\r
-/**\r
- Builds a Firmware Volume HOB.\r
-\r
- This function builds a Firmware Volume HOB.\r
- It can only be invoked during PEI phase;\r
- for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
-\r
- If there is no additional space for HOB creation, then ASSERT().\r
-\r
- @param BaseAddress The base address of the Firmware Volume.\r
- @param Length The size of the Firmware Volume in bytes.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-BuildFvHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
- )\r
-{\r
- //\r
- // PEI HOB is read only for DXE phase\r
- //\r
- ASSERT (FALSE);\r
-}\r
-\r
-/**\r
- Builds a EFI_HOB_TYPE_FV2 HOB.\r
-\r
- This function builds a EFI_HOB_TYPE_FV2 HOB.\r
- It can only be invoked during PEI phase;\r
- for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
-\r
- If there is no additional space for HOB creation, then ASSERT().\r
-\r
- @param BaseAddress The base address of the Firmware Volume.\r
- @param Length The size of the Firmware Volume in bytes.\r
- @param FvName The name of the Firmware Volume.\r
- @param FileName The name of the file.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-BuildFv2Hob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN CONST EFI_GUID *FvName,\r
- IN CONST EFI_GUID *FileName\r
- )\r
-{\r
- ASSERT (FALSE);\r
-}\r
-\r
-\r
-/**\r
- Builds a Capsule Volume HOB.\r
-\r
- This function builds a Capsule Volume HOB.\r
- It can only be invoked during PEI phase;\r
- for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
-\r
- If the platform does not support Capsule Volume HOBs, then ASSERT().\r
- If there is no additional space for HOB creation, then ASSERT().\r
-\r
- @param BaseAddress The base address of the Capsule Volume.\r
- @param Length The size of the Capsule Volume in bytes.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-BuildCvHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
- )\r
-{\r
- //\r
- // PEI HOB is read only for DXE phase\r
- //\r
- ASSERT (FALSE);\r
-}\r
-\r
-/**\r
- Builds a HOB for the CPU.\r
-\r
- This function builds a HOB for the CPU.\r
- It can only be invoked during PEI phase;\r
- for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
-\r
- If there is no additional space for HOB creation, then ASSERT().\r
-\r
- @param SizeOfMemorySpace The maximum physical memory addressability of the processor.\r
- @param SizeOfIoSpace The maximum physical I/O addressability of the processor.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-BuildCpuHob (\r
- IN UINT8 SizeOfMemorySpace,\r
- IN UINT8 SizeOfIoSpace\r
- )\r
-{\r
- //\r
- // PEI HOB is read only for DXE phase\r
- //\r
- ASSERT (FALSE);\r
-}\r
-\r
-/**\r
- Builds a HOB for the Stack.\r
-\r
- This function builds a HOB for the stack.\r
- It can only be invoked during PEI phase;\r
- for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
-\r
- If there is no additional space for HOB creation, then ASSERT().\r
-\r
- @param BaseAddress The 64 bit physical address of the Stack.\r
- @param Length The length of the stack in bytes.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-BuildStackHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
- )\r
-{\r
- //\r
- // PEI HOB is read only for DXE phase\r
- //\r
- ASSERT (FALSE);\r
-}\r
-\r
-/**\r
- Builds a HOB for the BSP store.\r
-\r
- This function builds a HOB for BSP store.\r
- It can only be invoked during PEI phase;\r
- for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
-\r
- If there is no additional space for HOB creation, then ASSERT().\r
-\r
- @param BaseAddress The 64 bit physical address of the BSP.\r
- @param Length The length of the BSP store in bytes.\r
- @param MemoryType Type of memory allocated by this HOB.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-BuildBspStoreHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN EFI_MEMORY_TYPE MemoryType\r
- )\r
-{\r
- //\r
- // PEI HOB is read only for DXE phase\r
- //\r
- ASSERT (FALSE);\r
-}\r
-\r
-/**\r
- Builds a HOB for the memory allocation.\r
-\r
- This function builds a HOB for the memory allocation.\r
- It can only be invoked during PEI phase;\r
- for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
-\r
- If there is no additional space for HOB creation, then ASSERT().\r
-\r
- @param BaseAddress The 64 bit physical address of the memory.\r
- @param Length The length of the memory allocation in bytes.\r
- @param MemoryType Type of memory allocated by this HOB.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-BuildMemoryAllocationHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN EFI_MEMORY_TYPE MemoryType\r
- )\r
-{\r
- //\r
- // PEI HOB is read only for DXE phase\r
- //\r
- ASSERT (FALSE);\r
-}\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-* Copyright (c) 2014, Linaro Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <PiPei.h>\r
-\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/HobLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/CacheMaintenanceLib.h>\r
-\r
-VOID\r
-BuildMemoryTypeInformationHob (\r
- VOID\r
- );\r
-\r
-VOID\r
-InitMmu (\r
- VOID\r
- )\r
-{\r
- ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;\r
- VOID *TranslationTableBase;\r
- UINTN TranslationTableSize;\r
- RETURN_STATUS Status;\r
-\r
- // Get Virtual Memory Map from the Platform Library\r
- ArmPlatformGetVirtualMemoryMap (&MemoryTable);\r
-\r
- //Note: Because we called PeiServicesInstallPeiMemory() before to call InitMmu() the MMU Page Table resides in\r
- // DRAM (even at the top of DRAM as it is the first permanent memory allocation)\r
- Status = ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "Error: Failed to enable MMU\n"));\r
- }\r
-}\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-MemoryPeim (\r
- IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,\r
- IN UINT64 UefiMemorySize\r
- )\r
-{\r
- EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;\r
-\r
- // Ensure PcdSystemMemorySize has been set\r
- ASSERT (PcdGet64 (PcdSystemMemorySize) != 0);\r
-\r
- //\r
- // Now, the permanent memory has been installed, we can call AllocatePages()\r
- //\r
- ResourceAttributes = (\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_TESTED\r
- );\r
-\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_SYSTEM_MEMORY,\r
- ResourceAttributes,\r
- PcdGet64 (PcdSystemMemoryBase),\r
- PcdGet64 (PcdSystemMemorySize)\r
- );\r
-\r
- //\r
- // When running under virtualization, the PI/UEFI memory region may be\r
- // clean but not invalidated in system caches or in lower level caches\r
- // on other CPUs. So invalidate the region by virtual address, to ensure\r
- // that the contents we put there with the caches and MMU off will still\r
- // be visible after turning them on.\r
- //\r
- InvalidateDataCacheRange ((VOID*)(UINTN)UefiMemoryBase, UefiMemorySize);\r
-\r
- // Build Memory Allocation Hob\r
- InitMmu ();\r
-\r
- if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) {\r
- // Optional feature that helps prevent EFI memory map fragmentation.\r
- BuildMemoryTypeInformationHob ();\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
+++ /dev/null
-#/** @file\r
-#\r
-# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>\r
-# Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = ArmVirtMemoryInitPeiLib\r
- FILE_GUID = 021b6156-3cc8-4e99-85ee-13d8a871edf2\r
- MODULE_TYPE = SEC\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = MemoryInitPeiLib\r
-\r
-[Sources]\r
- ArmVirtualizationMemoryInitPeiLib.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
-\r
-[LibraryClasses]\r
- DebugLib\r
- HobLib\r
- ArmLib\r
- ArmPlatformLib\r
- CacheMaintenanceLib\r
-\r
-[Guids]\r
- gEfiMemoryTypeInformationGuid\r
-\r
-[FeaturePcd]\r
- gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob\r
-\r
-[FixedPcd]\r
- gArmTokenSpaceGuid.PcdFdSize\r
-\r
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize\r
-\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData\r
-\r
-[Pcd]\r
- gArmTokenSpaceGuid.PcdSystemMemoryBase\r
- gArmTokenSpaceGuid.PcdSystemMemorySize\r
- gArmTokenSpaceGuid.PcdFdBaseAddress\r
-\r
-[Depex]\r
- TRUE\r
+++ /dev/null
-#\r
-# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-\r
-#include <AsmMacroIoLibV8.h>\r
-#include <Base.h>\r
-#include <Library/ArmLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <AutoGen.h>\r
-\r
-.text\r
-.align 2\r
-\r
-GCC_ASM_EXPORT(ArmPlatformPeiBootAction)\r
-GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
-GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r
-GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r
-GCC_ASM_EXPORT(ArmGetPhysAddrTop)\r
-\r
-GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r
-GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r
-GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdCoreCount)\r
-\r
-ASM_PFX(ArmPlatformPeiBootAction):\r
- ret\r
-\r
-//UINTN\r
-//ArmPlatformGetPrimaryCoreMpId (\r
-// VOID\r
-// );\r
-ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, x0)\r
- ldrh w0, [x0]\r
- ret\r
-\r
-//UINTN\r
-//ArmPlatformIsPrimaryCore (\r
-// IN UINTN MpId\r
-// );\r
-ASM_PFX(ArmPlatformIsPrimaryCore):\r
- mov x0, #1\r
- ret\r
-\r
-//UINTN\r
-//ArmPlatformGetCorePosition (\r
-// IN UINTN MpId\r
-// );\r
-// With this function: CorePos = (ClusterId * 4) + CoreId\r
-ASM_PFX(ArmPlatformGetCorePosition):\r
- and x1, x0, #ARM_CORE_MASK\r
- and x0, x0, #ARM_CLUSTER_MASK\r
- add x0, x1, x0, LSR #6\r
- ret\r
-\r
-//EFI_PHYSICAL_ADDRESS\r
-//GetPhysAddrTop (\r
-// VOID\r
-// );\r
-ASM_PFX(ArmGetPhysAddrTop):\r
- mrs x0, id_aa64mmfr0_el1\r
- adr x1, .LPARanges\r
- and x0, x0, #7\r
- ldrb w1, [x1, x0]\r
- mov x0, #1\r
- lsl x0, x0, x1\r
- ret\r
-\r
-//\r
-// Bits 0..2 of the AA64MFR0_EL1 system register encode the size of the\r
-// physical address space support on this CPU:\r
-// 0 == 32 bits, 1 == 36 bits, etc etc\r
-// 6 and 7 are reserved\r
-//\r
-.LPARanges:\r
- .byte 32, 36, 40, 42, 44, 48, -1, -1\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
+++ /dev/null
-#\r
-# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <Library/ArmLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <AutoGen.h>\r
-\r
-.text\r
-.align 2\r
-\r
-GCC_ASM_EXPORT(ArmPlatformPeiBootAction)\r
-GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
-GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r
-GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r
-GCC_ASM_EXPORT(ArmGetPhysAddrTop)\r
-\r
-GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r
-GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r
-GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdCoreCount)\r
-\r
-ASM_PFX(ArmPlatformPeiBootAction):\r
- bx lr\r
-\r
-//UINTN\r
-//ArmPlatformGetPrimaryCoreMpId (\r
-// VOID\r
-// );\r
-ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)\r
- ldr r0, [r0]\r
- bx lr\r
-\r
-//UINTN\r
-//ArmPlatformIsPrimaryCore (\r
-// IN UINTN MpId\r
-// );\r
-ASM_PFX(ArmPlatformIsPrimaryCore):\r
- mov r0, #1\r
- bx lr\r
-\r
-//UINTN\r
-//ArmPlatformGetCorePosition (\r
-// IN UINTN MpId\r
-// );\r
-// With this function: CorePos = (ClusterId * 4) + CoreId\r
-ASM_PFX(ArmPlatformGetCorePosition):\r
- and r1, r0, #ARM_CORE_MASK\r
- and r0, r0, #ARM_CLUSTER_MASK\r
- add r0, r1, r0, LSR #6\r
- bx lr\r
-\r
-//EFI_PHYSICAL_ADDRESS\r
-//GetPhysAddrTop (\r
-// VOID\r
-// );\r
-ASM_PFX(ArmGetPhysAddrTop):\r
- mov r0, #0x00000000\r
- mov r1, #0x10000\r
- bx lr\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-// Copyright (c) 2014, Linaro Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <Library/ArmLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <AutoGen.h>\r
-\r
- INCLUDE AsmMacroIoLib.inc\r
-\r
- EXPORT ArmPlatformPeiBootAction\r
- EXPORT ArmPlatformIsPrimaryCore\r
- EXPORT ArmPlatformGetPrimaryCoreMpId\r
- EXPORT ArmPlatformGetCorePosition\r
- EXPORT ArmGetPhysAddrTop\r
-\r
- IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCore\r
- IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCoreMask\r
- IMPORT _gPcd_FixedAtBuild_PcdCoreCount\r
-\r
- AREA VirtHelper, CODE, READONLY\r
-\r
-ArmPlatformPeiBootAction FUNCTION\r
- bx lr\r
- ENDFUNC\r
-\r
-//UINTN\r
-//ArmPlatformGetPrimaryCoreMpId (\r
-// VOID\r
-// );\r
-ArmPlatformGetPrimaryCoreMpId FUNCTION\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)\r
- ldr r0, [r0]\r
- bx lr\r
- ENDFUNC\r
-\r
-//UINTN\r
-//ArmPlatformIsPrimaryCore (\r
-// IN UINTN MpId\r
-// );\r
-ArmPlatformIsPrimaryCore FUNCTION\r
- mov r0, #1\r
- bx lr\r
- ENDFUNC\r
-\r
-//UINTN\r
-//ArmPlatformGetCorePosition (\r
-// IN UINTN MpId\r
-// );\r
-// With this function: CorePos = (ClusterId * 4) + CoreId\r
-ArmPlatformGetCorePosition FUNCTION\r
- and r1, r0, #ARM_CORE_MASK\r
- and r0, r0, #ARM_CLUSTER_MASK\r
- add r0, r1, r0, LSR #6\r
- bx lr\r
- ENDFUNC\r
-\r
-//EFI_PHYSICAL_ADDRESS\r
-//GetPhysAddrTop (\r
-// VOID\r
-// );\r
-ArmGetPhysAddrTop FUNCTION\r
- mov r0, #0x00000000\r
- mov r1, #0x10000\r
- bx lr\r
- ENDFUNC\r
-\r
- END\r
+++ /dev/null
-#/* @file\r
-# Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#*/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = ArmVirtualizationPlatformLib\r
- FILE_GUID = 00214cc1-06d1-45fe-9700-dca5726ad7bf\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmPlatformLib|SEC PEIM\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
- ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationPkg.dec\r
-\r
-[LibraryClasses]\r
- IoLib\r
- MemoryAllocationLib\r
- ArmLib\r
- PrintLib\r
- FdtLib\r
-\r
-[Sources.common]\r
- Virt.c\r
- VirtMem.c\r
-\r
-[Sources.AARCH64]\r
- AARCH64/VirtHelper.S\r
-\r
-[Sources.ARM]\r
- ARM/VirtHelper.S | GCC\r
- ARM/VirtHelper.asm | RVCT\r
-\r
-[FeaturePcd]\r
- gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec\r
-\r
-[Pcd]\r
- gArmTokenSpaceGuid.PcdSystemMemorySize\r
-\r
-[FixedPcd]\r
- gArmVirtualizationTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress\r
- gArmPlatformTokenSpaceGuid.PcdCoreCount\r
- gArmTokenSpaceGuid.PcdSystemMemoryBase\r
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
- gArmTokenSpaceGuid.PcdArmPrimaryCore\r
- gArmTokenSpaceGuid.PcdFdBaseAddress\r
- gArmTokenSpaceGuid.PcdFdSize\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-* Copyright (c) 2014, Linaro Limited. All rights reserved.\r
-* Copyright (c) 2014, Red Hat, Inc.\r
-*\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Library/IoLib.h>\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <ArmPlatform.h>\r
-#include <libfdt.h>\r
-#include <Pi/PiBootMode.h>\r
-#include <Uefi/UefiBaseType.h>\r
-#include <Uefi/UefiMultiPhase.h>\r
-\r
-/**\r
- Return the current Boot Mode\r
-\r
- This function returns the boot reason on the platform\r
-\r
- @return Return the current Boot Mode of the platform\r
-\r
-**/\r
-EFI_BOOT_MODE\r
-ArmPlatformGetBootMode (\r
- VOID\r
- )\r
-{\r
- return BOOT_WITH_FULL_CONFIGURATION;\r
-}\r
-\r
-/**\r
- This function is called by PrePeiCore, in the SEC phase.\r
-**/\r
-RETURN_STATUS\r
-ArmPlatformInitialize (\r
- IN UINTN MpId\r
- )\r
-{\r
- //\r
- // We are relying on ArmPlatformInitializeSystemMemory () being called from\r
- // InitializeMemory (), which only occurs if the following feature is disabled\r
- //\r
- ASSERT (!FeaturePcdGet (PcdSystemMemoryInitializeInSec));\r
- return RETURN_SUCCESS;\r
-}\r
-\r
-/**\r
- Initialize the system (or sometimes called permanent) memory\r
-\r
- This memory is generally represented by the DRAM.\r
-\r
- This function is called from InitializeMemory() in MemoryInitPeim, in the PEI\r
- phase.\r
-**/\r
-VOID\r
-ArmPlatformInitializeSystemMemory (\r
- VOID\r
- )\r
-{\r
- VOID *DeviceTreeBase;\r
- INT32 Node, Prev;\r
- UINT64 NewBase;\r
- UINT64 NewSize;\r
- CONST CHAR8 *Type;\r
- INT32 Len;\r
- CONST UINT64 *RegProp;\r
-\r
- NewBase = 0;\r
- NewSize = 0;\r
-\r
- DeviceTreeBase = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeInitialBaseAddress);\r
- ASSERT (DeviceTreeBase != NULL);\r
-\r
- //\r
- // Make sure we have a valid device tree blob\r
- //\r
- ASSERT (fdt_check_header (DeviceTreeBase) == 0);\r
-\r
- //\r
- // Look for a memory node\r
- //\r
- for (Prev = 0;; Prev = Node) {\r
- Node = fdt_next_node (DeviceTreeBase, Prev, NULL);\r
- if (Node < 0) {\r
- break;\r
- }\r
-\r
- //\r
- // Check for memory node\r
- //\r
- Type = fdt_getprop (DeviceTreeBase, Node, "device_type", &Len);\r
- if (Type && AsciiStrnCmp (Type, "memory", Len) == 0) {\r
- //\r
- // Get the 'reg' property of this node. For now, we will assume\r
- // two 8 byte quantities for base and size, respectively.\r
- //\r
- RegProp = fdt_getprop (DeviceTreeBase, Node, "reg", &Len);\r
- if (RegProp != 0 && Len == (2 * sizeof (UINT64))) {\r
-\r
- NewBase = fdt64_to_cpu (ReadUnaligned64 (RegProp));\r
- NewSize = fdt64_to_cpu (ReadUnaligned64 (RegProp + 1));\r
-\r
- //\r
- // Make sure the start of DRAM matches our expectation\r
- //\r
- ASSERT (FixedPcdGet64 (PcdSystemMemoryBase) == NewBase);\r
- PcdSet64 (PcdSystemMemorySize, NewSize);\r
-\r
- DEBUG ((EFI_D_INFO, "%a: System RAM @ 0x%lx - 0x%lx\n",\r
- __FUNCTION__, NewBase, NewBase + NewSize - 1));\r
- } else {\r
- DEBUG ((EFI_D_ERROR, "%a: Failed to parse FDT memory node\n",\r
- __FUNCTION__));\r
- }\r
- break;\r
- }\r
- }\r
-\r
- //\r
- // We need to make sure that the machine we are running on has at least\r
- // 128 MB of memory configured, and is currently executing this binary from\r
- // NOR flash. This prevents a device tree image in DRAM from getting\r
- // clobbered when our caller installs permanent PEI RAM, before we have a\r
- // chance of marking its location as reserved or copy it to a freshly\r
- // allocated block in the permanent PEI RAM in the platform PEIM.\r
- //\r
- ASSERT (NewSize >= SIZE_128MB);\r
- ASSERT (\r
- (((UINT64)PcdGet64 (PcdFdBaseAddress) +\r
- (UINT64)PcdGet32 (PcdFdSize)) <= NewBase) ||\r
- ((UINT64)PcdGet64 (PcdFdBaseAddress) >= (NewBase + NewSize)));\r
-}\r
-\r
-VOID\r
-ArmPlatformGetPlatformPpiList (\r
- OUT UINTN *PpiListSize,\r
- OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r
- )\r
-{\r
- *PpiListSize = 0;\r
- *PpiList = NULL;\r
-}\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2014, Linaro Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <Library/ArmPlatformGlobalVariableLib.h>\r
-#include <ArmPlatform.h>\r
-\r
-// Number of Virtual Memory Map Descriptors\r
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 4\r
-\r
-// DDR attributes\r
-#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
-#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
-\r
-EFI_PHYSICAL_ADDRESS\r
-ArmGetPhysAddrTop (\r
- VOID\r
- );\r
-\r
-/**\r
- Return the Virtual Memory Map of your platform\r
-\r
- This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU\r
- on your platform.\r
-\r
- @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR\r
- describing a Physical-to-Virtual Memory\r
- mapping. This array must be ended by a\r
- zero-filled entry\r
-\r
-**/\r
-VOID\r
-ArmPlatformGetVirtualMemoryMap (\r
- IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap\r
- )\r
-{\r
- ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;\r
- ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r
-\r
- ASSERT (VirtualMemoryMap != NULL);\r
-\r
- VirtualMemoryTable = AllocatePages (\r
- EFI_SIZE_TO_PAGES (\r
- sizeof (ARM_MEMORY_REGION_DESCRIPTOR)\r
- * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS\r
- )\r
- );\r
-\r
- if (VirtualMemoryTable == NULL) {\r
- DEBUG ((EFI_D_ERROR, "%a: Error: Failed AllocatePages()\n", __FUNCTION__));\r
- return;\r
- }\r
-\r
- if (FeaturePcdGet (PcdCacheEnable) == TRUE) {\r
- CacheAttributes = DDR_ATTRIBUTES_CACHED;\r
- } else {\r
- CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r
- }\r
-\r
- // System DRAM\r
- VirtualMemoryTable[0].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);\r
- VirtualMemoryTable[0].VirtualBase = VirtualMemoryTable[0].PhysicalBase;\r
- VirtualMemoryTable[0].Length = PcdGet64 (PcdSystemMemorySize);\r
- VirtualMemoryTable[0].Attributes = CacheAttributes;\r
-\r
- DEBUG ((EFI_D_INFO, "%a: Dumping System DRAM Memory Map:\n"\r
- "\tPhysicalBase: 0x%lX\n"\r
- "\tVirtualBase: 0x%lX\n"\r
- "\tLength: 0x%lX\n",\r
- __FUNCTION__,\r
- VirtualMemoryTable[0].PhysicalBase,\r
- VirtualMemoryTable[0].VirtualBase,\r
- VirtualMemoryTable[0].Length));\r
-\r
- // Peripheral space before DRAM\r
- VirtualMemoryTable[1].PhysicalBase = 0x0;\r
- VirtualMemoryTable[1].VirtualBase = 0x0;\r
- VirtualMemoryTable[1].Length = VirtualMemoryTable[0].PhysicalBase;\r
- VirtualMemoryTable[1].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
-\r
- // Peripheral space after DRAM\r
- VirtualMemoryTable[2].PhysicalBase = VirtualMemoryTable[0].Length + VirtualMemoryTable[1].Length;\r
- VirtualMemoryTable[2].VirtualBase = VirtualMemoryTable[2].PhysicalBase;\r
- VirtualMemoryTable[2].Length = ArmGetPhysAddrTop () - VirtualMemoryTable[2].PhysicalBase;\r
- VirtualMemoryTable[2].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
-\r
- // End of Table\r
- ZeroMem (&VirtualMemoryTable[3], sizeof (ARM_MEMORY_REGION_DESCRIPTOR));\r
-\r
- *VirtualMemoryMap = VirtualMemoryTable;\r
-}\r
+++ /dev/null
-/** @file\r
- Support ResetSystem Runtime call using PSCI calls\r
-\r
- Note: A similar library is implemented in\r
- ArmPkg/Library/ArmPsciResetSystemLib. Similar issues might\r
- exist in this implementation too.\r
-\r
- Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
- Copyright (c) 2013, ARM Ltd. All rights reserved.<BR>\r
- Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <PiDxe.h>\r
-\r
-#include <Library/BaseLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/EfiResetSystemLib.h>\r
-#include <Library/ArmSmcLib.h>\r
-#include <Library/ArmHvcLib.h>\r
-\r
-#include <IndustryStandard/ArmStdSmc.h>\r
-\r
-STATIC UINT32 mArmPsciMethod;\r
-\r
-RETURN_STATUS\r
-EFIAPI\r
-ArmPsciResetSystemLibConstructor (\r
- VOID\r
- )\r
-{\r
- mArmPsciMethod = PcdGet32 (PcdArmPsciMethod);\r
- return RETURN_SUCCESS;\r
-}\r
-\r
-/**\r
- Resets the entire platform.\r
-\r
- @param ResetType The type of reset to perform.\r
- @param ResetStatus The status code for the reset.\r
- @param DataSize The size, in bytes, of WatchdogData.\r
- @param ResetData For a ResetType of EfiResetCold, EfiResetWarm, or\r
- EfiResetShutdown the data buffer starts with a Null-terminated\r
- Unicode string, optionally followed by additional binary data.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-LibResetSystem (\r
- IN EFI_RESET_TYPE ResetType,\r
- IN EFI_STATUS ResetStatus,\r
- IN UINTN DataSize,\r
- IN CHAR16 *ResetData OPTIONAL\r
- )\r
-{\r
- ARM_SMC_ARGS ArmSmcArgs;\r
- ARM_HVC_ARGS ArmHvcArgs;\r
-\r
- switch (ResetType) {\r
-\r
- case EfiResetPlatformSpecific:\r
- // Map the platform specific reset as reboot\r
- case EfiResetWarm:\r
- // Map a warm reset into a cold reset\r
- case EfiResetCold:\r
- // Send a PSCI 0.2 SYSTEM_RESET command\r
- ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET;\r
- ArmHvcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET;\r
- break;\r
- case EfiResetShutdown:\r
- // Send a PSCI 0.2 SYSTEM_OFF command\r
- ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_OFF;\r
- ArmHvcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_OFF;\r
- break;\r
- default:\r
- ASSERT (FALSE);\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- switch (mArmPsciMethod) {\r
- case 1:\r
- ArmCallHvc (&ArmHvcArgs);\r
- break;\r
-\r
- case 2:\r
- ArmCallSmc (&ArmSmcArgs);\r
- break;\r
-\r
- default:\r
- DEBUG ((EFI_D_ERROR, "%a: no PSCI method defined\n", __FUNCTION__));\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- // We should never be here\r
- DEBUG ((EFI_D_ERROR, "%a: PSCI Reset failed\n", __FUNCTION__));\r
- CpuDeadLoop ();\r
- return EFI_UNSUPPORTED;\r
-}\r
-\r
-/**\r
- Initialize any infrastructure required for LibResetSystem () to function.\r
-\r
- @param ImageHandle The firmware allocated handle for the EFI image.\r
- @param SystemTable A pointer to the EFI System Table.\r
-\r
- @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-LibInitializeResetSystem (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-{\r
- return EFI_SUCCESS;\r
-}\r
+++ /dev/null
-#/** @file\r
-# Reset System lib using PSCI hypervisor or secure monitor calls\r
-#\r
-# Copyright (c) 2008, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = ArmVirtualizationPsciResetSystemLib\r
- FILE_GUID = c81d76ed-66fa-44a3-ac4a-f163120187a9\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = EfiResetSystemLib\r
- CONSTRUCTOR = ArmPsciResetSystemLibConstructor\r
-\r
-[Sources]\r
- ArmVirtualizationPsciResetSystemLib.c\r
-\r
-[Packages]\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationPkg.dec\r
- MdePkg/MdePkg.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
-\r
-[LibraryClasses]\r
- DebugLib\r
- BaseLib\r
- ArmSmcLib\r
- ArmHvcLib\r
-\r
-[Pcd]\r
- gArmVirtualizationTokenSpaceGuid.PcdArmPsciMethod\r
+++ /dev/null
-/*\r
- * Copyright (c) 2014, Linaro Ltd. All rights reserved.\r
- *\r
- * This program and the accompanying materials\r
- * are licensed and made available under the terms and conditions of the BSD License\r
- * which accompanies this distribution. The full text of the license may be found at\r
- * http://opensource.org/licenses/bsd-license.php\r
- *\r
- * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
- */\r
-\r
-/*\r
- * Theory of operation\r
- * -------------------\r
- *\r
- * This code parses a Flattened Device Tree binary (DTB) to find the base of\r
- * system RAM. It is written in assembly so that it can be executed before a\r
- * stack has been set up.\r
- *\r
- * To find the base of system RAM, we have to traverse the FDT to find a memory\r
- * node. In the context of this implementation, the first node that has a\r
- * device_type property with the value 'memory' and a 'reg' property is\r
- * acceptable, and the name of the node (memory[@xxx]) is ignored, as are any\r
- * other nodes that match the above constraints.\r
- *\r
- * In pseudo code, this implementation does the following:\r
- *\r
- * for each node {\r
- * have_device_type = false\r
- * have_reg = false\r
- *\r
- * for each property {\r
- * if property value == 'memory' {\r
- * if property name == 'device_type' {\r
- * have_device_type = true\r
- * }\r
- * } else {\r
- * if property name == 'reg' {\r
- * have_reg = true\r
- * membase = property value[0]\r
- * memsize = property value[1]\r
- * }\r
- * }\r
- * }\r
- * if have_device_type and have_reg {\r
- * return membase and memsize\r
- * }\r
- * }\r
- * return NOT_FOUND\r
- */\r
-\r
-#define FDT_MAGIC 0xedfe0dd0\r
-\r
-#define FDT_BEGIN_NODE 0x1\r
-#define FDT_END_NODE 0x2\r
-#define FDT_PROP 0x3\r
-#define FDT_END 0x9\r
-\r
- xMEMSIZE .req x0 // recorded system RAM size\r
- xMEMBASE .req x1 // recorded system RAM base\r
-\r
- xLR .req x8 // our preserved link register\r
- xDTP .req x9 // pointer to traverse the DT structure\r
- xSTRTAB .req x10 // pointer to the DTB string table\r
- xMEMNODE .req x11 // bit field to record found properties\r
-\r
-#define HAVE_REG 0x1\r
-#define HAVE_DEVICE_TYPE 0x2\r
-\r
- .text\r
- .align 3\r
-_memory:\r
- .asciz "memory"\r
-_reg:\r
- .asciz "reg"\r
-_device_type:\r
- .asciz "device_type"\r
-\r
- /*\r
- * Compare strings in x4 and x5, return in w7\r
- */\r
- .align 3\r
-strcmp:\r
- ldrb w2, [x4], #1\r
- ldrb w3, [x5], #1\r
- subs w7, w2, w3\r
- cbz w2, 0f\r
- cbz w3, 0f\r
- beq strcmp\r
-0: ret\r
-\r
- .globl find_memnode\r
-find_memnode:\r
- // preserve link register\r
- mov xLR, x30\r
- mov xDTP, x0\r
-\r
- /*\r
- * Check the DTB magic at offset 0\r
- */\r
- movz w4, #:abs_g0_nc:FDT_MAGIC\r
- movk w4, #:abs_g1:FDT_MAGIC\r
- ldr w5, [xDTP]\r
- cmp w4, w5\r
- bne err_invalid_magic\r
-\r
- /*\r
- * Read the string offset and store it for later use\r
- */\r
- ldr w4, [xDTP, #12]\r
- rev w4, w4\r
- add xSTRTAB, xDTP, x4\r
-\r
- /*\r
- * Read the struct offset and add it to the DT pointer\r
- */\r
- ldr w5, [xDTP, #8]\r
- rev w5, w5\r
- add xDTP, xDTP, x5\r
-\r
- /*\r
- * Check current tag for FDT_BEGIN_NODE\r
- */\r
- ldr w5, [xDTP]\r
- rev w5, w5\r
- cmp w5, #FDT_BEGIN_NODE\r
- bne err_unexpected_begin_tag\r
-\r
-begin_node:\r
- mov xMEMNODE, #0\r
- add xDTP, xDTP, #4\r
-\r
- /*\r
- * Advance xDTP past NULL terminated string\r
- */\r
-0: ldrb w4, [xDTP], #1\r
- cbnz w4, 0b\r
-\r
-next_tag:\r
- /*\r
- * Align the DT pointer xDTP to the next 32-bit boundary\r
- */\r
- add xDTP, xDTP, #3\r
- and xDTP, xDTP, #~3\r
-\r
- /*\r
- * Read the next tag, could be BEGIN_NODE, END_NODE, PROP, END\r
- */\r
- ldr w5, [xDTP]\r
- rev w5, w5\r
- cmp w5, #FDT_BEGIN_NODE\r
- beq begin_node\r
- cmp w5, #FDT_END_NODE\r
- beq end_node\r
- cmp w5, #FDT_PROP\r
- beq prop_node\r
- cmp w5, #FDT_END\r
- beq err_end_of_fdt\r
- b err_unexpected_tag\r
-\r
-prop_node:\r
- /*\r
- * If propname == 'reg', record as membase and memsize\r
- * If propname == 'device_type' and value == 'memory',\r
- * set the 'is_memnode' flag for this node\r
- */\r
- ldr w6, [xDTP, #4]\r
- add xDTP, xDTP, #12\r
- rev w6, w6\r
- mov x5, xDTP\r
- adr x4, _memory\r
- bl strcmp\r
-\r
- /*\r
- * Get handle to property name\r
- */\r
- ldr w5, [xDTP, #-4]\r
- rev w5, w5\r
- add x5, xSTRTAB, x5\r
-\r
- cbz w7, check_device_type\r
-\r
- /*\r
- * Check for 'reg' property\r
- */\r
- adr x4, _reg\r
- bl strcmp\r
- cbnz w7, inc_and_next_tag\r
-\r
- /*\r
- * Extract two 64-bit quantities from the 'reg' property. These values\r
- * will only be used if the node also turns out to have a device_type\r
- * property with a value of 'memory'.\r
- *\r
- * NOTE: xDTP is only guaranteed to be 32 bit aligned, and we are most\r
- * likely executing with the MMU off, so we cannot use 64 bit\r
- * wide accesses here.\r
- */\r
- ldp w4, w5, [xDTP]\r
- orr xMEMBASE, x4, x5, lsl #32\r
- ldp w4, w5, [xDTP, #8]\r
- orr xMEMSIZE, x4, x5, lsl #32\r
- rev xMEMBASE, xMEMBASE\r
- rev xMEMSIZE, xMEMSIZE\r
- orr xMEMNODE, xMEMNODE, #HAVE_REG\r
- b inc_and_next_tag\r
-\r
-check_device_type:\r
- /*\r
- * Check whether the current property's name is 'device_type'\r
- */\r
- adr x4, _device_type\r
- bl strcmp\r
- cbnz w7, inc_and_next_tag\r
- orr xMEMNODE, xMEMNODE, #HAVE_DEVICE_TYPE\r
-\r
-inc_and_next_tag:\r
- add xDTP, xDTP, x6\r
- b next_tag\r
-\r
-end_node:\r
- /*\r
- * Check for device_type = memory and reg = xxxx\r
- * If we have both, we are done\r
- */\r
- add xDTP, xDTP, #4\r
- cmp xMEMNODE, #(HAVE_REG | HAVE_DEVICE_TYPE)\r
- bne next_tag\r
-\r
- ret xLR\r
-\r
-err_invalid_magic:\r
-err_unexpected_begin_tag:\r
-err_unexpected_tag:\r
-err_end_of_fdt:\r
- wfi\r
+++ /dev/null
-#\r
-# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-\r
-#include <AsmMacroIoLibV8.h>\r
-#include <Base.h>\r
-#include <Library/ArmLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <AutoGen.h>\r
-\r
-.text\r
-.align 2\r
-\r
-GCC_ASM_EXPORT(ArmPlatformPeiBootAction)\r
-GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
-GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r
-GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r
-GCC_ASM_EXPORT(ArmGetPhysAddrTop)\r
-\r
-GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r
-GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r
-GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdCoreCount)\r
-\r
-.LFdtMagic:\r
- .byte 0xd0, 0x0d, 0xfe, 0xed\r
-\r
-.LArm64LinuxMagic:\r
- .byte 0x41, 0x52, 0x4d, 0x64\r
-\r
-// VOID\r
-// ArmPlatformPeiBootAction (\r
-// VOID *DeviceTreeBaseAddress, // passed by loader in x0\r
-// VOID *ImageBase // passed by FDF trampoline in x1\r
-// );\r
-ASM_PFX(ArmPlatformPeiBootAction):\r
- mov x29, x30 // preserve LR\r
-\r
- //\r
- // If we are booting from RAM using the Linux kernel boot protocol, x0 will\r
- // point to the DTB image in memory. Otherwise, we are just coming out of\r
- // reset, and x0 will be 0. Check also the FDT magic.\r
- //\r
- cbz x0, .Lout\r
- ldr w8, .LFdtMagic\r
- ldr w9, [x0]\r
- cmp w8, w9\r
- bne .Lout\r
-\r
- //\r
- // The base of the runtime image has been preserved in x1. Check whether\r
- // the expected magic number can be found in the header.\r
- //\r
- ldr w8, .LArm64LinuxMagic\r
- ldr w9, [x1, #0x38]\r
- cmp w8, w9\r
- bne .Lout\r
-\r
- //\r
- //\r
- // OK, so far so good. We have confirmed that we likely have a DTB and are\r
- // booting via the arm64 Linux boot protocol. Update the base-of-image PCD\r
- // to the actual relocated value, and add the shift of PcdFdBaseAddress to\r
- // PcdFvBaseAddress as well\r
- //\r
- adr x8, PcdGet64 (PcdFdBaseAddress)\r
- adr x9, PcdGet64 (PcdFvBaseAddress)\r
- ldr x6, [x8]\r
- ldr x7, [x9]\r
- sub x7, x7, x6\r
- add x7, x7, x1\r
- str x1, [x8]\r
- str x7, [x9]\r
-\r
- //\r
- // Copy the DTB to the slack space right after the 64 byte arm64/Linux style\r
- // image header at the base of this image (defined in the FDF), and record the\r
- // pointer in PcdDeviceTreeInitialBaseAddress.\r
- //\r
- adr x8, PcdGet64 (PcdDeviceTreeInitialBaseAddress)\r
- add x1, x1, #0x40\r
- str x1, [x8]\r
-\r
- ldr w8, [x0, #4] // get DTB size (BE)\r
- mov x9, x1\r
- rev w8, w8\r
- add x8, x8, x0\r
-0:ldp x6, x7, [x0], #16\r
- stp x6, x7, [x9], #16\r
- cmp x0, x8\r
- blt 0b\r
-\r
- //\r
- // Discover the memory size and offset from the DTB, and record in the\r
- // respective PCDs\r
- //\r
- mov x0, x1\r
- bl find_memnode // returns (size, base) size in (x0, x1)\r
- cbz x0, .Lout\r
-\r
- adr x8, PcdGet64 (PcdSystemMemorySize)\r
- adr x9, PcdGet64 (PcdSystemMemoryBase)\r
- str x0, [x8]\r
- str x1, [x9]\r
-\r
-.Lout:\r
- ret x29\r
-\r
-//UINTN\r
-//ArmPlatformGetPrimaryCoreMpId (\r
-// VOID\r
-// );\r
-ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, x0)\r
- ldrh w0, [x0]\r
- ret\r
-\r
-//UINTN\r
-//ArmPlatformIsPrimaryCore (\r
-// IN UINTN MpId\r
-// );\r
-ASM_PFX(ArmPlatformIsPrimaryCore):\r
- mov x0, #1\r
- ret\r
-\r
-//UINTN\r
-//ArmPlatformGetCorePosition (\r
-// IN UINTN MpId\r
-// );\r
-// With this function: CorePos = (ClusterId * 4) + CoreId\r
-ASM_PFX(ArmPlatformGetCorePosition):\r
- and x1, x0, #ARM_CORE_MASK\r
- and x0, x0, #ARM_CLUSTER_MASK\r
- add x0, x1, x0, LSR #6\r
- ret\r
-\r
-//EFI_PHYSICAL_ADDRESS\r
-//GetPhysAddrTop (\r
-// VOID\r
-// );\r
-ASM_PFX(ArmGetPhysAddrTop):\r
- mrs x0, id_aa64mmfr0_el1\r
- adr x1, .LPARanges\r
- and x0, x0, #7\r
- ldrb w1, [x1, x0]\r
- mov x0, #1\r
- lsl x0, x0, x1\r
- ret\r
-\r
-//\r
-// Bits 0..2 of the AA64MFR0_EL1 system register encode the size of the\r
-// physical address space support on this CPU:\r
-// 0 == 32 bits, 1 == 36 bits, etc etc\r
-// 6 and 7 are reserved\r
-//\r
-.LPARanges:\r
- .byte 32, 36, 40, 42, 44, 48, -1, -1\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
+++ /dev/null
-#/* @file\r
-# Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#*/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = ArmXenRelocatablePlatformLib\r
- FILE_GUID = c8602718-4faa-4119-90ca-cae72509ac4c\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmPlatformLib|SEC PEIM\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
- ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationPkg.dec\r
-\r
-[LibraryClasses]\r
- IoLib\r
- ArmLib\r
- PrintLib\r
-\r
-[Sources.common]\r
- RelocatableVirt.c\r
- XenVirtMem.c\r
-\r
-[Sources.AARCH64]\r
- AARCH64/RelocatableVirtHelper.S\r
- AARCH64/MemnodeParser.S\r
-\r
-[FeaturePcd]\r
- gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec\r
-\r
-[PatchPcd]\r
- gArmVirtualizationTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress\r
- gArmTokenSpaceGuid.PcdFdBaseAddress\r
- gArmTokenSpaceGuid.PcdFvBaseAddress\r
- gArmTokenSpaceGuid.PcdSystemMemoryBase\r
- gArmTokenSpaceGuid.PcdSystemMemorySize\r
-\r
-[FixedPcd]\r
- gArmPlatformTokenSpaceGuid.PcdCoreCount\r
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
- gArmTokenSpaceGuid.PcdArmPrimaryCore\r
- gArmTokenSpaceGuid.PcdFdSize\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-* Copyright (c) 2014, Linaro Limited. All rights reserved.\r
-* Copyright (c) 2014, Red Hat, Inc.\r
-*\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Library/IoLib.h>\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <ArmPlatform.h>\r
-#include <Pi/PiBootMode.h>\r
-\r
-/**\r
- Return the current Boot Mode\r
-\r
- This function returns the boot reason on the platform\r
-\r
- @return Return the current Boot Mode of the platform\r
-\r
-**/\r
-EFI_BOOT_MODE\r
-ArmPlatformGetBootMode (\r
- VOID\r
- )\r
-{\r
- return BOOT_WITH_FULL_CONFIGURATION;\r
-}\r
-\r
-/**\r
- This function is called by PrePeiCore, in the SEC phase.\r
-**/\r
-RETURN_STATUS\r
-ArmPlatformInitialize (\r
- IN UINTN MpId\r
- )\r
-{\r
- //\r
- // We are relying on ArmPlatformInitializeSystemMemory () being called from\r
- // InitializeMemory (), which only occurs if the following feature is disabled\r
- //\r
- ASSERT (!FeaturePcdGet (PcdSystemMemoryInitializeInSec));\r
- return RETURN_SUCCESS;\r
-}\r
-\r
-VOID\r
-ArmPlatformInitializeSystemMemory (\r
- VOID\r
- )\r
-{\r
-}\r
-\r
-VOID\r
-ArmPlatformGetPlatformPpiList (\r
- OUT UINTN *PpiListSize,\r
- OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r
- )\r
-{\r
- *PpiListSize = 0;\r
- *PpiList = NULL;\r
-}\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2014, Linaro Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <ArmPlatform.h>\r
-\r
-// Number of Virtual Memory Map Descriptors\r
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 2\r
-\r
-// DDR attributes\r
-#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
-#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
-\r
-EFI_PHYSICAL_ADDRESS\r
-ArmGetPhysAddrTop (\r
- VOID\r
- );\r
-\r
-/**\r
- Return the Virtual Memory Map of your platform\r
-\r
- This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU\r
- on your platform.\r
-\r
- @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR\r
- describing a Physical-to-Virtual Memory\r
- mapping. This array must be ended by a\r
- zero-filled entry\r
-\r
-**/\r
-VOID\r
-ArmPlatformGetVirtualMemoryMap (\r
- IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap\r
- )\r
-{\r
- ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r
-\r
- ASSERT (VirtualMemoryMap != NULL);\r
-\r
- VirtualMemoryTable = AllocatePages (\r
- EFI_SIZE_TO_PAGES (\r
- sizeof (ARM_MEMORY_REGION_DESCRIPTOR)\r
- * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS\r
- )\r
- );\r
-\r
- if (VirtualMemoryTable == NULL) {\r
- DEBUG ((EFI_D_ERROR, "%a: Error: Failed AllocatePages()\n", __FUNCTION__));\r
- return;\r
- }\r
-\r
- //\r
- // Map the entire physical memory space as cached. The only device\r
- // we care about is the GIC, which will be stage 2 mapped as a device\r
- // by the hypervisor, which will override the cached mapping we install\r
- // here.\r
- //\r
- VirtualMemoryTable[0].PhysicalBase = 0x0;\r
- VirtualMemoryTable[0].VirtualBase = 0x0;\r
- VirtualMemoryTable[0].Length = ArmGetPhysAddrTop ();\r
- VirtualMemoryTable[0].Attributes = DDR_ATTRIBUTES_CACHED;\r
-\r
- // End of Table\r
- ZeroMem (&VirtualMemoryTable[1], sizeof (ARM_MEMORY_REGION_DESCRIPTOR));\r
-\r
- *VirtualMemoryMap = VirtualMemoryTable;\r
-}\r
+++ /dev/null
-## @file\r
-# Instance of PCI Express Library using the 256 MB PCI Express MMIO window.\r
-#\r
-# PCI Express Library that uses the 256 MB PCI Express MMIO window to perform\r
-# PCI Configuration cycles. Layers on top of an I/O Library instance.\r
-#\r
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-##\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = BaseCachingPciExpressLib\r
- FILE_GUID = 3f3ffd80-04dc-4a2b-9d25-ecca55c2e520\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PciExpressLib|DXE_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
- CONSTRUCTOR = PciExpressLibInitialize\r
-\r
-#\r
-# VALID_ARCHITECTURES = ARM AARCH64\r
-#\r
-\r
-[Sources]\r
- PciExpressLib.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
-\r
-[LibraryClasses]\r
- BaseLib\r
- PcdLib\r
- DebugLib\r
- IoLib\r
-\r
-[Pcd]\r
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES\r
-\r
+++ /dev/null
-/** @file\r
- Functions in this library instance make use of MMIO functions in IoLib to\r
- access memory mapped PCI configuration space.\r
-\r
- All assertions for I/O operations are handled in MMIO functions in the IoLib\r
- Library.\r
-\r
- Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-\r
-#include <Base.h>\r
-\r
-#include <Library/BaseLib.h>\r
-#include <Library/PciExpressLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/PcdLib.h>\r
-\r
-\r
-/**\r
- Assert the validity of a PCI address. A valid PCI address should contain 1's\r
- only in the low 28 bits.\r
-\r
- @param A The address to validate.\r
-\r
-**/\r
-#define ASSERT_INVALID_PCI_ADDRESS(A) \\r
- ASSERT (((A) & ~0xfffffff) == 0)\r
-\r
-/**\r
- Registers a PCI device so PCI configuration registers may be accessed after\r
- SetVirtualAddressMap().\r
-\r
- Registers the PCI device specified by Address so all the PCI configuration\r
- registers associated with that PCI device may be accessed after SetVirtualAddressMap()\r
- is called.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address The address that encodes the PCI Bus, Device, Function and\r
- Register.\r
-\r
- @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r
- @retval RETURN_UNSUPPORTED An attempt was made to call this function\r
- after ExitBootServices().\r
- @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r
- at runtime could not be mapped.\r
- @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r
- complete the registration.\r
-\r
-**/\r
-RETURN_STATUS\r
-EFIAPI\r
-PciExpressRegisterForRuntimeAccess (\r
- IN UINTN Address\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return RETURN_UNSUPPORTED;\r
-}\r
-\r
-STATIC UINT64 mPciExpressBaseAddress;\r
-\r
-RETURN_STATUS\r
-EFIAPI\r
-PciExpressLibInitialize (\r
- VOID\r
- )\r
-{\r
- mPciExpressBaseAddress = PcdGet64 (PcdPciExpressBaseAddress);\r
- return RETURN_SUCCESS;\r
-}\r
-\r
-\r
-/**\r
- Gets the base address of PCI Express.\r
-\r
- @return The base address of PCI Express.\r
-\r
-**/\r
-VOID*\r
-GetPciExpressBaseAddress (\r
- VOID\r
- )\r
-{\r
- return (VOID*)(UINTN) mPciExpressBaseAddress;\r
-}\r
-\r
-/**\r
- Reads an 8-bit PCI configuration register.\r
-\r
- Reads and returns the 8-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address The address that encodes the PCI Bus, Device, Function and\r
- Register.\r
-\r
- @return The read value from the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciExpressRead8 (\r
- IN UINTN Address\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioRead8 ((UINTN) GetPciExpressBaseAddress () + Address);\r
-}\r
-\r
-/**\r
- Writes an 8-bit PCI configuration register.\r
-\r
- Writes the 8-bit PCI configuration register specified by Address with the\r
- value specified by Value. Value is returned. This function must guarantee\r
- that all PCI read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address The address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param Value The value to write.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciExpressWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r
-}\r
-\r
-/**\r
- Performs a bitwise OR of an 8-bit PCI configuration register with\r
- an 8-bit value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 8-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address The address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciExpressOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioOr8 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
- value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 8-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address The address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciExpressAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioAnd8 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
- value, followed a bitwise OR with another 8-bit value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise OR between the result of the AND operation and\r
- the value specified by OrData, and writes the result to the 8-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address The address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciExpressAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioAndThenOr8 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
- AndData,\r
- OrData\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field of a PCI configuration register.\r
-\r
- Reads the bit field in an 8-bit PCI configuration register. The bit field is\r
- specified by the StartBit and the EndBit. The value of the bit field is\r
- returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address The PCI configuration register to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
-\r
- @return The value of the bit field read from the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciExpressBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioBitFieldRead8 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
- StartBit,\r
- EndBit\r
- );\r
-}\r
-\r
-/**\r
- Writes a bit field to a PCI configuration register.\r
-\r
- Writes Value to the bit field of the PCI configuration register. The bit\r
- field is specified by the StartBit and the EndBit. All other bits in the\r
- destination PCI configuration register are preserved. The new value of the\r
- 8-bit register is returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address The PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param Value The new value of the bit field.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciExpressBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioBitFieldWrite8 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
- StartBit,\r
- EndBit,\r
- Value\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r
- writes the result back to the bit field in the 8-bit port.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 8-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized. Extra left bits in OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address The PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciExpressBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioBitFieldOr8 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
- StartBit,\r
- EndBit,\r
- OrData\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r
- AND, and writes the result back to the bit field in the 8-bit register.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 8-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized. Extra left bits in AndData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address The PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciExpressBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioBitFieldAnd8 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
- StartBit,\r
- EndBit,\r
- AndData\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
- bitwise OR, and writes the result back to the bit field in the\r
- 8-bit port.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise OR between the read result and\r
- the value specified by AndData, and writes the result to the 8-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized. Extra left bits in both AndData and\r
- OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address The PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciExpressBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioBitFieldAndThenOr8 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
- StartBit,\r
- EndBit,\r
- AndData,\r
- OrData\r
- );\r
-}\r
-\r
-/**\r
- Reads a 16-bit PCI configuration register.\r
-\r
- Reads and returns the 16-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
-\r
- @param Address The address that encodes the PCI Bus, Device, Function and\r
- Register.\r
-\r
- @return The read value from the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciExpressRead16 (\r
- IN UINTN Address\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioRead16 ((UINTN) GetPciExpressBaseAddress () + Address);\r
-}\r
-\r
-/**\r
- Writes a 16-bit PCI configuration register.\r
-\r
- Writes the 16-bit PCI configuration register specified by Address with the\r
- value specified by Value. Value is returned. This function must guarantee\r
- that all PCI read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
-\r
- @param Address The address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param Value The value to write.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciExpressWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioWrite16 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r
-}\r
-\r
-/**\r
- Performs a bitwise OR of a 16-bit PCI configuration register with\r
- a 16-bit value.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 16-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
-\r
- @param Address The address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciExpressOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
- value.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 16-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
-\r
- @param Address The address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciExpressAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioAnd16 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
- value, followed a bitwise OR with another 16-bit value.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise OR between the result of the AND operation and\r
- the value specified by OrData, and writes the result to the 16-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
-\r
- @param Address The address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciExpressAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioAndThenOr16 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
- AndData,\r
- OrData\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field of a PCI configuration register.\r
-\r
- Reads the bit field in a 16-bit PCI configuration register. The bit field is\r
- specified by the StartBit and the EndBit. The value of the bit field is\r
- returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address The PCI configuration register to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
-\r
- @return The value of the bit field read from the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciExpressBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioBitFieldRead16 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
- StartBit,\r
- EndBit\r
- );\r
-}\r
-\r
-/**\r
- Writes a bit field to a PCI configuration register.\r
-\r
- Writes Value to the bit field of the PCI configuration register. The bit\r
- field is specified by the StartBit and the EndBit. All other bits in the\r
- destination PCI configuration register are preserved. The new value of the\r
- 16-bit register is returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address The PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param Value The new value of the bit field.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciExpressBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioBitFieldWrite16 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
- StartBit,\r
- EndBit,\r
- Value\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r
- writes the result back to the bit field in the 16-bit port.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 16-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized. Extra left bits in OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address The PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciExpressBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioBitFieldOr16 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
- StartBit,\r
- EndBit,\r
- OrData\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r
- AND, and writes the result back to the bit field in the 16-bit register.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 16-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized. Extra left bits in AndData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address The PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciExpressBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioBitFieldAnd16 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
- StartBit,\r
- EndBit,\r
- AndData\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r
- bitwise OR, and writes the result back to the bit field in the\r
- 16-bit port.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise OR between the read result and\r
- the value specified by AndData, and writes the result to the 16-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized. Extra left bits in both AndData and\r
- OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address The PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciExpressBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioBitFieldAndThenOr16 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
- StartBit,\r
- EndBit,\r
- AndData,\r
- OrData\r
- );\r
-}\r
-\r
-/**\r
- Reads a 32-bit PCI configuration register.\r
-\r
- Reads and returns the 32-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
-\r
- @param Address The address that encodes the PCI Bus, Device, Function and\r
- Register.\r
-\r
- @return The read value from the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciExpressRead32 (\r
- IN UINTN Address\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Address);\r
-}\r
-\r
-/**\r
- Writes a 32-bit PCI configuration register.\r
-\r
- Writes the 32-bit PCI configuration register specified by Address with the\r
- value specified by Value. Value is returned. This function must guarantee\r
- that all PCI read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
-\r
- @param Address The address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param Value The value to write.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciExpressWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r
-}\r
-\r
-/**\r
- Performs a bitwise OR of a 32-bit PCI configuration register with\r
- a 32-bit value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 32-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
-\r
- @param Address The address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciExpressOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
- value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 32-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
-\r
- @param Address The address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciExpressAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
- value, followed a bitwise OR with another 32-bit value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise OR between the result of the AND operation and\r
- the value specified by OrData, and writes the result to the 32-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
-\r
- @param Address The address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciExpressAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioAndThenOr32 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
- AndData,\r
- OrData\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field of a PCI configuration register.\r
-\r
- Reads the bit field in a 32-bit PCI configuration register. The bit field is\r
- specified by the StartBit and the EndBit. The value of the bit field is\r
- returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address The PCI configuration register to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
-\r
- @return The value of the bit field read from the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciExpressBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioBitFieldRead32 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
- StartBit,\r
- EndBit\r
- );\r
-}\r
-\r
-/**\r
- Writes a bit field to a PCI configuration register.\r
-\r
- Writes Value to the bit field of the PCI configuration register. The bit\r
- field is specified by the StartBit and the EndBit. All other bits in the\r
- destination PCI configuration register are preserved. The new value of the\r
- 32-bit register is returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address The PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param Value The new value of the bit field.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciExpressBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioBitFieldWrite32 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
- StartBit,\r
- EndBit,\r
- Value\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r
- writes the result back to the bit field in the 32-bit port.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 32-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized. Extra left bits in OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address The PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciExpressBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioBitFieldOr32 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
- StartBit,\r
- EndBit,\r
- OrData\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r
- AND, and writes the result back to the bit field in the 32-bit register.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 32-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized. Extra left bits in AndData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address The PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciExpressBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioBitFieldAnd32 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
- StartBit,\r
- EndBit,\r
- AndData\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r
- bitwise OR, and writes the result back to the bit field in the\r
- 32-bit port.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise OR between the read result and\r
- the value specified by AndData, and writes the result to the 32-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized. Extra left bits in both AndData and\r
- OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address The PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciExpressBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return MmioBitFieldAndThenOr32 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
- StartBit,\r
- EndBit,\r
- AndData,\r
- OrData\r
- );\r
-}\r
-\r
-/**\r
- Reads a range of PCI configuration registers into a caller supplied buffer.\r
-\r
- Reads the range of PCI configuration registers specified by StartAddress and\r
- Size into the buffer specified by Buffer. This function only allows the PCI\r
- configuration registers from a single PCI function to be read. Size is\r
- returned. When possible 32-bit PCI configuration read cycles are used to read\r
- from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
- and 16-bit PCI configuration read cycles may be used at the beginning and the\r
- end of the range.\r
-\r
- If StartAddress > 0x0FFFFFFF, then ASSERT().\r
- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
- If Size > 0 and Buffer is NULL, then ASSERT().\r
-\r
- @param StartAddress The starting address that encodes the PCI Bus, Device,\r
- Function and Register.\r
- @param Size The size in bytes of the transfer.\r
- @param Buffer The pointer to a buffer receiving the data read.\r
-\r
- @return Size read data from StartAddress.\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-PciExpressReadBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- UINTN ReturnValue;\r
-\r
- ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
-\r
- if (Size == 0) {\r
- return Size;\r
- }\r
-\r
- ASSERT (Buffer != NULL);\r
-\r
- //\r
- // Save Size for return\r
- //\r
- ReturnValue = Size;\r
-\r
- if ((StartAddress & 1) != 0) {\r
- //\r
- // Read a byte if StartAddress is byte aligned\r
- //\r
- *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
- //\r
- // Read a word if StartAddress is word aligned\r
- //\r
- WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r
-\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- while (Size >= sizeof (UINT32)) {\r
- //\r
- // Read as many double words as possible\r
- //\r
- WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));\r
-\r
- StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16)) {\r
- //\r
- // Read the last remaining word if exist\r
- //\r
- WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT8)) {\r
- //\r
- // Read the last remaining byte if exist\r
- //\r
- *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r
- }\r
-\r
- return ReturnValue;\r
-}\r
-\r
-/**\r
- Copies the data in a caller supplied buffer to a specified range of PCI\r
- configuration space.\r
-\r
- Writes the range of PCI configuration registers specified by StartAddress and\r
- Size from the buffer specified by Buffer. This function only allows the PCI\r
- configuration registers from a single PCI function to be written. Size is\r
- returned. When possible 32-bit PCI configuration write cycles are used to\r
- write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
- 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
- and the end of the range.\r
-\r
- If StartAddress > 0x0FFFFFFF, then ASSERT().\r
- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
- If Size > 0 and Buffer is NULL, then ASSERT().\r
-\r
- @param StartAddress The starting address that encodes the PCI Bus, Device,\r
- Function and Register.\r
- @param Size The size in bytes of the transfer.\r
- @param Buffer The pointer to a buffer containing the data to write.\r
-\r
- @return Size written to StartAddress.\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-PciExpressWriteBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
- )\r
-{\r
- UINTN ReturnValue;\r
-\r
- ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
-\r
- if (Size == 0) {\r
- return 0;\r
- }\r
-\r
- ASSERT (Buffer != NULL);\r
-\r
- //\r
- // Save Size for return\r
- //\r
- ReturnValue = Size;\r
-\r
- if ((StartAddress & 1) != 0) {\r
- //\r
- // Write a byte if StartAddress is byte aligned\r
- //\r
- PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
- //\r
- // Write a word if StartAddress is word aligned\r
- //\r
- PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- while (Size >= sizeof (UINT32)) {\r
- //\r
- // Write as many double words as possible\r
- //\r
- PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));\r
- StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16)) {\r
- //\r
- // Write the last remaining word if exist\r
- //\r
- PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT8)) {\r
- //\r
- // Write the last remaining byte if exist\r
- //\r
- PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r
- }\r
-\r
- return ReturnValue;\r
-}\r
+++ /dev/null
-/** @file\r
- Serial I/O Port library functions with base address discovered from FDT\r
-\r
- Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
- Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.<BR>\r
- Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <Base.h>\r
-\r
-#include <Library/PcdLib.h>\r
-#include <Library/SerialPortLib.h>\r
-#include <Library/SerialPortExtLib.h>\r
-#include <libfdt.h>\r
-\r
-#include <Drivers/PL011Uart.h>\r
-\r
-RETURN_STATUS\r
-EFIAPI\r
-SerialPortInitialize (\r
- VOID\r
- )\r
-{\r
- //\r
- // This SerialPortInitialize() function is completely empty, for a number of\r
- // reasons:\r
- // - if we are executing from flash, it is hard to keep state (i.e., store the\r
- // discovered base address in a global), and the most robust way to deal\r
- // with this is to discover the base address at every Write ();\r
- // - calls to the Write() function in this module may be issued before this\r
- // initialization function is called: this is not a problem when the base\r
- // address of the UART is hardcoded, and only the baud rate may be wrong,\r
- // but if we don't know the base address yet, we may be poking into memory\r
- // that does not tolerate being poked into;\r
- // - SEC and PEI phases produce debug output only, so with debug disabled, no\r
- // initialization (or device tree parsing) is performed at all.\r
- //\r
- // Note that this means that on *every* Write () call, the device tree will be\r
- // parsed and the UART re-initialized. However, this is a small price to pay\r
- // for having serial debug output on a UART with no fixed base address.\r
- //\r
- return RETURN_SUCCESS;\r
-}\r
-\r
-STATIC\r
-UINT64\r
-SerialPortGetBaseAddress (\r
- VOID\r
- )\r
-{\r
- UINT64 BaudRate;\r
- UINT32 ReceiveFifoDepth;\r
- EFI_PARITY_TYPE Parity;\r
- UINT8 DataBits;\r
- EFI_STOP_BITS_TYPE StopBits;\r
- VOID *DeviceTreeBase;\r
- INT32 Node, Prev;\r
- INT32 Len;\r
- CONST CHAR8 *Compatible;\r
- CONST CHAR8 *CompatibleItem;\r
- CONST UINT64 *RegProperty;\r
- UINTN UartBase;\r
- RETURN_STATUS Status;\r
-\r
- DeviceTreeBase = (VOID *)(UINTN)FixedPcdGet64 (PcdDeviceTreeInitialBaseAddress);\r
-\r
- if ((DeviceTreeBase == NULL) || (fdt_check_header (DeviceTreeBase) != 0)) {\r
- return 0;\r
- }\r
-\r
- //\r
- // Enumerate all FDT nodes looking for a PL011 and capture its base address\r
- //\r
- for (Prev = 0;; Prev = Node) {\r
- Node = fdt_next_node (DeviceTreeBase, Prev, NULL);\r
- if (Node < 0) {\r
- break;\r
- }\r
-\r
- Compatible = fdt_getprop (DeviceTreeBase, Node, "compatible", &Len);\r
- if (Compatible == NULL) {\r
- continue;\r
- }\r
-\r
- //\r
- // Iterate over the NULL-separated items in the compatible string\r
- //\r
- for (CompatibleItem = Compatible; CompatibleItem < Compatible + Len;\r
- CompatibleItem += 1 + AsciiStrLen (CompatibleItem)) {\r
-\r
- if (AsciiStrCmp (CompatibleItem, "arm,pl011") == 0) {\r
- RegProperty = fdt_getprop (DeviceTreeBase, Node, "reg", &Len);\r
- if (Len != 16) {\r
- return 0;\r
- }\r
- UartBase = (UINTN)fdt64_to_cpu (ReadUnaligned64 (RegProperty));\r
-\r
- BaudRate = (UINTN)FixedPcdGet64 (PcdUartDefaultBaudRate);\r
- ReceiveFifoDepth = 0; // Use the default value for Fifo depth\r
- Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);\r
- DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);\r
- StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);\r
-\r
- Status = PL011UartInitializePort (\r
- UartBase,\r
- &BaudRate, &ReceiveFifoDepth, &Parity, &DataBits, &StopBits);\r
- if (!EFI_ERROR (Status)) {\r
- return UartBase;\r
- }\r
- }\r
- }\r
- }\r
- return 0;\r
-}\r
-\r
-/**\r
- Write data to serial device.\r
-\r
- @param Buffer Point of data buffer which need to be written.\r
- @param NumberOfBytes Number of output bytes which are cached in Buffer.\r
-\r
- @retval 0 Write data failed.\r
- @retval !0 Actual number of bytes written to serial device.\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-SerialPortWrite (\r
- IN UINT8 *Buffer,\r
- IN UINTN NumberOfBytes\r
- )\r
-{\r
- UINT64 SerialRegisterBase;\r
-\r
- SerialRegisterBase = SerialPortGetBaseAddress ();\r
- if (SerialRegisterBase != 0) {\r
- return PL011UartWrite ((UINTN)SerialRegisterBase, Buffer, NumberOfBytes);\r
- }\r
- return 0;\r
-}\r
-\r
-/**\r
- Read data from serial device and save the data in buffer.\r
-\r
- @param Buffer Point of data buffer which need to be written.\r
- @param NumberOfBytes Size of Buffer[].\r
-\r
- @retval 0 Read data failed.\r
- @retval !0 Actual number of bytes read from serial device.\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-SerialPortRead (\r
- OUT UINT8 *Buffer,\r
- IN UINTN NumberOfBytes\r
-)\r
-{\r
- return 0;\r
-}\r
-\r
-/**\r
- Check to see if any data is available to be read from the debug device.\r
-\r
- @retval TRUE At least one byte of data is available to be read\r
- @retval FALSE No data is available to be read\r
-\r
-**/\r
-BOOLEAN\r
-EFIAPI\r
-SerialPortPoll (\r
- VOID\r
- )\r
-{\r
- return FALSE;\r
-}\r
+++ /dev/null
-#/** @file\r
-#\r
-# Component description file for EarlyFdtPL011SerialPortLib module\r
-#\r
-# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = EarlyFdtPL011SerialPortLib\r
- FILE_GUID = 0983616A-49BC-4732-B531-4AF98D2056F0\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = SerialPortLib|SEC PEI_CORE PEIM\r
-\r
-[Sources.common]\r
- EarlyFdtPL011SerialPortLib.c\r
-\r
-[LibraryClasses]\r
- PL011UartLib\r
- PcdLib\r
- FdtLib\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
- ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationPkg.dec\r
-\r
-[FixedPcd]\r
- gArmVirtualizationTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress\r
-\r
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate\r
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits\r
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity\r
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits\r
+++ /dev/null
-/** @file\r
- Serial I/O Port library functions with base address discovered from FDT\r
-\r
- Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
- Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.<BR>\r
- Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
- Copyright (c) 2014, Red Hat, Inc.<BR>\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <Base.h>\r
-\r
-#include <Library/PcdLib.h>\r
-#include <Library/SerialPortLib.h>\r
-#include <Pi/PiBootMode.h>\r
-#include <Uefi/UefiBaseType.h>\r
-#include <Uefi/UefiMultiPhase.h>\r
-#include <Pi/PiHob.h>\r
-#include <Library/HobLib.h>\r
-#include <Guid/EarlyPL011BaseAddress.h>\r
-\r
-#include <Drivers/PL011Uart.h>\r
-\r
-STATIC UINTN mSerialBaseAddress;\r
-\r
-RETURN_STATUS\r
-EFIAPI\r
-SerialPortInitialize (\r
- VOID\r
- )\r
-{\r
- return RETURN_SUCCESS;\r
-}\r
-\r
-/**\r
-\r
- Program hardware of Serial port\r
-\r
- @return RETURN_NOT_FOUND if no PL011 base address could be found\r
- Otherwise, result of PL011UartInitializePort () is returned\r
-\r
-**/\r
-RETURN_STATUS\r
-EFIAPI\r
-FdtPL011SerialPortLibInitialize (\r
- VOID\r
- )\r
-{\r
- VOID *Hob;\r
- CONST UINT64 *UartBase;\r
- UINT64 BaudRate;\r
- UINT32 ReceiveFifoDepth;\r
- EFI_PARITY_TYPE Parity;\r
- UINT8 DataBits;\r
- EFI_STOP_BITS_TYPE StopBits;\r
-\r
- Hob = GetFirstGuidHob (&gEarlyPL011BaseAddressGuid);\r
- if (Hob == NULL || GET_GUID_HOB_DATA_SIZE (Hob) != sizeof *UartBase) {\r
- return RETURN_NOT_FOUND;\r
- }\r
- UartBase = GET_GUID_HOB_DATA (Hob);\r
-\r
- mSerialBaseAddress = (UINTN)*UartBase;\r
- if (mSerialBaseAddress == 0) {\r
- return RETURN_NOT_FOUND;\r
- }\r
-\r
- BaudRate = (UINTN)PcdGet64 (PcdUartDefaultBaudRate);\r
- ReceiveFifoDepth = 0; // Use the default value for Fifo depth\r
- Parity = (EFI_PARITY_TYPE)PcdGet8 (PcdUartDefaultParity);\r
- DataBits = PcdGet8 (PcdUartDefaultDataBits);\r
- StopBits = (EFI_STOP_BITS_TYPE) PcdGet8 (PcdUartDefaultStopBits);\r
-\r
- return PL011UartInitializePort (\r
- mSerialBaseAddress, &BaudRate, &ReceiveFifoDepth,\r
- &Parity, &DataBits, &StopBits);\r
-}\r
-\r
-/**\r
- Write data to serial device.\r
-\r
- @param Buffer Point of data buffer which need to be written.\r
- @param NumberOfBytes Number of output bytes which are cached in Buffer.\r
-\r
- @retval 0 Write data failed.\r
- @retval !0 Actual number of bytes written to serial device.\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-SerialPortWrite (\r
- IN UINT8 *Buffer,\r
- IN UINTN NumberOfBytes\r
- )\r
-{\r
- if (mSerialBaseAddress != 0) {\r
- return PL011UartWrite (mSerialBaseAddress, Buffer, NumberOfBytes);\r
- }\r
- return 0;\r
-}\r
-\r
-/**\r
- Read data from serial device and save the data in buffer.\r
-\r
- @param Buffer Point of data buffer which need to be written.\r
- @param NumberOfBytes Number of output bytes which are cached in Buffer.\r
-\r
- @retval 0 Read data failed.\r
- @retval !0 Actual number of bytes read from serial device.\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-SerialPortRead (\r
- OUT UINT8 *Buffer,\r
- IN UINTN NumberOfBytes\r
-)\r
-{\r
- if (mSerialBaseAddress != 0) {\r
- return PL011UartRead (mSerialBaseAddress, Buffer, NumberOfBytes);\r
- }\r
- return 0;\r
-}\r
-\r
-/**\r
- Check to see if any data is available to be read from the debug device.\r
-\r
- @retval TRUE At least one byte of data is available to be read\r
- @retval FALSE No data is available to be read\r
-\r
-**/\r
-BOOLEAN\r
-EFIAPI\r
-SerialPortPoll (\r
- VOID\r
- )\r
-{\r
- if (mSerialBaseAddress != 0) {\r
- return PL011UartPoll (mSerialBaseAddress);\r
- }\r
- return FALSE;\r
-}\r
+++ /dev/null
-#/** @file\r
-#\r
-# Component description file for PL011SerialPortLib module\r
-#\r
-# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = FdtPL011SerialPortLib\r
- FILE_GUID = CB768406-7DE6-49B6-BC2C-F324E110DE5A\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = SerialPortLib|DXE_CORE DXE_DRIVER UEFI_DRIVER DXE_RUNTIME_DRIVER UEFI_APPLICATION\r
- CONSTRUCTOR = FdtPL011SerialPortLibInitialize\r
-\r
-[Sources.common]\r
- FdtPL011SerialPortLib.c\r
-\r
-[LibraryClasses]\r
- PL011UartLib\r
- HobLib\r
-\r
-[Packages]\r
- EmbeddedPkg/EmbeddedPkg.dec\r
- MdePkg/MdePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
- ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationPkg.dec\r
- ArmPkg/ArmPkg.dec\r
-\r
-[FixedPcd]\r
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate\r
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits\r
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity\r
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits\r
-\r
-[Guids]\r
- gEarlyPL011BaseAddressGuid\r
+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
- **/\r
-\r
-#include <ArmPlatform.h>\r
-#include <Library/NorFlashPlatformLib.h>\r
-\r
-EFI_STATUS\r
-NorFlashPlatformInitialization (\r
- VOID\r
- )\r
-{\r
- return EFI_SUCCESS;\r
-}\r
-\r
-NOR_FLASH_DESCRIPTION mNorFlashDevices[] = {\r
- {\r
- QEMU_NOR0_BASE,\r
- QEMU_NOR0_BASE,\r
- QEMU_NOR0_SIZE,\r
- QEMU_NOR_BLOCK_SIZE,\r
- {0xF9B94AE2, 0x8BA6, 0x409B, {0x9D, 0x56, 0xB9, 0xB4, 0x17, 0xF5, 0x3C, 0xB3}}\r
- }, {\r
- QEMU_NOR1_BASE,\r
- QEMU_NOR1_BASE,\r
- QEMU_NOR1_SIZE,\r
- QEMU_NOR_BLOCK_SIZE,\r
- {0x8047DB4B, 0x7E9C, 0x4C0C, {0x8E, 0xBC, 0xDF, 0xBB, 0xAA, 0xCA, 0xCE, 0x8F}}\r
- }\r
-};\r
-\r
-EFI_STATUS\r
-NorFlashPlatformGetDevices (\r
- OUT NOR_FLASH_DESCRIPTION **NorFlashDescriptions,\r
- OUT UINT32 *Count\r
- )\r
-{\r
- *NorFlashDescriptions = mNorFlashDevices;\r
- *Count = sizeof (mNorFlashDevices) / sizeof (mNorFlashDevices[0]);\r
- return EFI_SUCCESS;\r
-}\r
+++ /dev/null
-#/** @file\r
-#\r
-# Component description file for NorFlashQemuLib module\r
-#\r
-# Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = NorFlashQemuLib\r
- FILE_GUID = 339B7829-4C5F-4EFC-B2DD-5050E530DECE\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = NorFlashPlatformLib\r
-\r
-[Sources.common]\r
- NorFlashQemuLib.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
+++ /dev/null
-/** @file\r
- Implementation for PlatformBdsLib library class interfaces.\r
-\r
- Copyright (C) 2015, Red Hat, Inc.\r
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>\r
- Copyright (c) 2004 - 2008, Intel Corporation. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials are licensed and made available\r
- under the terms and conditions of the BSD License which accompanies this\r
- distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
- WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <IndustryStandard/Pci22.h>\r
-#include <Library/DevicePathLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/PlatformBdsLib.h>\r
-#include <Library/QemuBootOrderLib.h>\r
-#include <Protocol/DevicePath.h>\r
-#include <Protocol/GraphicsOutput.h>\r
-#include <Protocol/PciIo.h>\r
-#include <Protocol/PciRootBridgeIo.h>\r
-\r
-#include "IntelBdsPlatform.h"\r
-\r
-#define DP_NODE_LEN(Type) { (UINT8)sizeof (Type), (UINT8)(sizeof (Type) >> 8) }\r
-\r
-\r
-#pragma pack (1)\r
-typedef struct {\r
- VENDOR_DEVICE_PATH SerialDxe;\r
- UART_DEVICE_PATH Uart;\r
- VENDOR_DEFINED_DEVICE_PATH Vt100;\r
- EFI_DEVICE_PATH_PROTOCOL End;\r
-} PLATFORM_SERIAL_CONSOLE;\r
-#pragma pack ()\r
-\r
-#define SERIAL_DXE_FILE_GUID { \\r
- 0xD3987D4B, 0x971A, 0x435F, \\r
- { 0x8C, 0xAF, 0x49, 0x67, 0xEB, 0x62, 0x72, 0x41 } \\r
- }\r
-\r
-STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = {\r
- //\r
- // VENDOR_DEVICE_PATH SerialDxe\r
- //\r
- {\r
- { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH) },\r
- SERIAL_DXE_FILE_GUID\r
- },\r
-\r
- //\r
- // UART_DEVICE_PATH Uart\r
- //\r
- {\r
- { MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) },\r
- 0, // Reserved\r
- FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate\r
- FixedPcdGet8 (PcdUartDefaultDataBits), // DataBits\r
- FixedPcdGet8 (PcdUartDefaultParity), // Parity\r
- FixedPcdGet8 (PcdUartDefaultStopBits) // StopBits\r
- },\r
-\r
- //\r
- // VENDOR_DEFINED_DEVICE_PATH Vt100\r
- //\r
- {\r
- {\r
- MESSAGING_DEVICE_PATH, MSG_VENDOR_DP,\r
- DP_NODE_LEN (VENDOR_DEFINED_DEVICE_PATH)\r
- },\r
- EFI_VT_100_GUID\r
- },\r
-\r
- //\r
- // EFI_DEVICE_PATH_PROTOCOL End\r
- //\r
- {\r
- END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
- DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL)\r
- }\r
-};\r
-\r
-\r
-#pragma pack (1)\r
-typedef struct {\r
- USB_CLASS_DEVICE_PATH Keyboard;\r
- EFI_DEVICE_PATH_PROTOCOL End;\r
-} PLATFORM_USB_KEYBOARD;\r
-#pragma pack ()\r
-\r
-STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard = {\r
- //\r
- // USB_CLASS_DEVICE_PATH Keyboard\r
- //\r
- {\r
- {\r
- MESSAGING_DEVICE_PATH, MSG_USB_CLASS_DP,\r
- DP_NODE_LEN (USB_CLASS_DEVICE_PATH)\r
- },\r
- 0xFFFF, // VendorId: any\r
- 0xFFFF, // ProductId: any\r
- 3, // DeviceClass: HID\r
- 1, // DeviceSubClass: boot\r
- 1 // DeviceProtocol: keyboard\r
- },\r
-\r
- //\r
- // EFI_DEVICE_PATH_PROTOCOL End\r
- //\r
- {\r
- END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
- DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL)\r
- }\r
-};\r
-\r
-\r
-//\r
-// BDS Platform Functions\r
-//\r
-/**\r
- Platform Bds init. Include the platform firmware vendor, revision\r
- and so crc check.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-PlatformBdsInit (\r
- VOID\r
- )\r
-{\r
-}\r
-\r
-\r
-/**\r
- Check if the handle satisfies a particular condition.\r
-\r
- @param[in] Handle The handle to check.\r
- @param[in] ReportText A caller-allocated string passed in for reporting\r
- purposes. It must never be NULL.\r
-\r
- @retval TRUE The condition is satisfied.\r
- @retval FALSE Otherwise. This includes the case when the condition could not\r
- be fully evaluated due to an error.\r
-**/\r
-typedef\r
-BOOLEAN\r
-(EFIAPI *FILTER_FUNCTION) (\r
- IN EFI_HANDLE Handle,\r
- IN CONST CHAR16 *ReportText\r
- );\r
-\r
-\r
-/**\r
- Process a handle.\r
-\r
- @param[in] Handle The handle to process.\r
- @param[in] ReportText A caller-allocated string passed in for reporting\r
- purposes. It must never be NULL.\r
-**/\r
-typedef\r
-VOID\r
-(EFIAPI *CALLBACK_FUNCTION) (\r
- IN EFI_HANDLE Handle,\r
- IN CONST CHAR16 *ReportText\r
- );\r
-\r
-/**\r
- Locate all handles that carry the specified protocol, filter them with a\r
- callback function, and pass each handle that passes the filter to another\r
- callback.\r
-\r
- @param[in] ProtocolGuid The protocol to look for.\r
-\r
- @param[in] Filter The filter function to pass each handle to. If this\r
- parameter is NULL, then all handles are processed.\r
-\r
- @param[in] Process The callback function to pass each handle to that\r
- clears the filter.\r
-**/\r
-STATIC\r
-VOID\r
-FilterAndProcess (\r
- IN EFI_GUID *ProtocolGuid,\r
- IN FILTER_FUNCTION Filter OPTIONAL,\r
- IN CALLBACK_FUNCTION Process\r
- )\r
-{\r
- EFI_STATUS Status;\r
- EFI_HANDLE *Handles;\r
- UINTN NoHandles;\r
- UINTN Idx;\r
-\r
- Status = gBS->LocateHandleBuffer (ByProtocol, ProtocolGuid,\r
- NULL /* SearchKey */, &NoHandles, &Handles);\r
- if (EFI_ERROR (Status)) {\r
- //\r
- // This is not an error, just an informative condition.\r
- //\r
- DEBUG ((EFI_D_VERBOSE, "%a: %g: %r\n", __FUNCTION__, ProtocolGuid,\r
- Status));\r
- return;\r
- }\r
-\r
- ASSERT (NoHandles > 0);\r
- for (Idx = 0; Idx < NoHandles; ++Idx) {\r
- CHAR16 *DevicePathText;\r
- STATIC CHAR16 Fallback[] = L"<device path unavailable>";\r
-\r
- //\r
- // The ConvertDevicePathToText() function handles NULL input transparently.\r
- //\r
- DevicePathText = ConvertDevicePathToText (\r
- DevicePathFromHandle (Handles[Idx]),\r
- FALSE, // DisplayOnly\r
- FALSE // AllowShortcuts\r
- );\r
- if (DevicePathText == NULL) {\r
- DevicePathText = Fallback;\r
- }\r
-\r
- if (Filter == NULL || Filter (Handles[Idx], DevicePathText)) {\r
- Process (Handles[Idx], DevicePathText);\r
- }\r
-\r
- if (DevicePathText != Fallback) {\r
- FreePool (DevicePathText);\r
- }\r
- }\r
- gBS->FreePool (Handles);\r
-}\r
-\r
-\r
-/**\r
- This FILTER_FUNCTION checks if a handle corresponds to a PCI display device.\r
-**/\r
-STATIC\r
-BOOLEAN\r
-EFIAPI\r
-IsPciDisplay (\r
- IN EFI_HANDLE Handle,\r
- IN CONST CHAR16 *ReportText\r
- )\r
-{\r
- EFI_STATUS Status;\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
- PCI_TYPE00 Pci;\r
-\r
- Status = gBS->HandleProtocol (Handle, &gEfiPciIoProtocolGuid,\r
- (VOID**)&PciIo);\r
- if (EFI_ERROR (Status)) {\r
- //\r
- // This is not an error worth reporting.\r
- //\r
- return FALSE;\r
- }\r
-\r
- Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, 0 /* Offset */,\r
- sizeof Pci / sizeof (UINT32), &Pci);\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "%a: %s: %r\n", __FUNCTION__, ReportText, Status));\r
- return FALSE;\r
- }\r
-\r
- return IS_PCI_DISPLAY (&Pci);\r
-}\r
-\r
-\r
-/**\r
- This CALLBACK_FUNCTION attempts to connect a handle non-recursively, asking\r
- the matching driver to produce all first-level child handles.\r
-**/\r
-STATIC\r
-VOID\r
-EFIAPI\r
-Connect (\r
- IN EFI_HANDLE Handle,\r
- IN CONST CHAR16 *ReportText\r
- )\r
-{\r
- EFI_STATUS Status;\r
-\r
- Status = gBS->ConnectController (\r
- Handle, // ControllerHandle\r
- NULL, // DriverImageHandle\r
- NULL, // RemainingDevicePath -- produce all children\r
- FALSE // Recursive\r
- );\r
- DEBUG ((EFI_ERROR (Status) ? EFI_D_ERROR : EFI_D_VERBOSE, "%a: %s: %r\n",\r
- __FUNCTION__, ReportText, Status));\r
-}\r
-\r
-\r
-/**\r
- This CALLBACK_FUNCTION retrieves the EFI_DEVICE_PATH_PROTOCOL from the\r
- handle, and adds it to ConOut and ErrOut.\r
-**/\r
-STATIC\r
-VOID\r
-EFIAPI\r
-AddOutput (\r
- IN EFI_HANDLE Handle,\r
- IN CONST CHAR16 *ReportText\r
- )\r
-{\r
- EFI_STATUS Status;\r
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
-\r
- DevicePath = DevicePathFromHandle (Handle);\r
- if (DevicePath == NULL) {\r
- DEBUG ((EFI_D_ERROR, "%a: %s: handle %p: device path not found\n",\r
- __FUNCTION__, ReportText, Handle));\r
- return;\r
- }\r
-\r
- Status = BdsLibUpdateConsoleVariable (L"ConOut", DevicePath, NULL);\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "%a: %s: adding to ConOut: %r\n", __FUNCTION__,\r
- ReportText, Status));\r
- return;\r
- }\r
-\r
- Status = BdsLibUpdateConsoleVariable (L"ErrOut", DevicePath, NULL);\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "%a: %s: adding to ErrOut: %r\n", __FUNCTION__,\r
- ReportText, Status));\r
- return;\r
- }\r
-\r
- DEBUG ((EFI_D_VERBOSE, "%a: %s: added to ConOut and ErrOut\n", __FUNCTION__,\r
- ReportText));\r
-}\r
-\r
-\r
-/**\r
- The function will execute with as the platform policy, current policy\r
- is driven by boot mode. IBV/OEM can customize this code for their specific\r
- policy action.\r
-\r
- @param DriverOptionList The header of the driver option link list\r
- @param BootOptionList The header of the boot option link list\r
- @param ProcessCapsules A pointer to ProcessCapsules()\r
- @param BaseMemoryTest A pointer to BaseMemoryTest()\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-PlatformBdsPolicyBehavior (\r
- IN LIST_ENTRY *DriverOptionList,\r
- IN LIST_ENTRY *BootOptionList,\r
- IN PROCESS_CAPSULES ProcessCapsules,\r
- IN BASEM_MEMORY_TEST BaseMemoryTest\r
- )\r
-{\r
- //\r
- // Locate the PCI root bridges and make the PCI bus driver connect each,\r
- // non-recursively. This will produce a number of child handles with PciIo on\r
- // them.\r
- //\r
- FilterAndProcess (&gEfiPciRootBridgeIoProtocolGuid, NULL, Connect);\r
-\r
- //\r
- // Find all display class PCI devices (using the handles from the previous\r
- // step), and connect them non-recursively. This should produce a number of\r
- // child handles with GOPs on them.\r
- //\r
- FilterAndProcess (&gEfiPciIoProtocolGuid, IsPciDisplay, Connect);\r
-\r
- //\r
- // Now add the device path of all handles with GOP on them to ConOut and\r
- // ErrOut.\r
- //\r
- FilterAndProcess (&gEfiGraphicsOutputProtocolGuid, NULL, AddOutput);\r
-\r
- //\r
- // Add the hardcoded short-form USB keyboard device path to ConIn.\r
- //\r
- BdsLibUpdateConsoleVariable (L"ConIn",\r
- (EFI_DEVICE_PATH_PROTOCOL *)&mUsbKeyboard, NULL);\r
-\r
- //\r
- // Add the hardcoded serial console device path to ConIn, ConOut, ErrOut.\r
- //\r
- BdsLibUpdateConsoleVariable (L"ConIn",\r
- (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);\r
- BdsLibUpdateConsoleVariable (L"ConOut",\r
- (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);\r
- BdsLibUpdateConsoleVariable (L"ErrOut",\r
- (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);\r
-\r
- //\r
- // Connect the consoles based on the above variables.\r
- //\r
- BdsLibConnectAllDefaultConsoles ();\r
-\r
- //\r
- // Show the splash screen.\r
- //\r
- EnableQuietBoot (PcdGetPtr (PcdLogoFile));\r
-\r
- //\r
- // Connect the rest of the devices.\r
- //\r
- BdsLibConnectAll ();\r
-\r
- //\r
- // Process QEMU's -kernel command line option. Note that the kernel booted\r
- // this way should receive ACPI tables, which is why we connect all devices\r
- // first (see above) -- PCI enumeration blocks ACPI table installation, if\r
- // there is a PCI host.\r
- //\r
- TryRunningQemuKernel ();\r
-\r
- BdsLibEnumerateAllBootOption (BootOptionList);\r
- SetBootOrderFromQemu (BootOptionList);\r
- //\r
- // The BootOrder variable may have changed, reload the in-memory list with\r
- // it.\r
- //\r
- BdsLibBuildOptionFromVar (BootOptionList, L"BootOrder");\r
-\r
- PlatformBdsEnterFrontPage (GetFrontPageTimeoutFromQemu(), TRUE);\r
-}\r
-\r
-/**\r
- Hook point after a boot attempt succeeds. We don't expect a boot option to\r
- return, so the UEFI 2.0 specification defines that you will default to an\r
- interactive mode and stop processing the BootOrder list in this case. This\r
- is also a platform implementation and can be customized by IBV/OEM.\r
-\r
- @param Option Pointer to Boot Option that succeeded to boot.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-PlatformBdsBootSuccess (\r
- IN BDS_COMMON_OPTION *Option\r
- )\r
-{\r
-}\r
-\r
-/**\r
- Hook point after a boot attempt fails.\r
-\r
- @param Option Pointer to Boot Option that failed to boot.\r
- @param Status Status returned from failed boot.\r
- @param ExitData Exit data returned from failed boot.\r
- @param ExitDataSize Exit data size returned from failed boot.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-PlatformBdsBootFail (\r
- IN BDS_COMMON_OPTION *Option,\r
- IN EFI_STATUS Status,\r
- IN CHAR16 *ExitData,\r
- IN UINTN ExitDataSize\r
- )\r
-{\r
-}\r
-\r
-/**\r
- This function locks platform flash that is not allowed to be updated during normal boot path.\r
- The flash layout is platform specific.\r
-**/\r
-VOID\r
-EFIAPI\r
-PlatformBdsLockNonUpdatableFlash (\r
- VOID\r
- )\r
-{\r
- return;\r
-}\r
+++ /dev/null
-/** @file\r
- Head file for BDS Platform specific code\r
-\r
- Copyright (c) 2004 - 2008, Intel Corporation. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials are licensed and made available\r
- under the terms and conditions of the BSD License which accompanies this\r
- distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
- WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#ifndef _INTEL_BDS_PLATFORM_H_\r
-#define _INTEL_BDS_PLATFORM_H_\r
-\r
-#include <Library/BaseLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/DevicePathLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <Library/UefiBootServicesTableLib.h>\r
-#include <Library/UefiRuntimeServicesTableLib.h>\r
-\r
-VOID\r
-PlatformBdsEnterFrontPage (\r
- IN UINT16 TimeoutDefault,\r
- IN BOOLEAN ConnectAllHappened\r
- );\r
-\r
-/**\r
- Download the kernel, the initial ramdisk, and the kernel command line from\r
- QEMU's fw_cfg. Construct a minimal SimpleFileSystem that contains the two\r
- image files, and load and start the kernel from it.\r
-\r
- The kernel will be instructed via its command line to load the initrd from\r
- the same Simple FileSystem.\r
-\r
- @retval EFI_NOT_FOUND Kernel image was not found.\r
- @retval EFI_OUT_OF_RESOURCES Memory allocation failed.\r
- @retval EFI_PROTOCOL_ERROR Unterminated kernel command line.\r
-\r
- @return Error codes from any of the underlying\r
- functions. On success, the function doesn't\r
- return.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-TryRunningQemuKernel (\r
- VOID\r
- );\r
-\r
-#endif // _INTEL_BDS_PLATFORM_H\r
+++ /dev/null
-## @file\r
-# Implementation for PlatformBdsLib library class interfaces.\r
-#\r
-# Copyright (C) 2015, Red Hat, Inc.\r
-# Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>\r
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials are licensed and made available\r
-# under the terms and conditions of the BSD License which accompanies this\r
-# distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR\r
-# IMPLIED.\r
-#\r
-##\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = PlatformIntelBdsLib\r
- FILE_GUID = 46DF84EB-F603-4D39-99D8-E1E86B50BCC2\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PlatformBdsLib|DXE_DRIVER\r
-\r
-#\r
-# The following information is for reference only and not required by the build tools.\r
-#\r
-# VALID_ARCHITECTURES = ARM AARCH64\r
-#\r
-\r
-[Sources]\r
- IntelBdsPlatform.c\r
- QemuKernel.c\r
-\r
-[Packages]\r
- IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
- MdePkg/MdePkg.dec\r
- OvmfPkg/OvmfPkg.dec\r
-\r
-[LibraryClasses]\r
- BaseLib\r
- BaseMemoryLib\r
- DebugLib\r
- DevicePathLib\r
- GenericBdsLib\r
- MemoryAllocationLib\r
- PcdLib\r
- PrintLib\r
- QemuBootOrderLib\r
- QemuFwCfgLib\r
- UefiBootServicesTableLib\r
- UefiRuntimeServicesTableLib\r
-\r
-[FixedPcd]\r
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile\r
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate\r
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits\r
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity\r
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits\r
-\r
-[Guids]\r
- gEfiFileInfoGuid\r
- gEfiFileSystemInfoGuid\r
- gEfiFileSystemVolumeLabelInfoIdGuid\r
-\r
-[Protocols]\r
- gEfiDevicePathProtocolGuid\r
- gEfiGraphicsOutputProtocolGuid\r
- gEfiLoadedImageProtocolGuid\r
- gEfiPciRootBridgeIoProtocolGuid\r
- gEfiSimpleFileSystemProtocolGuid\r
+++ /dev/null
-/** @file\r
- Try to load an EFI-stubbed ARM Linux kernel from QEMU's fw_cfg.\r
-\r
- This implementation differs from OvmfPkg/Library/LoadLinuxLib. An EFI\r
- stub in the subject kernel is a hard requirement here.\r
-\r
- Copyright (C) 2014, Red Hat, Inc.\r
-\r
- This program and the accompanying materials are licensed and made available\r
- under the terms and conditions of the BSD License which accompanies this\r
- distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
- WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-**/\r
-\r
-#include <Guid/FileInfo.h>\r
-#include <Guid/FileSystemInfo.h>\r
-#include <Guid/FileSystemVolumeLabelInfo.h>\r
-#include <Library/PrintLib.h>\r
-#include <Library/QemuFwCfgLib.h>\r
-#include <Protocol/DevicePath.h>\r
-#include <Protocol/LoadedImage.h>\r
-#include <Protocol/SimpleFileSystem.h>\r
-\r
-#include "IntelBdsPlatform.h"\r
-\r
-//\r
-// Static data that hosts the fw_cfg blobs and serves file requests.\r
-//\r
-typedef enum {\r
- KernelBlobTypeKernel,\r
- KernelBlobTypeInitrd,\r
- KernelBlobTypeCommandLine,\r
- KernelBlobTypeMax\r
-} KERNEL_BLOB_TYPE;\r
-\r
-typedef struct {\r
- FIRMWARE_CONFIG_ITEM CONST SizeKey;\r
- FIRMWARE_CONFIG_ITEM CONST DataKey;\r
- CONST CHAR16 * CONST Name;\r
- UINT32 Size;\r
- UINT8 *Data;\r
-} KERNEL_BLOB;\r
-\r
-STATIC KERNEL_BLOB mKernelBlob[KernelBlobTypeMax] = {\r
- { QemuFwCfgItemKernelSize, QemuFwCfgItemKernelData, L"kernel" },\r
- { QemuFwCfgItemInitrdSize, QemuFwCfgItemInitrdData, L"initrd" },\r
- { QemuFwCfgItemCommandLineSize, QemuFwCfgItemCommandLineData, L"cmdline" }\r
-};\r
-\r
-STATIC UINT64 mTotalBlobBytes;\r
-\r
-//\r
-// Device path for the handle that incorporates our "EFI stub filesystem". The\r
-// GUID is arbitrary and need not be standardized or advertized.\r
-//\r
-#pragma pack(1)\r
-typedef struct {\r
- VENDOR_DEVICE_PATH VenHwNode;\r
- EFI_DEVICE_PATH_PROTOCOL EndNode;\r
-} SINGLE_VENHW_NODE_DEVPATH;\r
-#pragma pack()\r
-\r
-STATIC CONST SINGLE_VENHW_NODE_DEVPATH mFileSystemDevicePath = {\r
- {\r
- { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH) } },\r
- {\r
- 0xb0fae7e7, 0x6b07, 0x49d0,\r
- { 0x9e, 0x5b, 0x3b, 0xde, 0xc8, 0x3b, 0x03, 0x9d }\r
- }\r
- },\r
-\r
- {\r
- END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
- { sizeof (EFI_DEVICE_PATH_PROTOCOL) }\r
- }\r
-};\r
-\r
-//\r
-// The "file in the EFI stub filesystem" abstraction.\r
-//\r
-STATIC EFI_TIME mInitTime;\r
-\r
-#define STUB_FILE_SIG SIGNATURE_64 ('S', 'T', 'U', 'B', 'F', 'I', 'L', 'E')\r
-\r
-typedef struct {\r
- UINT64 Signature; // Carries STUB_FILE_SIG.\r
-\r
- KERNEL_BLOB_TYPE BlobType; // Index into mKernelBlob. KernelBlobTypeMax\r
- // denotes the root directory of the filesystem.\r
-\r
- UINT64 Position; // Byte position for regular files;\r
- // next directory entry to return for the root\r
- // directory.\r
-\r
- EFI_FILE_PROTOCOL File; // Standard protocol interface.\r
-} STUB_FILE;\r
-\r
-#define STUB_FILE_FROM_FILE(FilePointer) \\r
- CR (FilePointer, STUB_FILE, File, STUB_FILE_SIG)\r
-\r
-//\r
-// Tentative definition of the file protocol template. The initializer\r
-// (external definition) will be provided later.\r
-//\r
-STATIC CONST EFI_FILE_PROTOCOL mEfiFileProtocolTemplate;\r
-\r
-\r
-//\r
-// Protocol member functions for File.\r
-//\r
-\r
-/**\r
- Opens a new file relative to the source file's location.\r
-\r
- @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that is\r
- the file handle to the source location. This would\r
- typically be an open handle to a directory.\r
-\r
- @param[out] NewHandle A pointer to the location to return the opened handle\r
- for the new file.\r
-\r
- @param[in] FileName The Null-terminated string of the name of the file to\r
- be opened. The file name may contain the following\r
- path modifiers: "\", ".", and "..".\r
-\r
- @param[in] OpenMode The mode to open the file. The only valid\r
- combinations that the file may be opened with are:\r
- Read, Read/Write, or Create/Read/Write.\r
-\r
- @param[in] Attributes Only valid for EFI_FILE_MODE_CREATE, in which case\r
- these are the attribute bits for the newly created\r
- file.\r
-\r
- @retval EFI_SUCCESS The file was opened.\r
- @retval EFI_NOT_FOUND The specified file could not be found on the\r
- device.\r
- @retval EFI_NO_MEDIA The device has no medium.\r
- @retval EFI_MEDIA_CHANGED The device has a different medium in it or the\r
- medium is no longer supported.\r
- @retval EFI_DEVICE_ERROR The device reported an error.\r
- @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted.\r
- @retval EFI_WRITE_PROTECTED An attempt was made to create a file, or open a\r
- file for write when the media is\r
- write-protected.\r
- @retval EFI_ACCESS_DENIED The service denied access to the file.\r
- @retval EFI_OUT_OF_RESOURCES Not enough resources were available to open the\r
- file.\r
- @retval EFI_VOLUME_FULL The volume is full.\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-EFIAPI\r
-StubFileOpen (\r
- IN EFI_FILE_PROTOCOL *This,\r
- OUT EFI_FILE_PROTOCOL **NewHandle,\r
- IN CHAR16 *FileName,\r
- IN UINT64 OpenMode,\r
- IN UINT64 Attributes\r
- )\r
-{\r
- CONST STUB_FILE *StubFile;\r
- UINTN BlobType;\r
- STUB_FILE *NewStubFile;\r
-\r
- //\r
- // We're read-only.\r
- //\r
- switch (OpenMode) {\r
- case EFI_FILE_MODE_READ:\r
- break;\r
-\r
- case EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE:\r
- case EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE | EFI_FILE_MODE_CREATE:\r
- return EFI_WRITE_PROTECTED;\r
-\r
- default:\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // Only the root directory supports opening files in it.\r
- //\r
- StubFile = STUB_FILE_FROM_FILE (This);\r
- if (StubFile->BlobType != KernelBlobTypeMax) {\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- //\r
- // Locate the file.\r
- //\r
- for (BlobType = 0; BlobType < KernelBlobTypeMax; ++BlobType) {\r
- if (StrCmp (FileName, mKernelBlob[BlobType].Name) == 0) {\r
- break;\r
- }\r
- }\r
- if (BlobType == KernelBlobTypeMax) {\r
- return EFI_NOT_FOUND;\r
- }\r
-\r
- //\r
- // Found it.\r
- //\r
- NewStubFile = AllocatePool (sizeof *NewStubFile);\r
- if (NewStubFile == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
-\r
- NewStubFile->Signature = STUB_FILE_SIG;\r
- NewStubFile->BlobType = (KERNEL_BLOB_TYPE)BlobType;\r
- NewStubFile->Position = 0;\r
- CopyMem (&NewStubFile->File, &mEfiFileProtocolTemplate,\r
- sizeof mEfiFileProtocolTemplate);\r
- *NewHandle = &NewStubFile->File;\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-/**\r
- Closes a specified file handle.\r
-\r
- @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that is the file\r
- handle to close.\r
-\r
- @retval EFI_SUCCESS The file was closed.\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-EFIAPI\r
-StubFileClose (\r
- IN EFI_FILE_PROTOCOL *This\r
- )\r
-{\r
- FreePool (STUB_FILE_FROM_FILE (This));\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-/**\r
- Close and delete the file handle.\r
-\r
- @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that is the\r
- handle to the file to delete.\r
-\r
- @retval EFI_SUCCESS The file was closed and deleted, and the\r
- handle was closed.\r
- @retval EFI_WARN_DELETE_FAILURE The handle was closed, but the file was not\r
- deleted.\r
-\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-EFIAPI\r
-StubFileDelete (\r
- IN EFI_FILE_PROTOCOL *This\r
- )\r
-{\r
- FreePool (STUB_FILE_FROM_FILE (This));\r
- return EFI_WARN_DELETE_FAILURE;\r
-}\r
-\r
-\r
-/**\r
- Helper function that formats an EFI_FILE_INFO structure into the\r
- user-allocated buffer, for any valid KERNEL_BLOB_TYPE value (including\r
- KernelBlobTypeMax, which stands for the root directory).\r
-\r
- The interface follows the EFI_FILE_GET_INFO -- and for directories, the\r
- EFI_FILE_READ -- interfaces.\r
-\r
- @param[in] BlobType The KERNEL_BLOB_TYPE value identifying the fw_cfg\r
- blob backing the STUB_FILE that information is\r
- being requested about. If BlobType equals\r
- KernelBlobTypeMax, then information will be\r
- provided about the root directory of the\r
- filesystem.\r
-\r
- @param[in,out] BufferSize On input, the size of Buffer. On output, the\r
- amount of data returned in Buffer. In both cases,\r
- the size is measured in bytes.\r
-\r
- @param[out] Buffer A pointer to the data buffer to return. The\r
- buffer's type is EFI_FILE_INFO.\r
-\r
- @retval EFI_SUCCESS The information was returned.\r
- @retval EFI_BUFFER_TOO_SMALL BufferSize is too small to store the\r
- EFI_FILE_INFO structure. BufferSize has been\r
- updated with the size needed to complete the\r
- request.\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-ConvertKernelBlobTypeToFileInfo (\r
- IN KERNEL_BLOB_TYPE BlobType,\r
- IN OUT UINTN *BufferSize,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- CONST CHAR16 *Name;\r
- UINT64 FileSize;\r
- UINT64 Attribute;\r
-\r
- UINTN NameSize;\r
- UINTN FileInfoSize;\r
- EFI_FILE_INFO *FileInfo;\r
- UINTN OriginalBufferSize;\r
-\r
- if (BlobType == KernelBlobTypeMax) {\r
- //\r
- // getting file info about the root directory\r
- //\r
- Name = L"\\";\r
- FileSize = KernelBlobTypeMax;\r
- Attribute = EFI_FILE_READ_ONLY | EFI_FILE_DIRECTORY;\r
- } else {\r
- CONST KERNEL_BLOB *Blob;\r
-\r
- Blob = &mKernelBlob[BlobType];\r
- Name = Blob->Name;\r
- FileSize = Blob->Size;\r
- Attribute = EFI_FILE_READ_ONLY;\r
- }\r
-\r
- NameSize = (StrLen(Name) + 1) * 2;\r
- FileInfoSize = OFFSET_OF (EFI_FILE_INFO, FileName) + NameSize;\r
- ASSERT (FileInfoSize >= sizeof *FileInfo);\r
-\r
- OriginalBufferSize = *BufferSize;\r
- *BufferSize = FileInfoSize;\r
- if (OriginalBufferSize < *BufferSize) {\r
- return EFI_BUFFER_TOO_SMALL;\r
- }\r
-\r
- FileInfo = (EFI_FILE_INFO *)Buffer;\r
- FileInfo->Size = FileInfoSize;\r
- FileInfo->FileSize = FileSize;\r
- FileInfo->PhysicalSize = FileSize;\r
- FileInfo->Attribute = Attribute;\r
-\r
- CopyMem (&FileInfo->CreateTime, &mInitTime, sizeof mInitTime);\r
- CopyMem (&FileInfo->LastAccessTime, &mInitTime, sizeof mInitTime);\r
- CopyMem (&FileInfo->ModificationTime, &mInitTime, sizeof mInitTime);\r
- CopyMem (FileInfo->FileName, Name, NameSize);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-/**\r
- Reads data from a file, or continues scanning a directory.\r
-\r
- @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that\r
- is the file handle to read data from.\r
-\r
- @param[in,out] BufferSize On input, the size of the Buffer. On output, the\r
- amount of data returned in Buffer. In both cases,\r
- the size is measured in bytes. If the read goes\r
- beyond the end of the file, the read length is\r
- truncated to the end of the file.\r
-\r
- If This is a directory, the function reads the\r
- directory entry at the current position and\r
- returns the entry (as EFI_FILE_INFO) in Buffer. If\r
- there are no more directory entries, the\r
- BufferSize is set to zero on output.\r
-\r
- @param[out] Buffer The buffer into which the data is read.\r
-\r
- @retval EFI_SUCCESS Data was read.\r
- @retval EFI_NO_MEDIA The device has no medium.\r
- @retval EFI_DEVICE_ERROR The device reported an error.\r
- @retval EFI_DEVICE_ERROR An attempt was made to read from a deleted\r
- file.\r
- @retval EFI_DEVICE_ERROR On entry, the current file position is beyond\r
- the end of the file.\r
- @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted.\r
- @retval EFI_BUFFER_TOO_SMALL The BufferSize is too small to store the\r
- current directory entry as a EFI_FILE_INFO\r
- structure. BufferSize has been updated with the\r
- size needed to complete the request, and the\r
- directory position has not been advanced.\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-EFIAPI\r
-StubFileRead (\r
- IN EFI_FILE_PROTOCOL *This,\r
- IN OUT UINTN *BufferSize,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- STUB_FILE *StubFile;\r
- CONST KERNEL_BLOB *Blob;\r
- UINT64 Left;\r
-\r
- StubFile = STUB_FILE_FROM_FILE (This);\r
-\r
- //\r
- // Scanning the root directory?\r
- //\r
- if (StubFile->BlobType == KernelBlobTypeMax) {\r
- EFI_STATUS Status;\r
-\r
- if (StubFile->Position == KernelBlobTypeMax) {\r
- //\r
- // Scanning complete.\r
- //\r
- *BufferSize = 0;\r
- return EFI_SUCCESS;\r
- }\r
-\r
- Status = ConvertKernelBlobTypeToFileInfo (StubFile->Position, BufferSize,\r
- Buffer);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- ++StubFile->Position;\r
- return EFI_SUCCESS;\r
- }\r
-\r
- //\r
- // Reading a file.\r
- //\r
- Blob = &mKernelBlob[StubFile->BlobType];\r
- if (StubFile->Position > Blob->Size) {\r
- return EFI_DEVICE_ERROR;\r
- }\r
-\r
- Left = Blob->Size - StubFile->Position;\r
- if (*BufferSize > Left) {\r
- *BufferSize = (UINTN)Left;\r
- }\r
- if (Blob->Data != NULL) {\r
- CopyMem (Buffer, Blob->Data + StubFile->Position, *BufferSize);\r
- }\r
- StubFile->Position += *BufferSize;\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-/**\r
- Writes data to a file.\r
-\r
- @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that\r
- is the file handle to write data to.\r
-\r
- @param[in,out] BufferSize On input, the size of the Buffer. On output, the\r
- amount of data actually written. In both cases,\r
- the size is measured in bytes.\r
-\r
- @param[in] Buffer The buffer of data to write.\r
-\r
- @retval EFI_SUCCESS Data was written.\r
- @retval EFI_UNSUPPORTED Writes to open directory files are not\r
- supported.\r
- @retval EFI_NO_MEDIA The device has no medium.\r
- @retval EFI_DEVICE_ERROR The device reported an error.\r
- @retval EFI_DEVICE_ERROR An attempt was made to write to a deleted file.\r
- @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted.\r
- @retval EFI_WRITE_PROTECTED The file or medium is write-protected.\r
- @retval EFI_ACCESS_DENIED The file was opened read only.\r
- @retval EFI_VOLUME_FULL The volume is full.\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-EFIAPI\r
-StubFileWrite (\r
- IN EFI_FILE_PROTOCOL *This,\r
- IN OUT UINTN *BufferSize,\r
- IN VOID *Buffer\r
- )\r
-{\r
- STUB_FILE *StubFile;\r
-\r
- StubFile = STUB_FILE_FROM_FILE (This);\r
- return (StubFile->BlobType == KernelBlobTypeMax) ?\r
- EFI_UNSUPPORTED :\r
- EFI_WRITE_PROTECTED;\r
-}\r
-\r
-\r
-/**\r
- Returns a file's current position.\r
-\r
- @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that is the\r
- file handle to get the current position on.\r
-\r
- @param[out] Position The address to return the file's current position\r
- value.\r
-\r
- @retval EFI_SUCCESS The position was returned.\r
- @retval EFI_UNSUPPORTED The request is not valid on open directories.\r
- @retval EFI_DEVICE_ERROR An attempt was made to get the position from a\r
- deleted file.\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-EFIAPI\r
-StubFileGetPosition (\r
- IN EFI_FILE_PROTOCOL *This,\r
- OUT UINT64 *Position\r
- )\r
-{\r
- STUB_FILE *StubFile;\r
-\r
- StubFile = STUB_FILE_FROM_FILE (This);\r
- if (StubFile->BlobType == KernelBlobTypeMax) {\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- *Position = StubFile->Position;\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-/**\r
- Sets a file's current position.\r
-\r
- @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that is the\r
- file handle to set the requested position on.\r
-\r
- @param[in] Position The byte position from the start of the file to set. For\r
- regular files, MAX_UINT64 means "seek to end". For\r
- directories, zero means "rewind directory scan".\r
-\r
- @retval EFI_SUCCESS The position was set.\r
- @retval EFI_UNSUPPORTED The seek request for nonzero is not valid on open\r
- directories.\r
- @retval EFI_DEVICE_ERROR An attempt was made to set the position of a\r
- deleted file.\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-EFIAPI\r
-StubFileSetPosition (\r
- IN EFI_FILE_PROTOCOL *This,\r
- IN UINT64 Position\r
- )\r
-{\r
- STUB_FILE *StubFile;\r
- KERNEL_BLOB *Blob;\r
-\r
- StubFile = STUB_FILE_FROM_FILE (This);\r
-\r
- if (StubFile->BlobType == KernelBlobTypeMax) {\r
- if (Position == 0) {\r
- //\r
- // rewinding a directory scan is allowed\r
- //\r
- StubFile->Position = 0;\r
- return EFI_SUCCESS;\r
- }\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- //\r
- // regular file seek\r
- //\r
- Blob = &mKernelBlob[StubFile->BlobType];\r
- if (Position == MAX_UINT64) {\r
- //\r
- // seek to end\r
- //\r
- StubFile->Position = Blob->Size;\r
- } else {\r
- //\r
- // absolute seek from beginning -- seeking past the end is allowed\r
- //\r
- StubFile->Position = Position;\r
- }\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-/**\r
- Returns information about a file.\r
-\r
- @param[in] This A pointer to the EFI_FILE_PROTOCOL instance\r
- that is the file handle the requested\r
- information is for.\r
-\r
- @param[in] InformationType The type identifier GUID for the information\r
- being requested. The following information\r
- types are supported, storing the\r
- corresponding structures in Buffer:\r
-\r
- - gEfiFileInfoGuid: EFI_FILE_INFO\r
-\r
- - gEfiFileSystemInfoGuid:\r
- EFI_FILE_SYSTEM_INFO\r
-\r
- - gEfiFileSystemVolumeLabelInfoIdGuid:\r
- EFI_FILE_SYSTEM_VOLUME_LABEL\r
-\r
- @param[in,out] BufferSize On input, the size of Buffer. On output, the\r
- amount of data returned in Buffer. In both\r
- cases, the size is measured in bytes.\r
-\r
- @param[out] Buffer A pointer to the data buffer to return. The\r
- buffer's type is indicated by\r
- InformationType.\r
-\r
- @retval EFI_SUCCESS The information was returned.\r
- @retval EFI_UNSUPPORTED The InformationType is not known.\r
- @retval EFI_NO_MEDIA The device has no medium.\r
- @retval EFI_DEVICE_ERROR The device reported an error.\r
- @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted.\r
- @retval EFI_BUFFER_TOO_SMALL The BufferSize is too small to store the\r
- information structure requested by\r
- InformationType. BufferSize has been updated\r
- with the size needed to complete the request.\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-EFIAPI\r
-StubFileGetInfo (\r
- IN EFI_FILE_PROTOCOL *This,\r
- IN EFI_GUID *InformationType,\r
- IN OUT UINTN *BufferSize,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- CONST STUB_FILE *StubFile;\r
- UINTN OriginalBufferSize;\r
-\r
- StubFile = STUB_FILE_FROM_FILE (This);\r
-\r
- if (CompareGuid (InformationType, &gEfiFileInfoGuid)) {\r
- return ConvertKernelBlobTypeToFileInfo (StubFile->BlobType, BufferSize,\r
- Buffer);\r
- }\r
-\r
- OriginalBufferSize = *BufferSize;\r
-\r
- if (CompareGuid (InformationType, &gEfiFileSystemInfoGuid)) {\r
- EFI_FILE_SYSTEM_INFO *FileSystemInfo;\r
-\r
- *BufferSize = sizeof *FileSystemInfo;\r
- if (OriginalBufferSize < *BufferSize) {\r
- return EFI_BUFFER_TOO_SMALL;\r
- }\r
-\r
- FileSystemInfo = (EFI_FILE_SYSTEM_INFO *)Buffer;\r
- FileSystemInfo->Size = sizeof *FileSystemInfo;\r
- FileSystemInfo->ReadOnly = TRUE;\r
- FileSystemInfo->VolumeSize = mTotalBlobBytes;\r
- FileSystemInfo->FreeSpace = 0;\r
- FileSystemInfo->BlockSize = 1;\r
- FileSystemInfo->VolumeLabel[0] = L'\0';\r
-\r
- return EFI_SUCCESS;\r
- }\r
-\r
- if (CompareGuid (InformationType, &gEfiFileSystemVolumeLabelInfoIdGuid)) {\r
- EFI_FILE_SYSTEM_VOLUME_LABEL *FileSystemVolumeLabel;\r
-\r
- *BufferSize = sizeof *FileSystemVolumeLabel;\r
- if (OriginalBufferSize < *BufferSize) {\r
- return EFI_BUFFER_TOO_SMALL;\r
- }\r
-\r
- FileSystemVolumeLabel = (EFI_FILE_SYSTEM_VOLUME_LABEL *)Buffer;\r
- FileSystemVolumeLabel->VolumeLabel[0] = L'\0';\r
-\r
- return EFI_SUCCESS;\r
- }\r
-\r
- return EFI_UNSUPPORTED;\r
-}\r
-\r
-\r
-/**\r
- Sets information about a file.\r
-\r
- @param[in] File A pointer to the EFI_FILE_PROTOCOL instance that\r
- is the file handle the information is for.\r
-\r
- @param[in] InformationType The type identifier for the information being\r
- set.\r
-\r
- @param[in] BufferSize The size, in bytes, of Buffer.\r
-\r
- @param[in] Buffer A pointer to the data buffer to write. The\r
- buffer's type is indicated by InformationType.\r
-\r
- @retval EFI_SUCCESS The information was set.\r
- @retval EFI_UNSUPPORTED The InformationType is not known.\r
- @retval EFI_NO_MEDIA The device has no medium.\r
- @retval EFI_DEVICE_ERROR The device reported an error.\r
- @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted.\r
- @retval EFI_WRITE_PROTECTED InformationType is EFI_FILE_INFO_ID and the\r
- media is read-only.\r
- @retval EFI_WRITE_PROTECTED InformationType is\r
- EFI_FILE_PROTOCOL_SYSTEM_INFO_ID and the media\r
- is read only.\r
- @retval EFI_WRITE_PROTECTED InformationType is\r
- EFI_FILE_SYSTEM_VOLUME_LABEL_ID and the media\r
- is read-only.\r
- @retval EFI_ACCESS_DENIED An attempt is made to change the name of a file\r
- to a file that is already present.\r
- @retval EFI_ACCESS_DENIED An attempt is being made to change the\r
- EFI_FILE_DIRECTORY Attribute.\r
- @retval EFI_ACCESS_DENIED An attempt is being made to change the size of\r
- a directory.\r
- @retval EFI_ACCESS_DENIED InformationType is EFI_FILE_INFO_ID and the\r
- file was opened read-only and an attempt is\r
- being made to modify a field other than\r
- Attribute.\r
- @retval EFI_VOLUME_FULL The volume is full.\r
- @retval EFI_BAD_BUFFER_SIZE BufferSize is smaller than the size of the type\r
- indicated by InformationType.\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-EFIAPI\r
-StubFileSetInfo (\r
- IN EFI_FILE_PROTOCOL *This,\r
- IN EFI_GUID *InformationType,\r
- IN UINTN BufferSize,\r
- IN VOID *Buffer\r
- )\r
-{\r
- return EFI_WRITE_PROTECTED;\r
-}\r
-\r
-\r
-/**\r
- Flushes all modified data associated with a file to a device.\r
-\r
- @param [in] This A pointer to the EFI_FILE_PROTOCOL instance that is the\r
- file handle to flush.\r
-\r
- @retval EFI_SUCCESS The data was flushed.\r
- @retval EFI_NO_MEDIA The device has no medium.\r
- @retval EFI_DEVICE_ERROR The device reported an error.\r
- @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted.\r
- @retval EFI_WRITE_PROTECTED The file or medium is write-protected.\r
- @retval EFI_ACCESS_DENIED The file was opened read-only.\r
- @retval EFI_VOLUME_FULL The volume is full.\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-EFIAPI\r
-StubFileFlush (\r
- IN EFI_FILE_PROTOCOL *This\r
- )\r
-{\r
- return EFI_WRITE_PROTECTED;\r
-}\r
-\r
-//\r
-// External definition of the file protocol template.\r
-//\r
-STATIC CONST EFI_FILE_PROTOCOL mEfiFileProtocolTemplate = {\r
- EFI_FILE_PROTOCOL_REVISION, // revision 1\r
- StubFileOpen,\r
- StubFileClose,\r
- StubFileDelete,\r
- StubFileRead,\r
- StubFileWrite,\r
- StubFileGetPosition,\r
- StubFileSetPosition,\r
- StubFileGetInfo,\r
- StubFileSetInfo,\r
- StubFileFlush,\r
- NULL, // OpenEx, revision 2\r
- NULL, // ReadEx, revision 2\r
- NULL, // WriteEx, revision 2\r
- NULL // FlushEx, revision 2\r
-};\r
-\r
-\r
-//\r
-// Protocol member functions for SimpleFileSystem.\r
-//\r
-\r
-/**\r
- Open the root directory on a volume.\r
-\r
- @param[in] This A pointer to the volume to open the root directory on.\r
-\r
- @param[out] Root A pointer to the location to return the opened file handle\r
- for the root directory in.\r
-\r
- @retval EFI_SUCCESS The device was opened.\r
- @retval EFI_UNSUPPORTED This volume does not support the requested file\r
- system type.\r
- @retval EFI_NO_MEDIA The device has no medium.\r
- @retval EFI_DEVICE_ERROR The device reported an error.\r
- @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted.\r
- @retval EFI_ACCESS_DENIED The service denied access to the file.\r
- @retval EFI_OUT_OF_RESOURCES The volume was not opened due to lack of\r
- resources.\r
- @retval EFI_MEDIA_CHANGED The device has a different medium in it or the\r
- medium is no longer supported. Any existing\r
- file handles for this volume are no longer\r
- valid. To access the files on the new medium,\r
- the volume must be reopened with OpenVolume().\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-EFIAPI\r
-StubFileSystemOpenVolume (\r
- IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This,\r
- OUT EFI_FILE_PROTOCOL **Root\r
- )\r
-{\r
- STUB_FILE *StubFile;\r
-\r
- StubFile = AllocatePool (sizeof *StubFile);\r
- if (StubFile == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
-\r
- StubFile->Signature = STUB_FILE_SIG;\r
- StubFile->BlobType = KernelBlobTypeMax;\r
- StubFile->Position = 0;\r
- CopyMem (&StubFile->File, &mEfiFileProtocolTemplate,\r
- sizeof mEfiFileProtocolTemplate);\r
- *Root = &StubFile->File;\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-STATIC CONST EFI_SIMPLE_FILE_SYSTEM_PROTOCOL mFileSystem = {\r
- EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION,\r
- StubFileSystemOpenVolume\r
-};\r
-\r
-\r
-//\r
-// Utility functions.\r
-//\r
-\r
-/**\r
- Populate a blob in mKernelBlob.\r
-\r
- param[in,out] Blob Pointer to the KERNEL_BLOB element in mKernelBlob that is\r
- to be filled from fw_cfg.\r
-\r
- @retval EFI_SUCCESS Blob has been populated. If fw_cfg reported a\r
- size of zero for the blob, then Blob->Data has\r
- been left unchanged.\r
-\r
- @retval EFI_OUT_OF_RESOURCES Failed to allocate memory for Blob->Data.\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-FetchBlob (\r
- IN OUT KERNEL_BLOB *Blob\r
- )\r
-{\r
- UINT32 Left;\r
-\r
- //\r
- // Read blob size.\r
- //\r
- QemuFwCfgSelectItem (Blob->SizeKey);\r
- Blob->Size = QemuFwCfgRead32 ();\r
- if (Blob->Size == 0) {\r
- return EFI_SUCCESS;\r
- }\r
-\r
- //\r
- // Read blob.\r
- //\r
- Blob->Data = AllocatePool (Blob->Size);\r
- if (Blob->Data == NULL) {\r
- DEBUG ((EFI_D_ERROR, "%a: failed to allocate %Ld bytes for \"%s\"\n",\r
- __FUNCTION__, (INT64)Blob->Size, Blob->Name));\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
-\r
- DEBUG ((EFI_D_INFO, "%a: loading %Ld bytes for \"%s\"\n", __FUNCTION__,\r
- (INT64)Blob->Size, Blob->Name));\r
- QemuFwCfgSelectItem (Blob->DataKey);\r
-\r
- Left = Blob->Size;\r
- do {\r
- UINT32 Chunk;\r
-\r
- Chunk = (Left < SIZE_1MB) ? Left : SIZE_1MB;\r
- QemuFwCfgReadBytes (Chunk, Blob->Data + (Blob->Size - Left));\r
- Left -= Chunk;\r
- DEBUG ((EFI_D_VERBOSE, "%a: %Ld bytes remaining for \"%s\"\n",\r
- __FUNCTION__, (INT64)Left, Blob->Name));\r
- } while (Left > 0);\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-//\r
-// The entry point of the feature.\r
-//\r
-\r
-/**\r
- Download the kernel, the initial ramdisk, and the kernel command line from\r
- QEMU's fw_cfg. Construct a minimal SimpleFileSystem that contains the two\r
- image files, and load and start the kernel from it.\r
-\r
- The kernel will be instructed via its command line to load the initrd from\r
- the same Simple FileSystem.\r
-\r
- @retval EFI_NOT_FOUND Kernel image was not found.\r
- @retval EFI_OUT_OF_RESOURCES Memory allocation failed.\r
- @retval EFI_PROTOCOL_ERROR Unterminated kernel command line.\r
-\r
- @return Error codes from any of the underlying\r
- functions. On success, the function doesn't\r
- return.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-TryRunningQemuKernel (\r
- VOID\r
- )\r
-{\r
- UINTN BlobType;\r
- KERNEL_BLOB *CurrentBlob;\r
- KERNEL_BLOB *KernelBlob, *InitrdBlob, *CommandLineBlob;\r
- EFI_STATUS Status;\r
- EFI_HANDLE FileSystemHandle;\r
- EFI_DEVICE_PATH_PROTOCOL *KernelDevicePath;\r
- EFI_HANDLE KernelImageHandle;\r
- EFI_LOADED_IMAGE_PROTOCOL *KernelLoadedImage;\r
-\r
- Status = gRT->GetTime (&mInitTime, NULL /* Capabilities */);\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "%a: GetTime(): %r\n", __FUNCTION__, Status));\r
- return Status;\r
- }\r
-\r
- //\r
- // Fetch all blobs.\r
- //\r
- for (BlobType = 0; BlobType < KernelBlobTypeMax; ++BlobType) {\r
- CurrentBlob = &mKernelBlob[BlobType];\r
- Status = FetchBlob (CurrentBlob);\r
- if (EFI_ERROR (Status)) {\r
- goto FreeBlobs;\r
- }\r
- mTotalBlobBytes += CurrentBlob->Size;\r
- }\r
- KernelBlob = &mKernelBlob[KernelBlobTypeKernel];\r
- InitrdBlob = &mKernelBlob[KernelBlobTypeInitrd];\r
- CommandLineBlob = &mKernelBlob[KernelBlobTypeCommandLine];\r
-\r
- if (KernelBlob->Data == NULL) {\r
- Status = EFI_NOT_FOUND;\r
- goto FreeBlobs;\r
- }\r
-\r
- //\r
- // Create a new handle with a single VenHw() node device path protocol on it,\r
- // plus a custom SimpleFileSystem protocol on it.\r
- //\r
- FileSystemHandle = NULL;\r
- Status = gBS->InstallMultipleProtocolInterfaces (&FileSystemHandle,\r
- &gEfiDevicePathProtocolGuid, &mFileSystemDevicePath,\r
- &gEfiSimpleFileSystemProtocolGuid, &mFileSystem,\r
- NULL);\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "%a: InstallMultipleProtocolInterfaces(): %r\n",\r
- __FUNCTION__, Status));\r
- goto FreeBlobs;\r
- }\r
-\r
- //\r
- // Create a device path for the kernel image to be loaded from that will call\r
- // back into our file system.\r
- //\r
- KernelDevicePath = FileDevicePath (FileSystemHandle, KernelBlob->Name);\r
- if (KernelDevicePath == NULL) {\r
- DEBUG ((EFI_D_ERROR, "%a: failed to allocate kernel device path\n",\r
- __FUNCTION__));\r
- Status = EFI_OUT_OF_RESOURCES;\r
- goto UninstallProtocols;\r
- }\r
-\r
- //\r
- // Load the image. This should call back into our file system.\r
- //\r
- Status = gBS->LoadImage (\r
- FALSE, // BootPolicy: exact match required\r
- gImageHandle, // ParentImageHandle\r
- KernelDevicePath,\r
- NULL, // SourceBuffer\r
- 0, // SourceSize\r
- &KernelImageHandle\r
- );\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "%a: LoadImage(): %r\n", __FUNCTION__, Status));\r
- goto FreeKernelDevicePath;\r
- }\r
-\r
- //\r
- // Construct the kernel command line.\r
- //\r
- Status = gBS->OpenProtocol (\r
- KernelImageHandle,\r
- &gEfiLoadedImageProtocolGuid,\r
- (VOID **)&KernelLoadedImage,\r
- gImageHandle, // AgentHandle\r
- NULL, // ControllerHandle\r
- EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- if (CommandLineBlob->Data == NULL) {\r
- KernelLoadedImage->LoadOptionsSize = 0;\r
- } else {\r
- //\r
- // Verify NUL-termination of the command line.\r
- //\r
- if (CommandLineBlob->Data[CommandLineBlob->Size - 1] != '\0') {\r
- DEBUG ((EFI_D_ERROR, "%a: kernel command line is not NUL-terminated\n",\r
- __FUNCTION__));\r
- Status = EFI_PROTOCOL_ERROR;\r
- goto UnloadKernelImage;\r
- }\r
-\r
- //\r
- // Drop the terminating NUL, convert to UTF-16.\r
- //\r
- KernelLoadedImage->LoadOptionsSize = (CommandLineBlob->Size - 1) * 2;\r
- }\r
-\r
- if (InitrdBlob->Data != NULL) {\r
- //\r
- // Append ' initrd=<name>' in UTF-16.\r
- //\r
- KernelLoadedImage->LoadOptionsSize +=\r
- (8 + StrLen(InitrdBlob->Name)) * 2;\r
- }\r
-\r
- if (KernelLoadedImage->LoadOptionsSize == 0) {\r
- KernelLoadedImage->LoadOptions = NULL;\r
- } else {\r
- //\r
- // NUL-terminate in UTF-16.\r
- //\r
- KernelLoadedImage->LoadOptionsSize += 2;\r
-\r
- KernelLoadedImage->LoadOptions = AllocatePool (\r
- KernelLoadedImage->LoadOptionsSize);\r
- if (KernelLoadedImage->LoadOptions == NULL) {\r
- KernelLoadedImage->LoadOptionsSize = 0;\r
- Status = EFI_OUT_OF_RESOURCES;\r
- goto UnloadKernelImage;\r
- }\r
-\r
- UnicodeSPrintAsciiFormat (\r
- KernelLoadedImage->LoadOptions,\r
- KernelLoadedImage->LoadOptionsSize,\r
- "%a%a%s",\r
- (CommandLineBlob->Data == NULL) ? "" : (CHAR8 *)CommandLineBlob->Data,\r
- (InitrdBlob->Data == NULL) ? "" : " initrd=",\r
- (InitrdBlob->Data == NULL) ? L"" : InitrdBlob->Name\r
- );\r
- DEBUG ((EFI_D_INFO, "%a: command line: \"%s\"\n", __FUNCTION__,\r
- (CHAR16 *)KernelLoadedImage->LoadOptions));\r
- }\r
-\r
- //\r
- // Start the image.\r
- //\r
- Status = gBS->StartImage (\r
- KernelImageHandle,\r
- NULL, // ExitDataSize\r
- NULL // ExitData\r
- );\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "%a: StartImage(): %r\n", __FUNCTION__, Status));\r
- }\r
-\r
- if (KernelLoadedImage->LoadOptions != NULL) {\r
- FreePool (KernelLoadedImage->LoadOptions);\r
- }\r
- KernelLoadedImage->LoadOptionsSize = 0;\r
-\r
-UnloadKernelImage:\r
- gBS->UnloadImage (KernelImageHandle);\r
-\r
-FreeKernelDevicePath:\r
- FreePool (KernelDevicePath);\r
-\r
-UninstallProtocols:\r
- gBS->UninstallMultipleProtocolInterfaces (FileSystemHandle,\r
- &gEfiSimpleFileSystemProtocolGuid, &mFileSystem,\r
- &gEfiDevicePathProtocolGuid, &mFileSystemDevicePath,\r
- NULL);\r
-\r
-FreeBlobs:\r
- while (BlobType > 0) {\r
- CurrentBlob = &mKernelBlob[--BlobType];\r
- if (CurrentBlob->Data != NULL) {\r
- FreePool (CurrentBlob->Data);\r
- CurrentBlob->Size = 0;\r
- CurrentBlob->Data = NULL;\r
- }\r
- }\r
-\r
- return Status;\r
-}\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-* Copyright (c) 2014, Linaro Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <PiPei.h>\r
-\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/HobLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <libfdt.h>\r
-\r
-#include <Guid/EarlyPL011BaseAddress.h>\r
-#include <Guid/FdtHob.h>\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-PlatformPeim (\r
- VOID\r
- )\r
-{\r
- VOID *Base;\r
- VOID *NewBase;\r
- UINTN FdtSize;\r
- UINTN FdtPages;\r
- UINT64 *FdtHobData;\r
- UINT64 *UartHobData;\r
- INT32 Node, Prev;\r
- CONST CHAR8 *Compatible;\r
- CONST CHAR8 *CompItem;\r
- INT32 Len;\r
- CONST UINT64 *RegProp;\r
- UINT64 UartBase;\r
-\r
-\r
- Base = (VOID*)(UINTN)PcdGet64 (PcdDeviceTreeInitialBaseAddress);\r
- ASSERT (Base != NULL);\r
- ASSERT (fdt_check_header (Base) == 0);\r
-\r
- FdtSize = fdt_totalsize (Base) + PcdGet32 (PcdDeviceTreeAllocationPadding);\r
- FdtPages = EFI_SIZE_TO_PAGES (FdtSize);\r
- NewBase = AllocatePages (FdtPages);\r
- ASSERT (NewBase != NULL);\r
- fdt_open_into (Base, NewBase, EFI_PAGES_TO_SIZE (FdtPages));\r
-\r
- FdtHobData = BuildGuidHob (&gFdtHobGuid, sizeof *FdtHobData);\r
- ASSERT (FdtHobData != NULL);\r
- *FdtHobData = (UINTN)NewBase;\r
-\r
- UartHobData = BuildGuidHob (&gEarlyPL011BaseAddressGuid, sizeof *UartHobData);\r
- ASSERT (UartHobData != NULL);\r
- *UartHobData = 0;\r
-\r
- //\r
- // Look for a UART node\r
- //\r
- for (Prev = 0;; Prev = Node) {\r
- Node = fdt_next_node (Base, Prev, NULL);\r
- if (Node < 0) {\r
- break;\r
- }\r
-\r
- //\r
- // Check for UART node\r
- //\r
- Compatible = fdt_getprop (Base, Node, "compatible", &Len);\r
-\r
- //\r
- // Iterate over the NULL-separated items in the compatible string\r
- //\r
- for (CompItem = Compatible; CompItem != NULL && CompItem < Compatible + Len;\r
- CompItem += 1 + AsciiStrLen (CompItem)) {\r
-\r
- if (AsciiStrCmp (CompItem, "arm,pl011") == 0) {\r
- RegProp = fdt_getprop (Base, Node, "reg", &Len);\r
- ASSERT (Len == 16);\r
-\r
- UartBase = fdt64_to_cpu (ReadUnaligned64 (RegProp));\r
-\r
- DEBUG ((EFI_D_INFO, "%a: PL011 UART @ 0x%lx\n", __FUNCTION__, UartBase));\r
-\r
- *UartHobData = UartBase;\r
- break;\r
- }\r
- }\r
- }\r
-\r
- BuildFvHob (PcdGet64 (PcdFvBaseAddress), PcdGet32 (PcdFvSize));\r
-\r
- return EFI_SUCCESS;\r
-}\r
+++ /dev/null
-#/** @file\r
-#\r
-# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = PlatformPeiLib\r
- FILE_GUID = 59C11815-F8DA-4F49-B4FB-EC1E41ED1F06\r
- MODULE_TYPE = SEC\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PlatformPeiLib\r
-\r
-[Sources]\r
- PlatformPeiLib.c\r
-\r
-[Packages]\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationPkg.dec\r
- MdePkg/MdePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
-\r
-[LibraryClasses]\r
- DebugLib\r
- HobLib\r
- FdtLib\r
-\r
-[FixedPcd]\r
- gArmTokenSpaceGuid.PcdFvSize\r
- gArmVirtualizationTokenSpaceGuid.PcdDeviceTreeAllocationPadding\r
-\r
-[Pcd]\r
- gArmTokenSpaceGuid.PcdFvBaseAddress\r
- gArmVirtualizationTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress\r
-\r
-[Guids]\r
- gEarlyPL011BaseAddressGuid\r
- gFdtHobGuid\r
-\r
-[Depex]\r
- gEfiPeiMemoryDiscoveredPpiGuid\r
+++ /dev/null
-/** @file\r
-\r
- Stateful and implicitly initialized fw_cfg library implementation.\r
-\r
- Copyright (C) 2013 - 2014, Red Hat, Inc.\r
- Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials are licensed and made available\r
- under the terms and conditions of the BSD License which accompanies this\r
- distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
- WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-**/\r
-\r
-#include <Library/BaseLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/QemuFwCfgLib.h>\r
-\r
-STATIC UINTN mFwCfgSelectorAddress;\r
-STATIC UINTN mFwCfgDataAddress;\r
-\r
-\r
-/**\r
- Returns a boolean indicating if the firmware configuration interface is\r
- available for library-internal purposes.\r
-\r
- This function never changes fw_cfg state.\r
-\r
- @retval TRUE The interface is available internally.\r
- @retval FALSE The interface is not available internally.\r
-**/\r
-BOOLEAN\r
-EFIAPI\r
-InternalQemuFwCfgIsAvailable (\r
- VOID\r
- )\r
-{\r
- return (BOOLEAN)(mFwCfgSelectorAddress != 0 && mFwCfgDataAddress != 0);\r
-}\r
-\r
-\r
-/**\r
- Returns a boolean indicating if the firmware configuration interface\r
- is available or not.\r
-\r
- This function may change fw_cfg state.\r
-\r
- @retval TRUE The interface is available\r
- @retval FALSE The interface is not available\r
-\r
-**/\r
-BOOLEAN\r
-EFIAPI\r
-QemuFwCfgIsAvailable (\r
- VOID\r
- )\r
-{\r
- return InternalQemuFwCfgIsAvailable ();\r
-}\r
-\r
-\r
-RETURN_STATUS\r
-EFIAPI\r
-QemuFwCfgInitialize (\r
- VOID\r
- )\r
-{\r
- mFwCfgSelectorAddress = (UINTN)PcdGet64 (PcdFwCfgSelectorAddress);\r
- mFwCfgDataAddress = (UINTN)PcdGet64 (PcdFwCfgDataAddress);\r
-\r
- if (InternalQemuFwCfgIsAvailable ()) {\r
- UINT32 Signature;\r
-\r
- QemuFwCfgSelectItem (QemuFwCfgItemSignature);\r
- Signature = QemuFwCfgRead32 ();\r
- if (Signature != SIGNATURE_32 ('Q', 'E', 'M', 'U')) {\r
- mFwCfgSelectorAddress = 0;\r
- mFwCfgDataAddress = 0;\r
- }\r
- }\r
- return RETURN_SUCCESS;\r
-}\r
-\r
-\r
-/**\r
- Selects a firmware configuration item for reading.\r
-\r
- Following this call, any data read from this item will start from the\r
- beginning of the configuration item's data.\r
-\r
- @param[in] QemuFwCfgItem Firmware Configuration item to read\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-QemuFwCfgSelectItem (\r
- IN FIRMWARE_CONFIG_ITEM QemuFwCfgItem\r
- )\r
-{\r
- if (InternalQemuFwCfgIsAvailable ()) {\r
- MmioWrite16 (mFwCfgSelectorAddress, SwapBytes16 ((UINT16)QemuFwCfgItem));\r
- }\r
-}\r
-\r
-\r
-/**\r
- Reads firmware configuration bytes into a buffer\r
-\r
- @param[in] Size Size in bytes to read\r
- @param[in] Buffer Buffer to store data into (OPTIONAL if Size is 0)\r
-\r
-**/\r
-STATIC\r
-VOID\r
-EFIAPI\r
-InternalQemuFwCfgReadBytes (\r
- IN UINTN Size,\r
- IN VOID *Buffer OPTIONAL\r
- )\r
-{\r
- UINTN Left;\r
- UINT8 *Ptr;\r
- UINT8 *End;\r
-\r
-#ifdef MDE_CPU_AARCH64\r
- Left = Size & 7;\r
-#else\r
- Left = Size & 3;\r
-#endif\r
-\r
- Size -= Left;\r
- Ptr = Buffer;\r
- End = Ptr + Size;\r
-\r
-#ifdef MDE_CPU_AARCH64\r
- while (Ptr < End) {\r
- *(UINT64 *)Ptr = MmioRead64 (mFwCfgDataAddress);\r
- Ptr += 8;\r
- }\r
- if (Left & 4) {\r
- *(UINT32 *)Ptr = MmioRead32 (mFwCfgDataAddress);\r
- Ptr += 4;\r
- }\r
-#else\r
- while (Ptr < End) {\r
- *(UINT32 *)Ptr = MmioRead32 (mFwCfgDataAddress);\r
- Ptr += 4;\r
- }\r
-#endif\r
-\r
- if (Left & 2) {\r
- *(UINT16 *)Ptr = MmioRead16 (mFwCfgDataAddress);\r
- Ptr += 2;\r
- }\r
- if (Left & 1) {\r
- *Ptr = MmioRead8 (mFwCfgDataAddress);\r
- }\r
-}\r
-\r
-\r
-/**\r
- Reads firmware configuration bytes into a buffer\r
-\r
- If called multiple times, then the data read will continue at the offset of\r
- the firmware configuration item where the previous read ended.\r
-\r
- @param[in] Size Size in bytes to read\r
- @param[in] Buffer Buffer to store data into\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-QemuFwCfgReadBytes (\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
- )\r
-{\r
- if (InternalQemuFwCfgIsAvailable ()) {\r
- InternalQemuFwCfgReadBytes (Size, Buffer);\r
- } else {\r
- ZeroMem (Buffer, Size);\r
- }\r
-}\r
-\r
-/**\r
- Write firmware configuration bytes from a buffer\r
-\r
- If called multiple times, then the data written will continue at the offset\r
- of the firmware configuration item where the previous write ended.\r
-\r
- @param[in] Size Size in bytes to write\r
- @param[in] Buffer Buffer to read data from\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-QemuFwCfgWriteBytes (\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
- )\r
-{\r
- if (InternalQemuFwCfgIsAvailable ()) {\r
- UINTN Idx;\r
-\r
- for (Idx = 0; Idx < Size; ++Idx) {\r
- MmioWrite8 (mFwCfgDataAddress, ((UINT8 *)Buffer)[Idx]);\r
- }\r
- }\r
-}\r
-\r
-\r
-/**\r
- Reads a UINT8 firmware configuration value\r
-\r
- @return Value of Firmware Configuration item read\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-QemuFwCfgRead8 (\r
- VOID\r
- )\r
-{\r
- UINT8 Result;\r
-\r
- QemuFwCfgReadBytes (sizeof Result, &Result);\r
- return Result;\r
-}\r
-\r
-\r
-/**\r
- Reads a UINT16 firmware configuration value\r
-\r
- @return Value of Firmware Configuration item read\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-QemuFwCfgRead16 (\r
- VOID\r
- )\r
-{\r
- UINT16 Result;\r
-\r
- QemuFwCfgReadBytes (sizeof Result, &Result);\r
- return Result;\r
-}\r
-\r
-\r
-/**\r
- Reads a UINT32 firmware configuration value\r
-\r
- @return Value of Firmware Configuration item read\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-QemuFwCfgRead32 (\r
- VOID\r
- )\r
-{\r
- UINT32 Result;\r
-\r
- QemuFwCfgReadBytes (sizeof Result, &Result);\r
- return Result;\r
-}\r
-\r
-\r
-/**\r
- Reads a UINT64 firmware configuration value\r
-\r
- @return Value of Firmware Configuration item read\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-QemuFwCfgRead64 (\r
- VOID\r
- )\r
-{\r
- UINT64 Result;\r
-\r
- QemuFwCfgReadBytes (sizeof Result, &Result);\r
- return Result;\r
-}\r
-\r
-\r
-/**\r
- Find the configuration item corresponding to the firmware configuration file.\r
-\r
- @param[in] Name Name of file to look up.\r
- @param[out] Item Configuration item corresponding to the file, to be passed\r
- to QemuFwCfgSelectItem ().\r
- @param[out] Size Number of bytes in the file.\r
-\r
- @retval RETURN_SUCCESS If file is found.\r
- @retval RETURN_NOT_FOUND If file is not found.\r
- @retval RETURN_UNSUPPORTED If firmware configuration is unavailable.\r
-\r
-**/\r
-RETURN_STATUS\r
-EFIAPI\r
-QemuFwCfgFindFile (\r
- IN CONST CHAR8 *Name,\r
- OUT FIRMWARE_CONFIG_ITEM *Item,\r
- OUT UINTN *Size\r
- )\r
-{\r
- UINT32 Count;\r
- UINT32 Idx;\r
-\r
- if (!InternalQemuFwCfgIsAvailable ()) {\r
- return RETURN_UNSUPPORTED;\r
- }\r
-\r
- QemuFwCfgSelectItem (QemuFwCfgItemFileDir);\r
- Count = SwapBytes32 (QemuFwCfgRead32 ());\r
-\r
- for (Idx = 0; Idx < Count; ++Idx) {\r
- UINT32 FileSize;\r
- UINT16 FileSelect;\r
- CHAR8 FName[QEMU_FW_CFG_FNAME_SIZE];\r
-\r
- FileSize = QemuFwCfgRead32 ();\r
- FileSelect = QemuFwCfgRead16 ();\r
- QemuFwCfgRead16 (); // skip the field called "reserved"\r
- InternalQemuFwCfgReadBytes (sizeof (FName), FName);\r
-\r
- if (AsciiStrCmp (Name, FName) == 0) {\r
- *Item = (FIRMWARE_CONFIG_ITEM) SwapBytes16 (FileSelect);\r
- *Size = SwapBytes32 (FileSize);\r
- return RETURN_SUCCESS;\r
- }\r
- }\r
-\r
- return RETURN_NOT_FOUND;\r
-}\r
-\r
-\r
-/**\r
- Determine if S3 support is explicitly enabled.\r
-\r
- @retval TRUE if S3 support is explicitly enabled.\r
- FALSE otherwise. This includes unavailability of the firmware\r
- configuration interface.\r
-**/\r
-BOOLEAN\r
-EFIAPI\r
-QemuFwCfgS3Enabled (\r
- VOID\r
- )\r
-{\r
- return FALSE;\r
-}\r
+++ /dev/null
-## @file\r
-#\r
-# Stateful, implicitly initialized fw_cfg library.\r
-#\r
-# Copyright (C) 2013 - 2014, Red Hat, Inc.\r
-# Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials are licensed and made available\r
-# under the terms and conditions of the BSD License which accompanies this\r
-# distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR\r
-# IMPLIED.\r
-#\r
-##\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = QemuFwCfgLib\r
- FILE_GUID = B271F41F-B841-48A9-BA8D-545B4BC2E2BF\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = QemuFwCfgLib|DXE_DRIVER\r
-\r
- CONSTRUCTOR = QemuFwCfgInitialize\r
-\r
-#\r
-# The following information is for reference only and not required by the build\r
-# tools.\r
-#\r
-# VALID_ARCHITECTURES = ARM AARCH64\r
-#\r
-\r
-[Sources]\r
- QemuFwCfgLib.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- OvmfPkg/OvmfPkg.dec\r
- ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationPkg.dec\r
-\r
-[LibraryClasses]\r
- BaseLib\r
- BaseMemoryLib\r
- IoLib\r
- PcdLib\r
-\r
-[Pcd]\r
- gArmVirtualizationTokenSpaceGuid.PcdFwCfgSelectorAddress\r
- gArmVirtualizationTokenSpaceGuid.PcdFwCfgDataAddress\r
+++ /dev/null
-/** @file\r
- Implement EFI RealTimeClock runtime services via Xen shared info page\r
-\r
- Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <Uefi.h>\r
-#include <PiDxe.h>\r
-#include <Library/BaseLib.h>\r
-#include <Library/DebugLib.h>\r
-\r
-/**\r
- Converts Epoch seconds (elapsed since 1970 JANUARY 01, 00:00:00 UTC) to EFI_TIME\r
- **/\r
-STATIC\r
-VOID\r
-EpochToEfiTime (\r
- IN UINTN EpochSeconds,\r
- OUT EFI_TIME *Time\r
- )\r
-{\r
- UINTN a;\r
- UINTN b;\r
- UINTN c;\r
- UINTN d;\r
- UINTN g;\r
- UINTN j;\r
- UINTN m;\r
- UINTN y;\r
- UINTN da;\r
- UINTN db;\r
- UINTN dc;\r
- UINTN dg;\r
- UINTN hh;\r
- UINTN mm;\r
- UINTN ss;\r
- UINTN J;\r
-\r
- J = (EpochSeconds / 86400) + 2440588;\r
- j = J + 32044;\r
- g = j / 146097;\r
- dg = j % 146097;\r
- c = (((dg / 36524) + 1) * 3) / 4;\r
- dc = dg - (c * 36524);\r
- b = dc / 1461;\r
- db = dc % 1461;\r
- a = (((db / 365) + 1) * 3) / 4;\r
- da = db - (a * 365);\r
- y = (g * 400) + (c * 100) + (b * 4) + a;\r
- m = (((da * 5) + 308) / 153) - 2;\r
- d = da - (((m + 4) * 153) / 5) + 122;\r
-\r
- Time->Year = y - 4800 + ((m + 2) / 12);\r
- Time->Month = ((m + 2) % 12) + 1;\r
- Time->Day = d + 1;\r
-\r
- ss = EpochSeconds % 60;\r
- a = (EpochSeconds - ss) / 60;\r
- mm = a % 60;\r
- b = (a - mm) / 60;\r
- hh = b % 24;\r
-\r
- Time->Hour = hh;\r
- Time->Minute = mm;\r
- Time->Second = ss;\r
- Time->Nanosecond = 0;\r
-\r
-}\r
-\r
-/**\r
- Returns the current time and date information, and the time-keeping capabilities\r
- of the hardware platform.\r
-\r
- @param Time A pointer to storage to receive a snapshot of the current time.\r
- @param Capabilities An optional pointer to a buffer to receive the real time clock\r
- device's capabilities.\r
-\r
- @retval EFI_SUCCESS The operation completed successfully.\r
- @retval EFI_INVALID_PARAMETER Time is NULL.\r
- @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-LibGetTime (\r
- OUT EFI_TIME *Time,\r
- OUT EFI_TIME_CAPABILITIES *Capabilities\r
- )\r
-{\r
- ASSERT (Time != NULL);\r
-\r
- //\r
- // For now, there is nothing that we can do besides returning a bogus time,\r
- // as Xen's timekeeping uses a shared info page which cannot be shared\r
- // between UEFI and the OS\r
- //\r
- EpochToEfiTime(1421770011, Time);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Sets the current local time and date information.\r
-\r
- @param Time A pointer to the current time.\r
-\r
- @retval EFI_SUCCESS The operation completed successfully.\r
- @retval EFI_INVALID_PARAMETER A time field is out of range.\r
- @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-LibSetTime (\r
- IN EFI_TIME *Time\r
- )\r
-{\r
- return EFI_DEVICE_ERROR;\r
-}\r
-\r
-\r
-/**\r
- Returns the current wakeup alarm clock setting.\r
-\r
- @param Enabled Indicates if the alarm is currently enabled or disabled.\r
- @param Pending Indicates if the alarm signal is pending and requires acknowledgement.\r
- @param Time The current alarm setting.\r
-\r
- @retval EFI_SUCCESS The alarm settings were returned.\r
- @retval EFI_INVALID_PARAMETER Any parameter is NULL.\r
- @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.\r
- @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-LibGetWakeupTime (\r
- OUT BOOLEAN *Enabled,\r
- OUT BOOLEAN *Pending,\r
- OUT EFI_TIME *Time\r
- )\r
-{\r
- return EFI_UNSUPPORTED;\r
-}\r
-\r
-/**\r
- Sets the system wakeup alarm clock time.\r
-\r
- @param Enabled Enable or disable the wakeup alarm.\r
- @param Time If Enable is TRUE, the time to set the wakeup alarm for.\r
-\r
- @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If\r
- Enable is FALSE, then the wakeup alarm was disabled.\r
- @retval EFI_INVALID_PARAMETER A time field is out of range.\r
- @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.\r
- @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-LibSetWakeupTime (\r
- IN BOOLEAN Enabled,\r
- OUT EFI_TIME *Time\r
- )\r
-{\r
- return EFI_UNSUPPORTED;\r
-}\r
-\r
-/**\r
- This is the declaration of an EFI image entry point. This can be the entry point to an application\r
- written to this specification, an EFI boot service driver, or an EFI runtime driver.\r
-\r
- @param ImageHandle Handle that identifies the loaded image.\r
- @param SystemTable System Table for this image.\r
-\r
- @retval EFI_SUCCESS The operation completed successfully.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-LibRtcInitialize (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-{\r
- return EFI_SUCCESS;\r
-}\r
+++ /dev/null
-#/** @file\r
-#\r
-# Copyright (c) 2015, L Ltd. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = XenRealTimeClockLib\r
- FILE_GUID = EC2557E8-7005-430B-9F6F-9BA109698248\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = RealTimeClockLib|DXE_CORE DXE_DRIVER UEFI_DRIVER DXE_RUNTIME_DRIVER UEFI_APPLICATION\r
-\r
-[Sources.common]\r
- XenRealTimeClockLib.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- OvmfPkg/OvmfPkg.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
-\r
-[LibraryClasses]\r
- UefiLib\r
- DebugLib\r
- DxeServicesTableLib\r
- UefiRuntimeLib\r
-\r
-[Guids]\r
- gEfiEventVirtualAddressChangeGuid\r
+++ /dev/null
-/** @file\r
- Provides the basic interfaces to abstract a PCI Host Bridge Resource Allocation\r
-\r
-Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials are\r
-licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include "PciHostBridge.h"\r
-\r
-//\r
-// Hard code: Root Bridge Number within the host bridge\r
-// Root Bridge's attribute\r
-// Root Bridge's device path\r
-// Root Bridge's resource aperture\r
-//\r
-UINTN RootBridgeNumber[1] = { 1 };\r
-\r
-UINT64 RootBridgeAttribute[1][1] = { { EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM } };\r
-\r
-EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[1][1] = {\r
- {\r
- {\r
- {\r
- {\r
- ACPI_DEVICE_PATH,\r
- ACPI_DP,\r
- {\r
- (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),\r
- (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)\r
- }\r
- },\r
- EISA_PNP_ID(0x0A03),\r
- 0\r
- },\r
-\r
- {\r
- END_DEVICE_PATH_TYPE,\r
- END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
- {\r
- END_DEVICE_PATH_LENGTH,\r
- 0\r
- }\r
- }\r
- }\r
- }\r
-};\r
-\r
-STATIC PCI_ROOT_BRIDGE_RESOURCE_APERTURE mResAperture[1][1];\r
-\r
-EFI_HANDLE mDriverImageHandle;\r
-\r
-PCI_HOST_BRIDGE_INSTANCE mPciHostBridgeInstanceTemplate = {\r
- PCI_HOST_BRIDGE_SIGNATURE, // Signature\r
- NULL, // HostBridgeHandle\r
- 0, // RootBridgeNumber\r
- {NULL, NULL}, // Head\r
- FALSE, // ResourceSubiteed\r
- TRUE, // CanRestarted\r
- {\r
- NotifyPhase,\r
- GetNextRootBridge,\r
- GetAttributes,\r
- StartBusEnumeration,\r
- SetBusNumbers,\r
- SubmitResources,\r
- GetProposedResources,\r
- PreprocessController\r
- }\r
-};\r
-\r
-//\r
-// Implementation\r
-//\r
-\r
-/**\r
- Entry point of this driver\r
-\r
- @param ImageHandle Handle of driver image\r
- @param SystemTable Point to EFI_SYSTEM_TABLE\r
-\r
- @retval EFI_ABORTED PCI host bridge not present\r
- @retval EFI_OUT_OF_RESOURCES Can not allocate memory resource\r
- @retval EFI_DEVICE_ERROR Can not install the protocol instance\r
- @retval EFI_SUCCESS Success to initialize the Pci host bridge.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-InitializePciHostBridge (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-{\r
- UINT64 MmioAttributes;\r
- EFI_STATUS Status;\r
- UINTN Loop1;\r
- UINTN Loop2;\r
- PCI_HOST_BRIDGE_INSTANCE *HostBridge;\r
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
-\r
- if (PcdGet64 (PcdPciExpressBaseAddress) == 0) {\r
- DEBUG ((EFI_D_INFO, "%a: PCI host bridge not present\n", __FUNCTION__));\r
- return EFI_ABORTED;\r
- }\r
-\r
- mDriverImageHandle = ImageHandle;\r
-\r
- mResAperture[0][0].BusBase = PcdGet32 (PcdPciBusMin);\r
- mResAperture[0][0].BusLimit = PcdGet32 (PcdPciBusMax);\r
-\r
- mResAperture[0][0].MemBase = PcdGet32 (PcdPciMmio32Base);\r
- mResAperture[0][0].MemLimit = (UINT64)PcdGet32 (PcdPciMmio32Base) +\r
- PcdGet32 (PcdPciMmio32Size) - 1;\r
-\r
- mResAperture[0][0].IoBase = PcdGet64 (PcdPciIoBase);\r
- mResAperture[0][0].IoLimit = PcdGet64 (PcdPciIoBase) +\r
- PcdGet64 (PcdPciIoSize) - 1;\r
- mResAperture[0][0].IoTranslation = PcdGet64 (PcdPciIoTranslation);\r
-\r
- //\r
- // Add IO and MMIO memory space, so that resources can be allocated in the\r
- // EfiPciHostBridgeAllocateResources phase.\r
- //\r
- Status = gDS->AddIoSpace (\r
- EfiGcdIoTypeIo,\r
- PcdGet64 (PcdPciIoBase),\r
- PcdGet64 (PcdPciIoSize)\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- MmioAttributes = FeaturePcdGet (PcdKludgeMapPciMmioAsCached) ?\r
- EFI_MEMORY_WB : EFI_MEMORY_UC;\r
-\r
- Status = gDS->AddMemorySpace (\r
- EfiGcdMemoryTypeMemoryMappedIo,\r
- PcdGet32 (PcdPciMmio32Base),\r
- PcdGet32 (PcdPciMmio32Size),\r
- MmioAttributes\r
- );\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "%a: AddMemorySpace: %r\n", __FUNCTION__, Status));\r
- return Status;\r
- }\r
-\r
- Status = gDS->SetMemorySpaceAttributes (\r
- PcdGet32 (PcdPciMmio32Base),\r
- PcdGet32 (PcdPciMmio32Size),\r
- MmioAttributes\r
- );\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "%a: SetMemorySpaceAttributes: %r\n", __FUNCTION__,\r
- Status));\r
- return Status;\r
- }\r
-\r
- //\r
- // Create Host Bridge Device Handle\r
- //\r
- for (Loop1 = 0; Loop1 < HOST_BRIDGE_NUMBER; Loop1++) {\r
- HostBridge = AllocateCopyPool (sizeof(PCI_HOST_BRIDGE_INSTANCE), &mPciHostBridgeInstanceTemplate);\r
- if (HostBridge == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
-\r
- HostBridge->RootBridgeNumber = RootBridgeNumber[Loop1];\r
- InitializeListHead (&HostBridge->Head);\r
-\r
- Status = gBS->InstallMultipleProtocolInterfaces (\r
- &HostBridge->HostBridgeHandle,\r
- &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc,\r
- NULL\r
- );\r
- if (EFI_ERROR (Status)) {\r
- FreePool (HostBridge);\r
- return EFI_DEVICE_ERROR;\r
- }\r
-\r
- //\r
- // Create Root Bridge Device Handle in this Host Bridge\r
- //\r
-\r
- for (Loop2 = 0; Loop2 < HostBridge->RootBridgeNumber; Loop2++) {\r
- PrivateData = AllocateZeroPool (sizeof(PCI_ROOT_BRIDGE_INSTANCE));\r
- if (PrivateData == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
-\r
- PrivateData->Signature = PCI_ROOT_BRIDGE_SIGNATURE;\r
- PrivateData->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[Loop1][Loop2];\r
-\r
- RootBridgeConstructor (\r
- &PrivateData->Io,\r
- HostBridge->HostBridgeHandle,\r
- RootBridgeAttribute[Loop1][Loop2],\r
- &mResAperture[Loop1][Loop2]\r
- );\r
-\r
- Status = gBS->InstallMultipleProtocolInterfaces(\r
- &PrivateData->Handle,\r
- &gEfiDevicePathProtocolGuid, PrivateData->DevicePath,\r
- &gEfiPciRootBridgeIoProtocolGuid, &PrivateData->Io,\r
- NULL\r
- );\r
- if (EFI_ERROR (Status)) {\r
- FreePool(PrivateData);\r
- return EFI_DEVICE_ERROR;\r
- }\r
-\r
- InsertTailList (&HostBridge->Head, &PrivateData->Link);\r
- }\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-/**\r
- These are the notifications from the PCI bus driver that it is about to enter a certain\r
- phase of the PCI enumeration process.\r
-\r
- This member function can be used to notify the host bridge driver to perform specific actions,\r
- including any chipset-specific initialization, so that the chipset is ready to enter the next phase.\r
- Eight notification points are defined at this time. See belows:\r
- EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data\r
- structures. The PCI enumerator should issue this notification\r
- before starting a fresh enumeration process. Enumeration cannot\r
- be restarted after sending any other notification such as\r
- EfiPciHostBridgeBeginBusAllocation.\r
- EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is\r
- required here. This notification can be used to perform any\r
- chipset-specific programming.\r
- EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No\r
- specific action is required here. This notification can be used to\r
- perform any chipset-specific programming.\r
- EfiPciHostBridgeBeginResourceAllocation\r
- The resource allocation phase is about to begin. No specific\r
- action is required here. This notification can be used to perform\r
- any chipset-specific programming.\r
- EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI\r
- root bridges. These resource settings are returned on the next call to\r
- GetProposedResources(). Before calling NotifyPhase() with a Phase of\r
- EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible\r
- for gathering I/O and memory requests for\r
- all the PCI root bridges and submitting these requests using\r
- SubmitResources(). This function pads the resource amount\r
- to suit the root bridge hardware, takes care of dependencies between\r
- the PCI root bridges, and calls the Global Coherency Domain (GCD)\r
- with the allocation request. In the case of padding, the allocated range\r
- could be bigger than what was requested.\r
- EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated\r
- resources (proposed resources) for all the PCI root bridges. After the\r
- hardware is programmed, reassigning resources will not be supported.\r
- The bus settings are not affected.\r
- EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI\r
- root bridges and resets the I/O and memory apertures to their initial\r
- state. The bus settings are not affected. If the request to allocate\r
- resources fails, the PCI enumerator can use this notification to\r
- deallocate previous resources, adjust the requests, and retry\r
- allocation.\r
- EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is\r
- required here. This notification can be used to perform any chipsetspecific\r
- programming.\r
-\r
- @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
- @param[in] Phase The phase during enumeration\r
-\r
- @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error\r
- is valid for a Phase of EfiPciHostBridgeAllocateResources if\r
- SubmitResources() has not been called for one or more\r
- PCI root bridges before this call\r
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid\r
- for a Phase of EfiPciHostBridgeSetResources.\r
- @retval EFI_INVALID_PARAMETER Invalid phase parameter\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
- This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the\r
- previously submitted resource requests cannot be fulfilled or\r
- were only partially fulfilled.\r
- @retval EFI_SUCCESS The notification was accepted without any errors.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-NotifyPhase(\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r
- )\r
-{\r
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
- PCI_RESOURCE_TYPE Index;\r
- LIST_ENTRY *List;\r
- EFI_PHYSICAL_ADDRESS BaseAddress;\r
- UINT64 AddrLen;\r
- UINTN BitsOfAlignment;\r
- EFI_STATUS Status;\r
- EFI_STATUS ReturnStatus;\r
-\r
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
-\r
- switch (Phase) {\r
-\r
- case EfiPciHostBridgeBeginEnumeration:\r
- if (HostBridgeInstance->CanRestarted) {\r
- //\r
- // Reset the Each Root Bridge\r
- //\r
- List = HostBridgeInstance->Head.ForwardLink;\r
-\r
- while (List != &HostBridgeInstance->Head) {\r
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
- for (Index = TypeIo; Index < TypeMax; Index++) {\r
- RootBridgeInstance->ResAllocNode[Index].Type = Index;\r
- RootBridgeInstance->ResAllocNode[Index].Base = 0;\r
- RootBridgeInstance->ResAllocNode[Index].Length = 0;\r
- RootBridgeInstance->ResAllocNode[Index].Status = ResNone;\r
- }\r
-\r
- List = List->ForwardLink;\r
- }\r
-\r
- HostBridgeInstance->ResourceSubmited = FALSE;\r
- HostBridgeInstance->CanRestarted = TRUE;\r
- } else {\r
- //\r
- // Can not restart\r
- //\r
- return EFI_NOT_READY;\r
- }\r
- break;\r
-\r
- case EfiPciHostBridgeEndEnumeration:\r
- break;\r
-\r
- case EfiPciHostBridgeBeginBusAllocation:\r
- //\r
- // No specific action is required here, can perform any chipset specific programing\r
- //\r
- HostBridgeInstance->CanRestarted = FALSE;\r
- break;\r
-\r
- case EfiPciHostBridgeEndBusAllocation:\r
- //\r
- // No specific action is required here, can perform any chipset specific programing\r
- //\r
- //HostBridgeInstance->CanRestarted = FALSE;\r
- break;\r
-\r
- case EfiPciHostBridgeBeginResourceAllocation:\r
- //\r
- // No specific action is required here, can perform any chipset specific programing\r
- //\r
- //HostBridgeInstance->CanRestarted = FALSE;\r
- break;\r
-\r
- case EfiPciHostBridgeAllocateResources:\r
- ReturnStatus = EFI_SUCCESS;\r
- if (HostBridgeInstance->ResourceSubmited) {\r
- //\r
- // Take care of the resource dependencies between the root bridges\r
- //\r
- List = HostBridgeInstance->Head.ForwardLink;\r
-\r
- while (List != &HostBridgeInstance->Head) {\r
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
- for (Index = TypeIo; Index < TypeBus; Index++) {\r
- if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {\r
-\r
- AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
-\r
- //\r
- // Get the number of '1' in Alignment.\r
- //\r
- BitsOfAlignment = (UINTN) (HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1);\r
-\r
- switch (Index) {\r
-\r
- case TypeIo:\r
- //\r
- // It is impossible for this chipset to align 0xFFFF for IO16\r
- // So clear it\r
- //\r
- if (BitsOfAlignment >= 16) {\r
- BitsOfAlignment = 0;\r
- }\r
-\r
- BaseAddress = mResAperture[0][0].IoLimit;\r
- Status = gDS->AllocateIoSpace (\r
- EfiGcdAllocateMaxAddressSearchTopDown,\r
- EfiGcdIoTypeIo,\r
- BitsOfAlignment,\r
- AddrLen,\r
- &BaseAddress,\r
- mDriverImageHandle,\r
- NULL\r
- );\r
-\r
- if (!EFI_ERROR (Status)) {\r
- RootBridgeInstance->ResAllocNode[Index].Base = (UINTN)BaseAddress;\r
- RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;\r
- } else {\r
- ReturnStatus = Status;\r
- if (Status != EFI_OUT_OF_RESOURCES) {\r
- RootBridgeInstance->ResAllocNode[Index].Length = 0;\r
- }\r
- }\r
-\r
- break;\r
-\r
-\r
- case TypeMem32:\r
- //\r
- // It is impossible for this chipset to align 0xFFFFFFFF for Mem32\r
- // So clear it\r
- //\r
-\r
- if (BitsOfAlignment >= 32) {\r
- BitsOfAlignment = 0;\r
- }\r
-\r
- BaseAddress = mResAperture[0][0].MemLimit;\r
- Status = gDS->AllocateMemorySpace (\r
- EfiGcdAllocateMaxAddressSearchTopDown,\r
- EfiGcdMemoryTypeMemoryMappedIo,\r
- BitsOfAlignment,\r
- AddrLen,\r
- &BaseAddress,\r
- mDriverImageHandle,\r
- NULL\r
- );\r
-\r
- if (!EFI_ERROR (Status)) {\r
- // We were able to allocate the PCI memory\r
- RootBridgeInstance->ResAllocNode[Index].Base = (UINTN)BaseAddress;\r
- RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;\r
-\r
- } else {\r
- // Not able to allocate enough PCI memory\r
- ReturnStatus = Status;\r
-\r
- if (Status != EFI_OUT_OF_RESOURCES) {\r
- RootBridgeInstance->ResAllocNode[Index].Length = 0;\r
- }\r
- ASSERT (FALSE);\r
- }\r
- break;\r
-\r
- case TypePMem32:\r
- case TypeMem64:\r
- case TypePMem64:\r
- ReturnStatus = EFI_ABORTED;\r
- break;\r
- default:\r
- ASSERT (FALSE);\r
- break;\r
- }; //end switch\r
- }\r
- }\r
-\r
- List = List->ForwardLink;\r
- }\r
-\r
- return ReturnStatus;\r
- } else {\r
- return EFI_NOT_READY;\r
- }\r
-\r
- case EfiPciHostBridgeSetResources:\r
- break;\r
-\r
- case EfiPciHostBridgeFreeResources:\r
- ReturnStatus = EFI_SUCCESS;\r
- List = HostBridgeInstance->Head.ForwardLink;\r
- while (List != &HostBridgeInstance->Head) {\r
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
- for (Index = TypeIo; Index < TypeBus; Index++) {\r
- if (RootBridgeInstance->ResAllocNode[Index].Status == ResAllocated) {\r
- AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
- BaseAddress = RootBridgeInstance->ResAllocNode[Index].Base;\r
- switch (Index) {\r
-\r
- case TypeIo:\r
- Status = gDS->FreeIoSpace (BaseAddress, AddrLen);\r
- if (EFI_ERROR (Status)) {\r
- ReturnStatus = Status;\r
- }\r
- break;\r
-\r
- case TypeMem32:\r
- Status = gDS->FreeMemorySpace (BaseAddress, AddrLen);\r
- if (EFI_ERROR (Status)) {\r
- ReturnStatus = Status;\r
- }\r
- break;\r
-\r
- case TypePMem32:\r
- break;\r
-\r
- case TypeMem64:\r
- break;\r
-\r
- case TypePMem64:\r
- break;\r
-\r
- default:\r
- ASSERT (FALSE);\r
- break;\r
-\r
- }; //end switch\r
- RootBridgeInstance->ResAllocNode[Index].Type = Index;\r
- RootBridgeInstance->ResAllocNode[Index].Base = 0;\r
- RootBridgeInstance->ResAllocNode[Index].Length = 0;\r
- RootBridgeInstance->ResAllocNode[Index].Status = ResNone;\r
- }\r
- }\r
-\r
- List = List->ForwardLink;\r
- }\r
-\r
- HostBridgeInstance->ResourceSubmited = FALSE;\r
- HostBridgeInstance->CanRestarted = TRUE;\r
- return ReturnStatus;\r
-\r
- case EfiPciHostBridgeEndResourceAllocation:\r
- HostBridgeInstance->CanRestarted = FALSE;\r
- break;\r
-\r
- default:\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Return the device handle of the next PCI root bridge that is associated with this Host Bridge.\r
-\r
- This function is called multiple times to retrieve the device handles of all the PCI root bridges that\r
- are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI\r
- root bridges. On each call, the handle that was returned by the previous call is passed into the\r
- interface, and on output the interface returns the device handle of the next PCI root bridge. The\r
- caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
- for that root bridge. When there are no more PCI root bridges to report, the interface returns\r
- EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they\r
- are returned by this function.\r
- For D945 implementation, there is only one root bridge in PCI host bridge.\r
-\r
- @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
- @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge.\r
-\r
- @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the\r
- specific Host bridge and return EFI_SUCCESS.\r
- @retval EFI_NOT_FOUND Can not find the any more root bridge in specific host bridge.\r
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was\r
- returned on a previous call to GetNextRootBridge().\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-GetNextRootBridge(\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN OUT EFI_HANDLE *RootBridgeHandle\r
- )\r
-{\r
- BOOLEAN NoRootBridge;\r
- LIST_ENTRY *List;\r
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
-\r
- NoRootBridge = TRUE;\r
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
- List = HostBridgeInstance->Head.ForwardLink;\r
-\r
-\r
- while (List != &HostBridgeInstance->Head) {\r
- NoRootBridge = FALSE;\r
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
- if (*RootBridgeHandle == NULL) {\r
- //\r
- // Return the first Root Bridge Handle of the Host Bridge\r
- //\r
- *RootBridgeHandle = RootBridgeInstance->Handle;\r
- return EFI_SUCCESS;\r
- } else {\r
- if (*RootBridgeHandle == RootBridgeInstance->Handle) {\r
- //\r
- // Get next if have\r
- //\r
- List = List->ForwardLink;\r
- if (List!=&HostBridgeInstance->Head) {\r
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
- *RootBridgeHandle = RootBridgeInstance->Handle;\r
- return EFI_SUCCESS;\r
- } else {\r
- return EFI_NOT_FOUND;\r
- }\r
- }\r
- }\r
-\r
- List = List->ForwardLink;\r
- } //end while\r
-\r
- if (NoRootBridge) {\r
- return EFI_NOT_FOUND;\r
- } else {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-}\r
-\r
-/**\r
- Returns the allocation attributes of a PCI root bridge.\r
-\r
- The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary\r
- from one PCI root bridge to another. These attributes are different from the decode-related\r
- attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The\r
- RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device\r
- handles of all the root bridges that are associated with this host bridge must be obtained by calling\r
- GetNextRootBridge(). The attributes are static in the sense that they do not change during or\r
- after the enumeration process. The hardware may provide mechanisms to change the attributes on\r
- the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is\r
- installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in\r
- "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.\r
- For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to\r
- include requests for the prefetchable memory in the nonprefetchable memory pool and not request any\r
- prefetchable memory.\r
- Attribute Description\r
- ------------------------------------ ----------------------------------------------------------------------\r
- EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root bridge does not support separate\r
- windows for nonprefetchable and prefetchable memory. A PCI bus\r
- driver needs to include requests for prefetchable memory in the\r
- nonprefetchable memory pool.\r
-\r
- EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root bridge supports 64-bit memory\r
- windows. If this bit is not set, the PCI bus driver needs to include\r
- requests for a 64-bit memory address in the corresponding 32-bit\r
- memory pool.\r
-\r
- @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
- @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested. Type\r
- EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.\r
- @param[out] Attributes The pointer to attribte of root bridge, it is output parameter\r
-\r
- @retval EFI_INVALID_PARAMETER Attribute pointer is NULL\r
- @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.\r
- @retval EFI_SUCCESS Success to get attribute of interested root bridge.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-GetAttributes(\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- OUT UINT64 *Attributes\r
- )\r
-{\r
- LIST_ENTRY *List;\r
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
-\r
- if (Attributes == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
- List = HostBridgeInstance->Head.ForwardLink;\r
-\r
- while (List != &HostBridgeInstance->Head) {\r
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
- if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
- *Attributes = RootBridgeInstance->RootBridgeAttrib;\r
- return EFI_SUCCESS;\r
- }\r
- List = List->ForwardLink;\r
- }\r
-\r
- //\r
- // RootBridgeHandle is not an EFI_HANDLE\r
- // that was returned on a previous call to GetNextRootBridge()\r
- //\r
- return EFI_INVALID_PARAMETER;\r
-}\r
-\r
-/**\r
- Sets up the specified PCI root bridge for the bus enumeration process.\r
-\r
- This member function sets up the root bridge for bus enumeration and returns the PCI bus range\r
- over which the search should be performed in ACPI 2.0 resource descriptor format.\r
-\r
- @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.\r
- @param[in] RootBridgeHandle The PCI Root Bridge to be set up.\r
- @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor.\r
-\r
- @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle\r
- @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.\r
- @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-StartBusEnumeration(\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- OUT VOID **Configuration\r
- )\r
-{\r
- LIST_ENTRY *List;\r
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
- VOID *Buffer;\r
- UINT8 *Temp;\r
- UINT64 BusStart;\r
- UINT64 BusEnd;\r
-\r
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
- List = HostBridgeInstance->Head.ForwardLink;\r
-\r
- while (List != &HostBridgeInstance->Head) {\r
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
- if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
- //\r
- // Set up the Root Bridge for Bus Enumeration\r
- //\r
- BusStart = RootBridgeInstance->BusBase;\r
- BusEnd = RootBridgeInstance->BusLimit;\r
- //\r
- // Program the Hardware(if needed) if error return EFI_DEVICE_ERROR\r
- //\r
-\r
- Buffer = AllocatePool (sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));\r
- if (Buffer == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
-\r
- Temp = (UINT8 *)Buffer;\r
-\r
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Desc = 0x8A;\r
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Len = 0x2B;\r
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->ResType = 2;\r
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->GenFlag = 0;\r
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->SpecificFlag = 0;\r
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrSpaceGranularity = 0;\r
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMin = BusStart;\r
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMax = 0;\r
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrTranslationOffset = 0;\r
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrLen = BusEnd - BusStart + 1;\r
-\r
- Temp = Temp + sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
- ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;\r
- ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;\r
-\r
- *Configuration = Buffer;\r
- return EFI_SUCCESS;\r
- }\r
- List = List->ForwardLink;\r
- }\r
-\r
- return EFI_INVALID_PARAMETER;\r
-}\r
-\r
-/**\r
- Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.\r
-\r
- This member function programs the specified PCI root bridge to decode the bus range that is\r
- specified by the input parameter Configuration.\r
- The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.\r
-\r
- @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance\r
- @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be programmed\r
- @param[in] Configuration The pointer to the PCI bus resource descriptor\r
-\r
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
- @retval EFI_INVALID_PARAMETER Configuration is NULL.\r
- @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.\r
- @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource descriptor.\r
- @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than\r
- bus descriptors.\r
- @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource descriptors.\r
- @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.\r
- @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.\r
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
- @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-SetBusNumbers(\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- IN VOID *Configuration\r
- )\r
-{\r
- LIST_ENTRY *List;\r
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
- UINT8 *Ptr;\r
- UINTN BusStart;\r
- UINTN BusEnd;\r
- UINTN BusLen;\r
-\r
- if (Configuration == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- Ptr = Configuration;\r
-\r
- //\r
- // Check the Configuration is valid\r
- //\r
- if(*Ptr != ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->ResType != 2) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- Ptr += sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
- if (*Ptr != ACPI_END_TAG_DESCRIPTOR) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
- List = HostBridgeInstance->Head.ForwardLink;\r
-\r
- Ptr = Configuration;\r
-\r
- while (List != &HostBridgeInstance->Head) {\r
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
- if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
- BusStart = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrRangeMin;\r
- BusLen = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrLen;\r
- BusEnd = BusStart + BusLen - 1;\r
-\r
- if (BusStart > BusEnd) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- if ((BusStart < RootBridgeInstance->BusBase) || (BusEnd > RootBridgeInstance->BusLimit)) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // Update the Bus Range\r
- //\r
- RootBridgeInstance->ResAllocNode[TypeBus].Base = BusStart;\r
- RootBridgeInstance->ResAllocNode[TypeBus].Length = BusLen;\r
- RootBridgeInstance->ResAllocNode[TypeBus].Status = ResAllocated;\r
-\r
- //\r
- // Program the Root Bridge Hardware\r
- //\r
-\r
- return EFI_SUCCESS;\r
- }\r
-\r
- List = List->ForwardLink;\r
- }\r
-\r
- return EFI_INVALID_PARAMETER;\r
-}\r
-\r
-\r
-/**\r
- Submits the I/O and memory resource requirements for the specified PCI root bridge.\r
-\r
- This function is used to submit all the I/O and memory resources that are required by the specified\r
- PCI root bridge. The input parameter Configuration is used to specify the following:\r
- - The various types of resources that are required\r
- - The associated lengths in terms of ACPI 2.0 resource descriptor format\r
-\r
- @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
- @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being submitted.\r
- @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor.\r
-\r
- @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were accepted.\r
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
- @retval EFI_INVALID_PARAMETER Configuration is NULL.\r
- @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.\r
- @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are\r
- not supported by this PCI root bridge. This error will happen if the caller\r
- did not combine resources according to Attributes that were returned by\r
- GetAllocAttributes().\r
- @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.\r
- @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-SubmitResources(\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- IN VOID *Configuration\r
- )\r
-{\r
- LIST_ENTRY *List;\r
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
- UINT8 *Temp;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
- UINT64 AddrLen;\r
- UINT64 Alignment;\r
-\r
- //\r
- // Check the input parameter: Configuration\r
- //\r
- if (Configuration == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
- List = HostBridgeInstance->Head.ForwardLink;\r
-\r
- Temp = (UINT8 *)Configuration;\r
- while ( *Temp == 0x8A) {\r
- Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ;\r
- }\r
- if (*Temp != 0x79) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- Temp = (UINT8 *)Configuration;\r
- while (List != &HostBridgeInstance->Head) {\r
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
- if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
- for (;\r
- *Temp == 0x8A;\r
- Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR)\r
- ) {\r
- Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;\r
-\r
- //\r
- // Check Address Length\r
- //\r
- if (Ptr->AddrLen == 0) {\r
- HostBridgeInstance->ResourceSubmited = TRUE;\r
- continue;\r
- }\r
- if (Ptr->AddrLen > 0xffffffff) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // Check address range alignment\r
- //\r
- if (Ptr->AddrRangeMax >= 0xffffffff || Ptr->AddrRangeMax != (GetPowerOfTwo64 (Ptr->AddrRangeMax + 1) - 1)) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- switch (Ptr->ResType) {\r
-\r
- case 0:\r
-\r
- //\r
- // Check invalid Address Sapce Granularity\r
- //\r
- if (Ptr->AddrSpaceGranularity != 32) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // check the memory resource request is supported by PCI root bridge\r
- //\r
- if (RootBridgeInstance->RootBridgeAttrib == EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM &&\r
- Ptr->SpecificFlag == 0x06) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- AddrLen = Ptr->AddrLen;\r
- Alignment = Ptr->AddrRangeMax;\r
- if (Ptr->AddrSpaceGranularity == 32) {\r
- if (Ptr->SpecificFlag == 0x06) {\r
- //\r
- // Apply from GCD\r
- //\r
- RootBridgeInstance->ResAllocNode[TypePMem32].Status = ResSubmitted;\r
- } else {\r
- RootBridgeInstance->ResAllocNode[TypeMem32].Length = AddrLen;\r
- RootBridgeInstance->ResAllocNode[TypeMem32].Alignment = Alignment;\r
- RootBridgeInstance->ResAllocNode[TypeMem32].Status = ResRequested;\r
- HostBridgeInstance->ResourceSubmited = TRUE;\r
- }\r
- }\r
-\r
- if (Ptr->AddrSpaceGranularity == 64) {\r
- if (Ptr->SpecificFlag == 0x06) {\r
- RootBridgeInstance->ResAllocNode[TypePMem64].Status = ResSubmitted;\r
- } else {\r
- RootBridgeInstance->ResAllocNode[TypeMem64].Status = ResSubmitted;\r
- }\r
- }\r
- break;\r
-\r
- case 1:\r
- AddrLen = (UINTN) Ptr->AddrLen;\r
- Alignment = (UINTN) Ptr->AddrRangeMax;\r
- RootBridgeInstance->ResAllocNode[TypeIo].Length = AddrLen;\r
- RootBridgeInstance->ResAllocNode[TypeIo].Alignment = Alignment;\r
- RootBridgeInstance->ResAllocNode[TypeIo].Status = ResRequested;\r
- HostBridgeInstance->ResourceSubmited = TRUE;\r
- break;\r
-\r
- default:\r
- break;\r
- };\r
- }\r
-\r
- return EFI_SUCCESS;\r
- }\r
-\r
- List = List->ForwardLink;\r
- }\r
-\r
- return EFI_INVALID_PARAMETER;\r
-}\r
-\r
-/**\r
- Returns the proposed resource settings for the specified PCI root bridge.\r
-\r
- This member function returns the proposed resource settings for the specified PCI root bridge. The\r
- proposed resource settings are prepared when NotifyPhase() is called with a Phase of\r
- EfiPciHostBridgeAllocateResources. The output parameter Configuration\r
- specifies the following:\r
- - The various types of resources, excluding bus resources, that are allocated\r
- - The associated lengths in terms of ACPI 2.0 resource descriptor format\r
-\r
- @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
- @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.\r
- @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.\r
-\r
- @retval EFI_SUCCESS The requested parameters were returned.\r
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-GetProposedResources(\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- OUT VOID **Configuration\r
- )\r
-{\r
- LIST_ENTRY *List;\r
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
- UINTN Index;\r
- UINTN Number;\r
- VOID *Buffer;\r
- UINT8 *Temp;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
- UINT64 ResStatus;\r
-\r
- Buffer = NULL;\r
- Number = 0;\r
- //\r
- // Get the Host Bridge Instance from the resource allocation protocol\r
- //\r
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
- List = HostBridgeInstance->Head.ForwardLink;\r
-\r
- //\r
- // Enumerate the root bridges in this host bridge\r
- //\r
- while (List != &HostBridgeInstance->Head) {\r
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
- if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
- for (Index = 0; Index < TypeBus; Index ++) {\r
- if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {\r
- Number ++;\r
- }\r
- }\r
-\r
- if (Number == 0) {\r
- EFI_ACPI_END_TAG_DESCRIPTOR *End;\r
-\r
- End = AllocateZeroPool (sizeof *End);\r
- if (End == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
- End->Desc = ACPI_END_TAG_DESCRIPTOR;\r
- *Configuration = End;\r
- return EFI_SUCCESS;\r
- }\r
-\r
- Buffer = AllocateZeroPool (Number * sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));\r
- if (Buffer == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
-\r
- Temp = Buffer;\r
- for (Index = 0; Index < TypeBus; Index ++) {\r
- if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {\r
- Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;\r
- ResStatus = RootBridgeInstance->ResAllocNode[Index].Status;\r
-\r
- switch (Index) {\r
-\r
- case TypeIo:\r
- //\r
- // Io\r
- //\r
- Ptr->Desc = 0x8A;\r
- Ptr->Len = 0x2B;\r
- Ptr->ResType = 1;\r
- Ptr->GenFlag = 0;\r
- Ptr->SpecificFlag = 0;\r
- Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
- Ptr->AddrRangeMax = 0;\r
- Ptr->AddrTranslationOffset = \\r
- (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;\r
- Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
- break;\r
-\r
- case TypeMem32:\r
- //\r
- // Memory 32\r
- //\r
- Ptr->Desc = 0x8A;\r
- Ptr->Len = 0x2B;\r
- Ptr->ResType = 0;\r
- Ptr->GenFlag = 0;\r
- Ptr->SpecificFlag = 0;\r
- Ptr->AddrSpaceGranularity = 32;\r
- Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
- Ptr->AddrRangeMax = 0;\r
- Ptr->AddrTranslationOffset = \\r
- (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;\r
- Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
- break;\r
-\r
- case TypePMem32:\r
- //\r
- // Prefetch memory 32\r
- //\r
- Ptr->Desc = 0x8A;\r
- Ptr->Len = 0x2B;\r
- Ptr->ResType = 0;\r
- Ptr->GenFlag = 0;\r
- Ptr->SpecificFlag = 6;\r
- Ptr->AddrSpaceGranularity = 32;\r
- Ptr->AddrRangeMin = 0;\r
- Ptr->AddrRangeMax = 0;\r
- Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;\r
- Ptr->AddrLen = 0;\r
- break;\r
-\r
- case TypeMem64:\r
- //\r
- // Memory 64\r
- //\r
- Ptr->Desc = 0x8A;\r
- Ptr->Len = 0x2B;\r
- Ptr->ResType = 0;\r
- Ptr->GenFlag = 0;\r
- Ptr->SpecificFlag = 0;\r
- Ptr->AddrSpaceGranularity = 64;\r
- Ptr->AddrRangeMin = 0;\r
- Ptr->AddrRangeMax = 0;\r
- Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;\r
- Ptr->AddrLen = 0;\r
- break;\r
-\r
- case TypePMem64:\r
- //\r
- // Prefetch memory 64\r
- //\r
- Ptr->Desc = 0x8A;\r
- Ptr->Len = 0x2B;\r
- Ptr->ResType = 0;\r
- Ptr->GenFlag = 0;\r
- Ptr->SpecificFlag = 6;\r
- Ptr->AddrSpaceGranularity = 64;\r
- Ptr->AddrRangeMin = 0;\r
- Ptr->AddrRangeMax = 0;\r
- Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;\r
- Ptr->AddrLen = 0;\r
- break;\r
- };\r
-\r
- Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
- }\r
- }\r
-\r
- ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;\r
- ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;\r
-\r
- *Configuration = Buffer;\r
-\r
- return EFI_SUCCESS;\r
- }\r
-\r
- List = List->ForwardLink;\r
- }\r
-\r
- return EFI_INVALID_PARAMETER;\r
-}\r
-\r
-/**\r
- Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r
- stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r
- PCI controllers before enumeration.\r
-\r
- This function is called during the PCI enumeration process. No specific action is expected from this\r
- member function. It allows the host bridge driver to preinitialize individual PCI controllers before\r
- enumeration.\r
-\r
- @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
- @param RootBridgeHandle The associated PCI root bridge handle. Type EFI_HANDLE is defined in\r
- InstallProtocolInterface() in the UEFI 2.0 Specification.\r
- @param PciAddress The address of the PCI device on the PCI bus. This address can be passed to the\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI\r
- configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for\r
- the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.\r
- @param Phase The phase of the PCI device enumeration.\r
-\r
- @retval EFI_SUCCESS The requested parameters were returned.\r
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
- @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in\r
- EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should\r
- not enumerate this device, including its child devices if it is a PCI-to-PCI\r
- bridge.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-PreprocessController (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
- IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
- )\r
-{\r
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
- LIST_ENTRY *List;\r
-\r
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
- List = HostBridgeInstance->Head.ForwardLink;\r
-\r
- //\r
- // Enumerate the root bridges in this host bridge\r
- //\r
- while (List != &HostBridgeInstance->Head) {\r
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
- if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
- break;\r
- }\r
- List = List->ForwardLink;\r
- }\r
- if (List == &HostBridgeInstance->Head) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- if ((UINT32)Phase > EfiPciBeforeResourceCollection) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
+++ /dev/null
-/** @file\r
- The Header file of the Pci Host Bridge Driver\r
-\r
- Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials are\r
- licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#ifndef _PCI_HOST_BRIDGE_H_\r
-#define _PCI_HOST_BRIDGE_H_\r
-\r
-#include <PiDxe.h>\r
-\r
-#include <IndustryStandard/Pci.h>\r
-#include <IndustryStandard/Acpi.h>\r
-\r
-#include <Protocol/PciHostBridgeResourceAllocation.h>\r
-#include <Protocol/PciRootBridgeIo.h>\r
-#include <Protocol/Metronome.h>\r
-#include <Protocol/DevicePath.h>\r
-\r
-\r
-#include <Library/BaseLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <Library/UefiLib.h>\r
-#include <Library/UefiBootServicesTableLib.h>\r
-#include <Library/DxeServicesTableLib.h>\r
-#include <Library/DevicePathLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/PciLib.h>\r
-#include <Library/PcdLib.h>\r
-\r
-//\r
-// Hard code the host bridge number in the platform.\r
-// In this chipset, there is only one host bridge.\r
-//\r
-#define HOST_BRIDGE_NUMBER 1\r
-\r
-#define MAX_PCI_DEVICE_NUMBER 31\r
-#define MAX_PCI_FUNCTION_NUMBER 7\r
-#define MAX_PCI_REG_ADDRESS (SIZE_4KB - 1)\r
-\r
-typedef enum {\r
- IoOperation,\r
- MemOperation,\r
- PciOperation\r
-} OPERATION_TYPE;\r
-\r
-#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32('e', 'h', 's', 't')\r
-typedef struct {\r
- UINTN Signature;\r
- EFI_HANDLE HostBridgeHandle;\r
- UINTN RootBridgeNumber;\r
- LIST_ENTRY Head;\r
- BOOLEAN ResourceSubmited;\r
- BOOLEAN CanRestarted;\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc;\r
-} PCI_HOST_BRIDGE_INSTANCE;\r
-\r
-#define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) \\r
- CR(a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)\r
-\r
-//\r
-// HostBridge Resource Allocation interface\r
-//\r
-\r
-/**\r
- These are the notifications from the PCI bus driver that it is about to enter a certain\r
- phase of the PCI enumeration process.\r
-\r
- This member function can be used to notify the host bridge driver to perform specific actions,\r
- including any chipset-specific initialization, so that the chipset is ready to enter the next phase.\r
- Eight notification points are defined at this time. See belows:\r
- EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data\r
- structures. The PCI enumerator should issue this notification\r
- before starting a fresh enumeration process. Enumeration cannot\r
- be restarted after sending any other notification such as\r
- EfiPciHostBridgeBeginBusAllocation.\r
- EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is\r
- required here. This notification can be used to perform any\r
- chipset-specific programming.\r
- EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No\r
- specific action is required here. This notification can be used to\r
- perform any chipset-specific programming.\r
- EfiPciHostBridgeBeginResourceAllocation\r
- The resource allocation phase is about to begin. No specific\r
- action is required here. This notification can be used to perform\r
- any chipset-specific programming.\r
- EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI\r
- root bridges. These resource settings are returned on the next call to\r
- GetProposedResources(). Before calling NotifyPhase() with a Phase of\r
- EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible\r
- for gathering I/O and memory requests for\r
- all the PCI root bridges and submitting these requests using\r
- SubmitResources(). This function pads the resource amount\r
- to suit the root bridge hardware, takes care of dependencies between\r
- the PCI root bridges, and calls the Global Coherency Domain (GCD)\r
- with the allocation request. In the case of padding, the allocated range\r
- could be bigger than what was requested.\r
- EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated\r
- resources (proposed resources) for all the PCI root bridges. After the\r
- hardware is programmed, reassigning resources will not be supported.\r
- The bus settings are not affected.\r
- EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI\r
- root bridges and resets the I/O and memory apertures to their initial\r
- state. The bus settings are not affected. If the request to allocate\r
- resources fails, the PCI enumerator can use this notification to\r
- deallocate previous resources, adjust the requests, and retry\r
- allocation.\r
- EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is\r
- required here. This notification can be used to perform any chipsetspecific\r
- programming.\r
-\r
- @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
- @param[in] Phase The phase during enumeration\r
-\r
- @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error\r
- is valid for a Phase of EfiPciHostBridgeAllocateResources if\r
- SubmitResources() has not been called for one or more\r
- PCI root bridges before this call\r
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid\r
- for a Phase of EfiPciHostBridgeSetResources.\r
- @retval EFI_INVALID_PARAMETER Invalid phase parameter\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
- This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the\r
- previously submitted resource requests cannot be fulfilled or\r
- were only partially fulfilled.\r
- @retval EFI_SUCCESS The notification was accepted without any errors.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-NotifyPhase(\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r
- );\r
-\r
-/**\r
- Return the device handle of the next PCI root bridge that is associated with this Host Bridge.\r
-\r
- This function is called multiple times to retrieve the device handles of all the PCI root bridges that\r
- are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI\r
- root bridges. On each call, the handle that was returned by the previous call is passed into the\r
- interface, and on output the interface returns the device handle of the next PCI root bridge. The\r
- caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
- for that root bridge. When there are no more PCI root bridges to report, the interface returns\r
- EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they\r
- are returned by this function.\r
- For D945 implementation, there is only one root bridge in PCI host bridge.\r
-\r
- @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
- @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge.\r
-\r
- @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the\r
- specific Host bridge and return EFI_SUCCESS.\r
- @retval EFI_NOT_FOUND Can not find the any more root bridge in specific host bridge.\r
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was\r
- returned on a previous call to GetNextRootBridge().\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-GetNextRootBridge(\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN OUT EFI_HANDLE *RootBridgeHandle\r
- );\r
-\r
-/**\r
- Returns the allocation attributes of a PCI root bridge.\r
-\r
- The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary\r
- from one PCI root bridge to another. These attributes are different from the decode-related\r
- attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The\r
- RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device\r
- handles of all the root bridges that are associated with this host bridge must be obtained by calling\r
- GetNextRootBridge(). The attributes are static in the sense that they do not change during or\r
- after the enumeration process. The hardware may provide mechanisms to change the attributes on\r
- the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is\r
- installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in\r
- "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.\r
- For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to\r
- include requests for the prefetchable memory in the nonprefetchable memory pool and not request any\r
- prefetchable memory.\r
- Attribute Description\r
- ------------------------------------ ----------------------------------------------------------------------\r
- EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root bridge does not support separate\r
- windows for nonprefetchable and prefetchable memory. A PCI bus\r
- driver needs to include requests for prefetchable memory in the\r
- nonprefetchable memory pool.\r
-\r
- EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root bridge supports 64-bit memory\r
- windows. If this bit is not set, the PCI bus driver needs to include\r
- requests for a 64-bit memory address in the corresponding 32-bit\r
- memory pool.\r
-\r
- @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
- @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested. Type\r
- EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.\r
- @param[out] Attributes The pointer to attribte of root bridge, it is output parameter\r
-\r
- @retval EFI_INVALID_PARAMETER Attribute pointer is NULL\r
- @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.\r
- @retval EFI_SUCCESS Success to get attribute of interested root bridge.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-GetAttributes(\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- OUT UINT64 *Attributes\r
- );\r
-\r
-/**\r
- Sets up the specified PCI root bridge for the bus enumeration process.\r
-\r
- This member function sets up the root bridge for bus enumeration and returns the PCI bus range\r
- over which the search should be performed in ACPI 2.0 resource descriptor format.\r
-\r
- @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.\r
- @param[in] RootBridgeHandle The PCI Root Bridge to be set up.\r
- @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor.\r
-\r
- @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle\r
- @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.\r
- @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-StartBusEnumeration(\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- OUT VOID **Configuration\r
- );\r
-\r
-/**\r
- Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.\r
-\r
- This member function programs the specified PCI root bridge to decode the bus range that is\r
- specified by the input parameter Configuration.\r
- The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.\r
-\r
- @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance\r
- @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be programmed\r
- @param[in] Configuration The pointer to the PCI bus resource descriptor\r
-\r
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
- @retval EFI_INVALID_PARAMETER Configuration is NULL.\r
- @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.\r
- @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource descriptor.\r
- @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than\r
- bus descriptors.\r
- @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource descriptors.\r
- @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.\r
- @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.\r
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
- @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-SetBusNumbers(\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- IN VOID *Configuration\r
- );\r
-\r
-/**\r
- Submits the I/O and memory resource requirements for the specified PCI root bridge.\r
-\r
- This function is used to submit all the I/O and memory resources that are required by the specified\r
- PCI root bridge. The input parameter Configuration is used to specify the following:\r
- - The various types of resources that are required\r
- - The associated lengths in terms of ACPI 2.0 resource descriptor format\r
-\r
- @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
- @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being submitted.\r
- @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor.\r
-\r
- @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were accepted.\r
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
- @retval EFI_INVALID_PARAMETER Configuration is NULL.\r
- @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.\r
- @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are\r
- not supported by this PCI root bridge. This error will happen if the caller\r
- did not combine resources according to Attributes that were returned by\r
- GetAllocAttributes().\r
- @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.\r
- @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-SubmitResources(\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- IN VOID *Configuration\r
- );\r
-\r
-/**\r
- Returns the proposed resource settings for the specified PCI root bridge.\r
-\r
- This member function returns the proposed resource settings for the specified PCI root bridge. The\r
- proposed resource settings are prepared when NotifyPhase() is called with a Phase of\r
- EfiPciHostBridgeAllocateResources. The output parameter Configuration\r
- specifies the following:\r
- - The various types of resources, excluding bus resources, that are allocated\r
- - The associated lengths in terms of ACPI 2.0 resource descriptor format\r
-\r
- @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
- @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.\r
- @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.\r
-\r
- @retval EFI_SUCCESS The requested parameters were returned.\r
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-GetProposedResources(\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- OUT VOID **Configuration\r
- );\r
-\r
-/**\r
- Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r
- stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r
- PCI controllers before enumeration.\r
-\r
- This function is called during the PCI enumeration process. No specific action is expected from this\r
- member function. It allows the host bridge driver to preinitialize individual PCI controllers before\r
- enumeration.\r
-\r
- @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
- @param RootBridgeHandle The associated PCI root bridge handle. Type EFI_HANDLE is defined in\r
- InstallProtocolInterface() in the UEFI 2.0 Specification.\r
- @param PciAddress The address of the PCI device on the PCI bus. This address can be passed to the\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI\r
- configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for\r
- the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.\r
- @param Phase The phase of the PCI device enumeration.\r
-\r
- @retval EFI_SUCCESS The requested parameters were returned.\r
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
- @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in\r
- EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should\r
- not enumerate this device, including its child devices if it is a PCI-to-PCI\r
- bridge.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-PreprocessController (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
- IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
- );\r
-\r
-\r
-//\r
-// Define resource status constant\r
-//\r
-#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL\r
-#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL\r
-\r
-\r
-//\r
-// Driver Instance Data Prototypes\r
-//\r
-\r
-typedef struct {\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;\r
- UINTN NumberOfBytes;\r
- UINTN NumberOfPages;\r
- EFI_PHYSICAL_ADDRESS HostAddress;\r
- EFI_PHYSICAL_ADDRESS MappedHostAddress;\r
-} MAP_INFO;\r
-\r
-typedef struct {\r
- ACPI_HID_DEVICE_PATH AcpiDevicePath;\r
- EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r
-} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;\r
-\r
-typedef struct {\r
- UINT64 BusBase;\r
- UINT64 BusLimit;\r
-\r
- UINT64 MemBase;\r
- UINT64 MemLimit;\r
-\r
- UINT64 IoBase;\r
- UINT64 IoLimit;\r
- UINT64 IoTranslation;\r
-} PCI_ROOT_BRIDGE_RESOURCE_APERTURE;\r
-\r
-typedef enum {\r
- TypeIo = 0,\r
- TypeMem32,\r
- TypePMem32,\r
- TypeMem64,\r
- TypePMem64,\r
- TypeBus,\r
- TypeMax\r
-} PCI_RESOURCE_TYPE;\r
-\r
-typedef enum {\r
- ResNone = 0,\r
- ResSubmitted,\r
- ResRequested,\r
- ResAllocated,\r
- ResStatusMax\r
-} RES_STATUS;\r
-\r
-typedef struct {\r
- PCI_RESOURCE_TYPE Type;\r
- UINT64 Base;\r
- UINT64 Length;\r
- UINT64 Alignment;\r
- RES_STATUS Status;\r
-} PCI_RES_NODE;\r
-\r
-#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32('e', '2', 'p', 'b')\r
-\r
-typedef struct {\r
- UINT32 Signature;\r
- LIST_ENTRY Link;\r
- EFI_HANDLE Handle;\r
- UINT64 RootBridgeAttrib;\r
- UINT64 Attributes;\r
- UINT64 Supports;\r
-\r
- //\r
- // Specific for this memory controller: Bus, I/O, Mem\r
- //\r
- PCI_RES_NODE ResAllocNode[6];\r
-\r
- //\r
- // Addressing for Memory and I/O and Bus arrange\r
- //\r
- UINT64 BusBase;\r
- UINT64 MemBase;\r
- UINT64 IoBase;\r
- UINT64 BusLimit;\r
- UINT64 MemLimit;\r
- UINT64 IoLimit;\r
- UINT64 IoTranslation;\r
-\r
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;\r
-\r
-} PCI_ROOT_BRIDGE_INSTANCE;\r
-\r
-\r
-//\r
-// Driver Instance Data Macros\r
-//\r
-#define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \\r
- CR(a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE)\r
-\r
-\r
-#define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) \\r
- CR(a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)\r
-\r
-/**\r
-\r
- Construct the Pci Root Bridge Io protocol\r
-\r
- @param Protocol Point to protocol instance\r
- @param HostBridgeHandle Handle of host bridge\r
- @param Attri Attribute of host bridge\r
- @param ResAperture ResourceAperture for host bridge\r
-\r
- @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.\r
-\r
-**/\r
-EFI_STATUS\r
-RootBridgeConstructor (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,\r
- IN EFI_HANDLE HostBridgeHandle,\r
- IN UINT64 Attri,\r
- IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture\r
- );\r
-\r
-#endif\r
+++ /dev/null
-## @file\r
-# The basic interfaces implementation to a single segment PCI Host Bridge driver.\r
-#\r
-# Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-##\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = PciHostBridge\r
- FILE_GUID = 9f609346-37cb-4eb7-801f-f55099373998\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
-\r
- ENTRY_POINT = InitializePciHostBridge\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
- ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationPkg.dec\r
-\r
-[LibraryClasses]\r
- UefiDriverEntryPoint\r
- UefiBootServicesTableLib\r
- DxeServicesTableLib\r
- UefiLib\r
- MemoryAllocationLib\r
- BaseMemoryLib\r
- BaseLib\r
- DebugLib\r
- DevicePathLib\r
- IoLib\r
- PciLib\r
- PcdLib\r
-\r
-[Sources]\r
- PciHostBridge.c\r
- PciRootBridgeIo.c\r
- PciHostBridge.h\r
-\r
-[Protocols]\r
- gEfiPciHostBridgeResourceAllocationProtocolGuid ## PRODUCES\r
- gEfiPciRootBridgeIoProtocolGuid ## PRODUCES\r
- gEfiMetronomeArchProtocolGuid ## CONSUMES\r
- gEfiDevicePathProtocolGuid ## PRODUCES\r
-\r
-[Pcd]\r
- gArmPlatformTokenSpaceGuid.PcdPciBusMin\r
- gArmPlatformTokenSpaceGuid.PcdPciBusMax\r
- gArmPlatformTokenSpaceGuid.PcdPciIoBase\r
- gArmPlatformTokenSpaceGuid.PcdPciIoSize\r
- gArmPlatformTokenSpaceGuid.PcdPciIoTranslation\r
- gArmPlatformTokenSpaceGuid.PcdPciMmio32Base\r
- gArmPlatformTokenSpaceGuid.PcdPciMmio32Size\r
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
-\r
-[FeaturePcd]\r
- gArmVirtualizationTokenSpaceGuid.PcdKludgeMapPciMmioAsCached\r
-\r
-[depex]\r
- gEfiMetronomeArchProtocolGuid AND\r
- gEfiCpuArchProtocolGuid\r
+++ /dev/null
-/** @file\r
- PCI Root Bridge Io Protocol implementation\r
-\r
-Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials are\r
-licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include "PciHostBridge.h"\r
-\r
-typedef struct {\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR SpaceDesp[TypeMax];\r
- EFI_ACPI_END_TAG_DESCRIPTOR EndDesp;\r
-} RESOURCE_CONFIGURATION;\r
-\r
-RESOURCE_CONFIGURATION Configuration = {\r
- {{0x8A, 0x2B, 1, 0, 0, 0, 0, 0, 0, 0},\r
- {0x8A, 0x2B, 0, 0, 0, 32, 0, 0, 0, 0},\r
- {0x8A, 0x2B, 0, 0, 6, 32, 0, 0, 0, 0},\r
- {0x8A, 0x2B, 0, 0, 0, 64, 0, 0, 0, 0},\r
- {0x8A, 0x2B, 0, 0, 6, 64, 0, 0, 0, 0},\r
- {0x8A, 0x2B, 2, 0, 0, 0, 0, 0, 0, 0}},\r
- {0x79, 0}\r
-};\r
-\r
-//\r
-// Protocol Member Function Prototypes\r
-//\r
-\r
-/**\r
- Polls an address in memory mapped I/O space until an exit condition is met, or\r
- a timeout occurs.\r
-\r
- This function provides a standard way to poll a PCI memory location. A PCI memory read\r
- operation is performed at the PCI memory address specified by Address for the width specified\r
- by Width. The result of this PCI memory read operation is stored in Result. This PCI memory\r
- read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result &\r
- Mask) is equal to Value.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Width Signifies the width of the memory operations.\r
- @param[in] Address The base address of the memory operations. The caller is\r
- responsible for aligning Address if required.\r
- @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask\r
- are ignored. The bits in the bytes below Width which are zero in\r
- Mask are ignored when polling the memory address.\r
- @param[in] Value The comparison value used for the polling exit criteria.\r
- @param[in] Delay The number of 100 ns units to poll. Note that timer available may\r
- be of poorer granularity.\r
- @param[out] Result Pointer to the last value read from the memory location.\r
-\r
- @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
- @retval EFI_INVALID_PARAMETER Width is invalid.\r
- @retval EFI_INVALID_PARAMETER Result is NULL.\r
- @retval EFI_TIMEOUT Delay expired before a match occurred.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoPollMem (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINT64 Mask,\r
- IN UINT64 Value,\r
- IN UINT64 Delay,\r
- OUT UINT64 *Result\r
- );\r
-\r
-/**\r
- Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r
- satisfied or after a defined duration.\r
-\r
- This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is\r
- performed at the PCI I/O address specified by Address for the width specified by Width.\r
- The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is\r
- repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal\r
- to Value.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Width Signifies the width of the I/O operations.\r
- @param[in] Address The base address of the I/O operations. The caller is responsible\r
- for aligning Address if required.\r
- @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask\r
- are ignored. The bits in the bytes below Width which are zero in\r
- Mask are ignored when polling the I/O address.\r
- @param[in] Value The comparison value used for the polling exit criteria.\r
- @param[in] Delay The number of 100 ns units to poll. Note that timer available may\r
- be of poorer granularity.\r
- @param[out] Result Pointer to the last value read from the memory location.\r
-\r
- @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
- @retval EFI_INVALID_PARAMETER Width is invalid.\r
- @retval EFI_INVALID_PARAMETER Result is NULL.\r
- @retval EFI_TIMEOUT Delay expired before a match occurred.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoPollIo (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINT64 Mask,\r
- IN UINT64 Value,\r
- IN UINT64 Delay,\r
- OUT UINT64 *Result\r
- );\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
-\r
- The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller\r
- registers in the PCI root bridge memory space.\r
- The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
- any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Width Signifies the width of the memory operation.\r
- @param[in] Address The base address of the memory operation. The caller is\r
- responsible for aligning the Address if required.\r
- @param[in] Count The number of memory operations to perform. Bytes moved is\r
- Width size * Count, starting at Address.\r
- @param[out] Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoMemRead (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- );\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
-\r
- The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller\r
- registers in the PCI root bridge memory space.\r
- The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
- any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Width Signifies the width of the memory operation.\r
- @param[in] Address The base address of the memory operation. The caller is\r
- responsible for aligning the Address if required.\r
- @param[in] Count The number of memory operations to perform. Bytes moved is\r
- Width size * Count, starting at Address.\r
- @param[in] Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoMemWrite (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- );\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Width Signifies the width of the memory operations.\r
- @param[in] UserAddress The base address of the I/O operation. The caller is responsible for\r
- aligning the Address if required.\r
- @param[in] Count The number of I/O operations to perform. Bytes moved is Width\r
- size * Count, starting at Address.\r
- @param[out] UserBuffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoIoRead (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 UserAddress,\r
- IN UINTN Count,\r
- OUT VOID *UserBuffer\r
- );\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Width Signifies the width of the memory operations.\r
- @param[in] UserAddress The base address of the I/O operation. The caller is responsible for\r
- aligning the Address if required.\r
- @param[in] Count The number of I/O operations to perform. Bytes moved is Width\r
- size * Count, starting at Address.\r
- @param[in] UserBuffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoIoWrite (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 UserAddress,\r
- IN UINTN Count,\r
- IN VOID *UserBuffer\r
- );\r
-\r
-/**\r
- Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI\r
- root bridge memory space.\r
-\r
- The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory\r
- space to another region of PCI root bridge memory space. This is especially useful for video scroll\r
- operation on a memory mapped video buffer.\r
- The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
- any alignment and memory width restrictions that a PCI root bridge on a platform might require.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
- @param[in] Width Signifies the width of the memory operations.\r
- @param[in] DestAddress The destination address of the memory operation. The caller is\r
- responsible for aligning the DestAddress if required.\r
- @param[in] SrcAddress The source address of the memory operation. The caller is\r
- responsible for aligning the SrcAddress if required.\r
- @param[in] Count The number of memory operations to perform. Bytes moved is\r
- Width size * Count, starting at DestAddress and SrcAddress.\r
-\r
- @retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoCopyMem (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 DestAddress,\r
- IN UINT64 SrcAddress,\r
- IN UINTN Count\r
- );\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.\r
-\r
- The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration\r
- registers for a PCI controller.\r
- The PCI Configuration operations are carried out exactly as requested. The caller is responsible for\r
- any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might\r
- require.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Width Signifies the width of the memory operations.\r
- @param[in] Address The address within the PCI configuration space for the PCI controller.\r
- @param[in] Count The number of PCI configuration operations to perform. Bytes\r
- moved is Width size * Count, starting at Address.\r
- @param[out] Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoPciRead (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- );\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.\r
-\r
- The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration\r
- registers for a PCI controller.\r
- The PCI Configuration operations are carried out exactly as requested. The caller is responsible for\r
- any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might\r
- require.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Width Signifies the width of the memory operations.\r
- @param[in] Address The address within the PCI configuration space for the PCI controller.\r
- @param[in] Count The number of PCI configuration operations to perform. Bytes\r
- moved is Width size * Count, starting at Address.\r
- @param[in] Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoPciWrite (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- );\r
-\r
-/**\r
- Provides the PCI controller-specific addresses required to access system memory from a\r
- DMA bus master.\r
-\r
- The Map() function provides the PCI controller specific addresses needed to access system\r
- memory. This function is used to map system memory for PCI bus master DMA accesses.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Operation Indicates if the bus master is going to read or write to system memory.\r
- @param[in] HostAddress The system memory address to map to the PCI controller.\r
- @param[in, out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.\r
- @param[out] DeviceAddress The resulting map address for the bus master PCI controller to use\r
- to access the system memory's HostAddress.\r
- @param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete.\r
-\r
- @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
- @retval EFI_INVALID_PARAMETER Operation is invalid.\r
- @retval EFI_INVALID_PARAMETER HostAddress is NULL.\r
- @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL.\r
- @retval EFI_INVALID_PARAMETER DeviceAddress is NULL.\r
- @retval EFI_INVALID_PARAMETER Mapping is NULL.\r
- @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r
- @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoMap (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,\r
- IN VOID *HostAddress,\r
- IN OUT UINTN *NumberOfBytes,\r
- OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
- OUT VOID **Mapping\r
- );\r
-\r
-/**\r
- Completes the Map() operation and releases any corresponding resources.\r
-\r
- The Unmap() function completes the Map() operation and releases any corresponding resources.\r
- If the operation was an EfiPciOperationBusMasterWrite or\r
- EfiPciOperationBusMasterWrite64, the data is committed to the target system memory.\r
- Any resources used for the mapping are freed.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Mapping The mapping value returned from Map().\r
-\r
- @retval EFI_SUCCESS The range was unmapped.\r
- @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r
- @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoUnmap (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN VOID *Mapping\r
- );\r
-\r
-/**\r
- Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or\r
- EfiPciOperationBusMasterCommonBuffer64 mapping.\r
-\r
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param Type This parameter is not used and must be ignored.\r
- @param MemoryType The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.\r
- @param Pages The number of pages to allocate.\r
- @param HostAddress A pointer to store the base system memory address of the allocated range.\r
- @param Attributes The requested bit mask of attributes for the allocated range. Only\r
- the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED,\r
- and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.\r
-\r
- @retval EFI_SUCCESS The requested memory pages were allocated.\r
- @retval EFI_INVALID_PARAMETER MemoryType is invalid.\r
- @retval EFI_INVALID_PARAMETER HostAddress is NULL.\r
- @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
- MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.\r
- @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoAllocateBuffer (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_ALLOCATE_TYPE Type,\r
- IN EFI_MEMORY_TYPE MemoryType,\r
- IN UINTN Pages,\r
- OUT VOID **HostAddress,\r
- IN UINT64 Attributes\r
- );\r
-\r
-/**\r
- Frees memory that was allocated with AllocateBuffer().\r
-\r
- The FreeBuffer() function frees memory that was allocated with AllocateBuffer().\r
-\r
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param Pages The number of pages to free.\r
- @param HostAddress The base system memory address of the allocated range.\r
-\r
- @retval EFI_SUCCESS The requested memory pages were freed.\r
- @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
- was not allocated with AllocateBuffer().\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoFreeBuffer (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN UINTN Pages,\r
- OUT VOID *HostAddress\r
- );\r
-\r
-/**\r
- Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
-\r
- The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system\r
- memory. Posted write transactions are generated by PCI bus masters when they perform write\r
- transactions to target addresses in system memory.\r
- This function does not flush posted write transactions from any PCI bridges. A PCI controller\r
- specific action must be taken to guarantee that the posted write transactions have been flushed from\r
- the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with\r
- a PCI read transaction from the PCI controller prior to calling Flush().\r
-\r
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r
- bridge to system memory.\r
- @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r
- host bridge due to a hardware error.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoFlush (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This\r
- );\r
-\r
-/**\r
- Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the\r
- attributes that a PCI root bridge is currently using.\r
-\r
- The GetAttributes() function returns the mask of attributes that this PCI root bridge supports\r
- and the mask of attributes that the PCI root bridge is currently using.\r
-\r
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param Supported A pointer to the mask of attributes that this PCI root bridge\r
- supports setting with SetAttributes().\r
- @param Attributes A pointer to the mask of attributes that this PCI root bridge is\r
- currently using.\r
-\r
- @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root\r
- bridge supports is returned in Supports. If Attributes is\r
- not NULL, then the attributes that the PCI root bridge is currently\r
- using is returned in Attributes.\r
- @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoGetAttributes (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- OUT UINT64 *Supported,\r
- OUT UINT64 *Attributes\r
- );\r
-\r
-/**\r
- Sets attributes for a resource range on a PCI root bridge.\r
-\r
- The SetAttributes() function sets the attributes specified in Attributes for the PCI root\r
- bridge on the resource range specified by ResourceBase and ResourceLength. Since the\r
- granularity of setting these attributes may vary from resource type to resource type, and from\r
- platform to platform, the actual resource range and the one passed in by the caller may differ. As a\r
- result, this function may set the attributes specified by Attributes on a larger resource range\r
- than the caller requested. The actual range is returned in ResourceBase and\r
- ResourceLength. The caller is responsible for verifying that the actual range for which the\r
- attributes were set is acceptable.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Attributes The mask of attributes to set. If the attribute bit\r
- MEMORY_WRITE_COMBINE, MEMORY_CACHED, or\r
- MEMORY_DISABLE is set, then the resource range is specified by\r
- ResourceBase and ResourceLength. If\r
- MEMORY_WRITE_COMBINE, MEMORY_CACHED, and\r
- MEMORY_DISABLE are not set, then ResourceBase and\r
- ResourceLength are ignored, and may be NULL.\r
- @param[in, out] ResourceBase A pointer to the base address of the resource range to be modified\r
- by the attributes specified by Attributes.\r
- @param[in, out] ResourceLength A pointer to the length of the resource range to be modified by the\r
- attributes specified by Attributes.\r
-\r
- @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.\r
- @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.\r
- @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoSetAttributes (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN UINT64 Attributes,\r
- IN OUT UINT64 *ResourceBase,\r
- IN OUT UINT64 *ResourceLength\r
- );\r
-\r
-/**\r
- Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0\r
- resource descriptors.\r
-\r
- There are only two resource descriptor types from the ACPI Specification that may be used to\r
- describe the current resources allocated to a PCI root bridge. These are the QWORD Address\r
- Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The\r
- QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic\r
- or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD\r
- Address Space Descriptors followed by an End Tag.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that describe the\r
- current configuration of this PCI root bridge. The storage for the\r
- ACPI 2.0 resource descriptors is allocated by this function. The\r
- caller must treat the return buffer as read-only data, and the buffer\r
- must not be freed by the caller.\r
-\r
- @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.\r
- @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.\r
- @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoConfiguration (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- OUT VOID **Resources\r
- );\r
-\r
-//\r
-// Memory Controller Pci Root Bridge Io Module Variables\r
-//\r
-EFI_METRONOME_ARCH_PROTOCOL *mMetronome;\r
-\r
-//\r
-// Lookup table for increment values based on transfer widths\r
-//\r
-UINT8 mInStride[] = {\r
- 1, // EfiPciWidthUint8\r
- 2, // EfiPciWidthUint16\r
- 4, // EfiPciWidthUint32\r
- 8, // EfiPciWidthUint64\r
- 0, // EfiPciWidthFifoUint8\r
- 0, // EfiPciWidthFifoUint16\r
- 0, // EfiPciWidthFifoUint32\r
- 0, // EfiPciWidthFifoUint64\r
- 1, // EfiPciWidthFillUint8\r
- 2, // EfiPciWidthFillUint16\r
- 4, // EfiPciWidthFillUint32\r
- 8 // EfiPciWidthFillUint64\r
-};\r
-\r
-//\r
-// Lookup table for increment values based on transfer widths\r
-//\r
-UINT8 mOutStride[] = {\r
- 1, // EfiPciWidthUint8\r
- 2, // EfiPciWidthUint16\r
- 4, // EfiPciWidthUint32\r
- 8, // EfiPciWidthUint64\r
- 1, // EfiPciWidthFifoUint8\r
- 2, // EfiPciWidthFifoUint16\r
- 4, // EfiPciWidthFifoUint32\r
- 8, // EfiPciWidthFifoUint64\r
- 0, // EfiPciWidthFillUint8\r
- 0, // EfiPciWidthFillUint16\r
- 0, // EfiPciWidthFillUint32\r
- 0 // EfiPciWidthFillUint64\r
-};\r
-\r
-/**\r
-\r
- Construct the Pci Root Bridge Io protocol\r
-\r
- @param Protocol Point to protocol instance\r
- @param HostBridgeHandle Handle of host bridge\r
- @param Attri Attribute of host bridge\r
- @param ResAperture ResourceAperture for host bridge\r
-\r
- @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.\r
-\r
-**/\r
-EFI_STATUS\r
-RootBridgeConstructor (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,\r
- IN EFI_HANDLE HostBridgeHandle,\r
- IN UINT64 Attri,\r
- IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture\r
- )\r
-{\r
- EFI_STATUS Status;\r
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
- PCI_RESOURCE_TYPE Index;\r
-\r
- PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (Protocol);\r
-\r
- //\r
- // The host to PCI bridge. The host memory addresses are direct mapped to PCI\r
- // addresses, so there's no need to translate them. IO addresses need\r
- // translation however.\r
- //\r
- PrivateData->MemBase = ResAperture->MemBase;\r
- PrivateData->IoBase = ResAperture->IoBase;\r
- PrivateData->IoTranslation = ResAperture->IoTranslation;\r
-\r
- //\r
- // The host bridge only supports 32bit addressing for memory\r
- // and standard IA32 16bit io\r
- //\r
- PrivateData->MemLimit = ResAperture->MemLimit;\r
- PrivateData->IoLimit = ResAperture->IoLimit;\r
-\r
- //\r
- // Bus Aperture for this Root Bridge (Possible Range)\r
- //\r
- PrivateData->BusBase = ResAperture->BusBase;\r
- PrivateData->BusLimit = ResAperture->BusLimit;\r
-\r
- //\r
- // Specific for this chipset\r
- //\r
- for (Index = TypeIo; Index < TypeMax; Index++) {\r
- PrivateData->ResAllocNode[Index].Type = Index;\r
- PrivateData->ResAllocNode[Index].Base = 0;\r
- PrivateData->ResAllocNode[Index].Length = 0;\r
- PrivateData->ResAllocNode[Index].Status = ResNone;\r
- }\r
-\r
- PrivateData->RootBridgeAttrib = Attri;\r
-\r
- PrivateData->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | \\r
- EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \\r
- EFI_PCI_ATTRIBUTE_VGA_MEMORY | \\r
- EFI_PCI_ATTRIBUTE_VGA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
- PrivateData->Attributes = PrivateData->Supports;\r
-\r
- Protocol->ParentHandle = HostBridgeHandle;\r
-\r
- Protocol->PollMem = RootBridgeIoPollMem;\r
- Protocol->PollIo = RootBridgeIoPollIo;\r
-\r
- Protocol->Mem.Read = RootBridgeIoMemRead;\r
- Protocol->Mem.Write = RootBridgeIoMemWrite;\r
-\r
- Protocol->Io.Read = RootBridgeIoIoRead;\r
- Protocol->Io.Write = RootBridgeIoIoWrite;\r
-\r
- Protocol->CopyMem = RootBridgeIoCopyMem;\r
-\r
- Protocol->Pci.Read = RootBridgeIoPciRead;\r
- Protocol->Pci.Write = RootBridgeIoPciWrite;\r
-\r
- Protocol->Map = RootBridgeIoMap;\r
- Protocol->Unmap = RootBridgeIoUnmap;\r
-\r
- Protocol->AllocateBuffer = RootBridgeIoAllocateBuffer;\r
- Protocol->FreeBuffer = RootBridgeIoFreeBuffer;\r
-\r
- Protocol->Flush = RootBridgeIoFlush;\r
-\r
- Protocol->GetAttributes = RootBridgeIoGetAttributes;\r
- Protocol->SetAttributes = RootBridgeIoSetAttributes;\r
-\r
- Protocol->Configuration = RootBridgeIoConfiguration;\r
-\r
- Protocol->SegmentNumber = 0;\r
-\r
- Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **)&mMetronome);\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.\r
-\r
- The I/O operations are carried out exactly as requested. The caller is responsible\r
- for satisfying any alignment and I/O width restrictions that a PI System on a\r
- platform might require. For example on some platforms, width requests of\r
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
- be handled by the driver.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] OperationType I/O operation type: IO/MMIO/PCI.\r
- @param[in] Width Signifies the width of the I/O or Memory operation.\r
- @param[in] Address The base address of the I/O operation.\r
- @param[in] Count The number of I/O operations to perform. The number of\r
- bytes moved is Width size * Count, starting at Address.\r
- @param[in] Buffer For read operations, the destination buffer to store the results.\r
- For write operations, the source buffer from which to write data.\r
-\r
- @retval EFI_SUCCESS The parameters for this request pass the checks.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
- and Count is not valid for this PI system.\r
-\r
-**/\r
-EFI_STATUS\r
-RootBridgeIoCheckParameter (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN OPERATION_TYPE OperationType,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- )\r
-{\r
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;\r
- UINT32 Stride;\r
- UINT64 Base;\r
- UINT64 Limit;\r
-\r
- //\r
- // Check to see if Buffer is NULL\r
- //\r
- if (Buffer == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // Check to see if Width is in the valid range\r
- //\r
- if ((UINT32)Width >= EfiPciWidthMaximum) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // For FIFO type, the target address won't increase during the access,\r
- // so treat Count as 1\r
- //\r
- if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {\r
- Count = 1;\r
- }\r
-\r
- //\r
- // Check to see if Width is in the valid range for I/O Port operations\r
- //\r
- Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
- if ((OperationType != MemOperation) && (Width == EfiPciWidthUint64)) {\r
- ASSERT (FALSE);\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // Check to see if Address is aligned\r
- //\r
- Stride = mInStride[Width];\r
- if ((Address & (UINT64)(Stride - 1)) != 0) {\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
-\r
- //\r
- // Check to see if any address associated with this transfer exceeds the maximum\r
- // allowed address. The maximum address implied by the parameters passed in is\r
- // Address + Size * Count. If the following condition is met, then the transfer\r
- // is not supported.\r
- //\r
- // Address + Size * Count > Limit + 1\r
- //\r
- // Since Limit can be the maximum integer value supported by the CPU and Count\r
- // can also be the maximum integer value supported by the CPU, this range\r
- // check must be adjusted to avoid all oveflow conditions.\r
- //\r
- if (OperationType == IoOperation) {\r
- Base = PrivateData->IoBase;\r
- Limit = PrivateData->IoLimit;\r
- } else if (OperationType == MemOperation) {\r
- Base = PrivateData->MemBase;\r
- Limit = PrivateData->MemLimit;\r
- } else {\r
- PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;\r
- if (PciRbAddr->Bus < PrivateData->BusBase || PciRbAddr->Bus > PrivateData->BusLimit) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- if (PciRbAddr->Device > MAX_PCI_DEVICE_NUMBER || PciRbAddr->Function > MAX_PCI_FUNCTION_NUMBER) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- if (PciRbAddr->ExtendedRegister != 0) {\r
- Address = PciRbAddr->ExtendedRegister;\r
- } else {\r
- Address = PciRbAddr->Register;\r
- }\r
- Base = 0;\r
- Limit = MAX_PCI_REG_ADDRESS;\r
- }\r
-\r
- if (Limit < Address) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- if (Address < Base) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // Base <= Address <= Limit\r
- //\r
- if (Address == 0 && Limit == MAX_UINT64) {\r
- //\r
- // 2^64 bytes are valid to transfer. With Stride == 1, that's simply\r
- // impossible to reach in Count; with Stride in {2, 4, 8}, we can divide\r
- // both 2^64 and Stride with 2.\r
- //\r
- if (Stride > 1 && Count > DivU64x32 (BIT63, Stride / 2)) {\r
- return EFI_UNSUPPORTED;\r
- }\r
- } else {\r
- //\r
- // (Limit - Address) does not wrap, and it is smaller than MAX_UINT64.\r
- //\r
- if (Count > DivU64x32 (Limit - Address + 1, Stride)) {\r
- return EFI_UNSUPPORTED;\r
- }\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Internal help function for read and write memory space.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Write Switch value for Read or Write.\r
- @param[in] Width Signifies the width of the memory operations.\r
- @param[in] UserAddress The address within the PCI configuration space for the PCI controller.\r
- @param[in] Count The number of PCI configuration operations to perform. Bytes\r
- moved is Width size * Count, starting at Address.\r
- @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-RootBridgeIoMemRW (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN BOOLEAN Write,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINT8 InStride;\r
- UINT8 OutStride;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;\r
- UINT8 *Uint8Buffer;\r
-\r
- Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address, Count, Buffer);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
- for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
- if (Write) {\r
- switch (OperationWidth) {\r
- case EfiPciWidthUint8:\r
- MmioWrite8 ((UINTN)Address, *Uint8Buffer);\r
- break;\r
- case EfiPciWidthUint16:\r
- MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));\r
- break;\r
- case EfiPciWidthUint32:\r
- MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));\r
- break;\r
- case EfiPciWidthUint64:\r
- MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));\r
- break;\r
- default:\r
- //\r
- // The RootBridgeIoCheckParameter call above will ensure that this\r
- // path is not taken.\r
- //\r
- ASSERT (FALSE);\r
- break;\r
- }\r
- } else {\r
- switch (OperationWidth) {\r
- case EfiPciWidthUint8:\r
- *Uint8Buffer = MmioRead8 ((UINTN)Address);\r
- break;\r
- case EfiPciWidthUint16:\r
- *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);\r
- break;\r
- case EfiPciWidthUint32:\r
- *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);\r
- break;\r
- case EfiPciWidthUint64:\r
- *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);\r
- break;\r
- default:\r
- //\r
- // The RootBridgeIoCheckParameter call above will ensure that this\r
- // path is not taken.\r
- //\r
- ASSERT (FALSE);\r
- break;\r
- }\r
- }\r
- }\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Internal help function for read and write IO space.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Write Switch value for Read or Write.\r
- @param[in] Width Signifies the width of the memory operations.\r
- @param[in] UserAddress The address within the PCI configuration space for the PCI controller.\r
- @param[in] Count The number of PCI configuration operations to perform. Bytes\r
- moved is Width size * Count, starting at Address.\r
- @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-RootBridgeIoIoRW (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN BOOLEAN Write,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- )\r
-{\r
- EFI_STATUS Status;\r
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
- UINT8 InStride;\r
- UINT8 OutStride;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;\r
- UINT8 *Uint8Buffer;\r
-\r
- Status = RootBridgeIoCheckParameter (This, IoOperation, Width, Address, Count, Buffer);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
- //\r
- // The addition below is performed in UINT64 modular arithmetic, in\r
- // accordance with the definition of PcdPciIoTranslation in\r
- // "ArmPlatformPkg.dec". Meaning, the addition below may in fact *decrease*\r
- // Address, implementing a negative offset translation.\r
- //\r
- Address += PrivateData->IoTranslation;\r
-\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
-\r
- for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
- if (Write) {\r
- switch (OperationWidth) {\r
- case EfiPciWidthUint8:\r
- MmioWrite8 ((UINTN)Address, *Uint8Buffer);\r
- break;\r
- case EfiPciWidthUint16:\r
- MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));\r
- break;\r
- case EfiPciWidthUint32:\r
- MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));\r
- break;\r
- default:\r
- //\r
- // The RootBridgeIoCheckParameter call above will ensure that this\r
- // path is not taken.\r
- //\r
- ASSERT (FALSE);\r
- break;\r
- }\r
- } else {\r
- switch (OperationWidth) {\r
- case EfiPciWidthUint8:\r
- *Uint8Buffer = MmioRead8 ((UINTN)Address);\r
- break;\r
- case EfiPciWidthUint16:\r
- *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);\r
- break;\r
- case EfiPciWidthUint32:\r
- *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);\r
- break;\r
- default:\r
- //\r
- // The RootBridgeIoCheckParameter call above will ensure that this\r
- // path is not taken.\r
- //\r
- ASSERT (FALSE);\r
- break;\r
- }\r
- }\r
- }\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Internal help function for read and write PCI configuration space.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Write Switch value for Read or Write.\r
- @param[in] Width Signifies the width of the memory operations.\r
- @param[in] UserAddress The address within the PCI configuration space for the PCI controller.\r
- @param[in] Count The number of PCI configuration operations to perform. Bytes\r
- moved is Width size * Count, starting at Address.\r
- @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-RootBridgeIoPciRW (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN BOOLEAN Write,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINT8 InStride;\r
- UINT8 OutStride;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;\r
- UINT8 *Uint8Buffer;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;\r
- UINTN PcieRegAddr;\r
-\r
- Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address, Count, Buffer);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;\r
-\r
- PcieRegAddr = (UINTN) PCI_LIB_ADDRESS (\r
- PciRbAddr->Bus,\r
- PciRbAddr->Device,\r
- PciRbAddr->Function,\r
- (PciRbAddr->ExtendedRegister != 0) ? \\r
- PciRbAddr->ExtendedRegister :\r
- PciRbAddr->Register\r
- );\r
-\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
- for (Uint8Buffer = Buffer; Count > 0; PcieRegAddr += InStride, Uint8Buffer += OutStride, Count--) {\r
- if (Write) {\r
- switch (OperationWidth) {\r
- case EfiPciWidthUint8:\r
- PciWrite8 (PcieRegAddr, *Uint8Buffer);\r
- break;\r
- case EfiPciWidthUint16:\r
- PciWrite16 (PcieRegAddr, *((UINT16 *)Uint8Buffer));\r
- break;\r
- case EfiPciWidthUint32:\r
- PciWrite32 (PcieRegAddr, *((UINT32 *)Uint8Buffer));\r
- break;\r
- default:\r
- //\r
- // The RootBridgeIoCheckParameter call above will ensure that this\r
- // path is not taken.\r
- //\r
- ASSERT (FALSE);\r
- break;\r
- }\r
- } else {\r
- switch (OperationWidth) {\r
- case EfiPciWidthUint8:\r
- *Uint8Buffer = PciRead8 (PcieRegAddr);\r
- break;\r
- case EfiPciWidthUint16:\r
- *((UINT16 *)Uint8Buffer) = PciRead16 (PcieRegAddr);\r
- break;\r
- case EfiPciWidthUint32:\r
- *((UINT32 *)Uint8Buffer) = PciRead32 (PcieRegAddr);\r
- break;\r
- default:\r
- //\r
- // The RootBridgeIoCheckParameter call above will ensure that this\r
- // path is not taken.\r
- //\r
- ASSERT (FALSE);\r
- break;\r
- }\r
- }\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Polls an address in memory mapped I/O space until an exit condition is met, or\r
- a timeout occurs.\r
-\r
- This function provides a standard way to poll a PCI memory location. A PCI memory read\r
- operation is performed at the PCI memory address specified by Address for the width specified\r
- by Width. The result of this PCI memory read operation is stored in Result. This PCI memory\r
- read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result &\r
- Mask) is equal to Value.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Width Signifies the width of the memory operations.\r
- @param[in] Address The base address of the memory operations. The caller is\r
- responsible for aligning Address if required.\r
- @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask\r
- are ignored. The bits in the bytes below Width which are zero in\r
- Mask are ignored when polling the memory address.\r
- @param[in] Value The comparison value used for the polling exit criteria.\r
- @param[in] Delay The number of 100 ns units to poll. Note that timer available may\r
- be of poorer granularity.\r
- @param[out] Result Pointer to the last value read from the memory location.\r
-\r
- @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
- @retval EFI_INVALID_PARAMETER Width is invalid.\r
- @retval EFI_INVALID_PARAMETER Result is NULL.\r
- @retval EFI_TIMEOUT Delay expired before a match occurred.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoPollMem (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINT64 Mask,\r
- IN UINT64 Value,\r
- IN UINT64 Delay,\r
- OUT UINT64 *Result\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINT64 NumberOfTicks;\r
- UINT32 Remainder;\r
-\r
- if (Result == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- if ((UINT32)Width > EfiPciWidthUint64) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // No matter what, always do a single poll.\r
- //\r
- Status = This->Mem.Read (This, Width, Address, 1, Result);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- if ((*Result & Mask) == Value) {\r
- return EFI_SUCCESS;\r
- }\r
-\r
- if (Delay == 0) {\r
- return EFI_SUCCESS;\r
-\r
- } else {\r
-\r
- //\r
- // Determine the proper # of metronome ticks to wait for polling the\r
- // location. The nuber of ticks is Roundup (Delay / mMetronome->TickPeriod)+1\r
- // The "+1" to account for the possibility of the first tick being short\r
- // because we started in the middle of a tick.\r
- //\r
- // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome\r
- // protocol definition is updated.\r
- //\r
- NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod, &Remainder);\r
- if (Remainder != 0) {\r
- NumberOfTicks += 1;\r
- }\r
- NumberOfTicks += 1;\r
-\r
- while (NumberOfTicks != 0) {\r
-\r
- mMetronome->WaitForTick (mMetronome, 1);\r
-\r
- Status = This->Mem.Read (This, Width, Address, 1, Result);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- if ((*Result & Mask) == Value) {\r
- return EFI_SUCCESS;\r
- }\r
-\r
- NumberOfTicks -= 1;\r
- }\r
- }\r
- return EFI_TIMEOUT;\r
-}\r
-\r
-/**\r
- Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r
- satisfied or after a defined duration.\r
-\r
- This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is\r
- performed at the PCI I/O address specified by Address for the width specified by Width.\r
- The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is\r
- repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal\r
- to Value.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Width Signifies the width of the I/O operations.\r
- @param[in] Address The base address of the I/O operations. The caller is responsible\r
- for aligning Address if required.\r
- @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask\r
- are ignored. The bits in the bytes below Width which are zero in\r
- Mask are ignored when polling the I/O address.\r
- @param[in] Value The comparison value used for the polling exit criteria.\r
- @param[in] Delay The number of 100 ns units to poll. Note that timer available may\r
- be of poorer granularity.\r
- @param[out] Result Pointer to the last value read from the memory location.\r
-\r
- @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
- @retval EFI_INVALID_PARAMETER Width is invalid.\r
- @retval EFI_INVALID_PARAMETER Result is NULL.\r
- @retval EFI_TIMEOUT Delay expired before a match occurred.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoPollIo (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINT64 Mask,\r
- IN UINT64 Value,\r
- IN UINT64 Delay,\r
- OUT UINT64 *Result\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINT64 NumberOfTicks;\r
- UINT32 Remainder;\r
-\r
- //\r
- // No matter what, always do a single poll.\r
- //\r
-\r
- if (Result == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- if ((UINT32)Width > EfiPciWidthUint64) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- Status = This->Io.Read (This, Width, Address, 1, Result);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- if ((*Result & Mask) == Value) {\r
- return EFI_SUCCESS;\r
- }\r
-\r
- if (Delay == 0) {\r
- return EFI_SUCCESS;\r
-\r
- } else {\r
-\r
- //\r
- // Determine the proper # of metronome ticks to wait for polling the\r
- // location. The number of ticks is Roundup (Delay / mMetronome->TickPeriod)+1\r
- // The "+1" to account for the possibility of the first tick being short\r
- // because we started in the middle of a tick.\r
- //\r
- NumberOfTicks = DivU64x32Remainder (Delay, (UINT32)mMetronome->TickPeriod, &Remainder);\r
- if (Remainder != 0) {\r
- NumberOfTicks += 1;\r
- }\r
- NumberOfTicks += 1;\r
-\r
- while (NumberOfTicks != 0) {\r
-\r
- mMetronome->WaitForTick (mMetronome, 1);\r
-\r
- Status = This->Io.Read (This, Width, Address, 1, Result);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- if ((*Result & Mask) == Value) {\r
- return EFI_SUCCESS;\r
- }\r
-\r
- NumberOfTicks -= 1;\r
- }\r
- }\r
- return EFI_TIMEOUT;\r
-}\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
-\r
- The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller\r
- registers in the PCI root bridge memory space.\r
- The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
- any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Width Signifies the width of the memory operation.\r
- @param[in] Address The base address of the memory operation. The caller is\r
- responsible for aligning the Address if required.\r
- @param[in] Count The number of memory operations to perform. Bytes moved is\r
- Width size * Count, starting at Address.\r
- @param[out] Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoMemRead (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- return RootBridgeIoMemRW (This, FALSE, Width, Address, Count, Buffer);\r
-}\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
-\r
- The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller\r
- registers in the PCI root bridge memory space.\r
- The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
- any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Width Signifies the width of the memory operation.\r
- @param[in] Address The base address of the memory operation. The caller is\r
- responsible for aligning the Address if required.\r
- @param[in] Count The number of memory operations to perform. Bytes moved is\r
- Width size * Count, starting at Address.\r
- @param[in] Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoMemWrite (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- )\r
-{\r
- return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer);\r
-}\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Width Signifies the width of the memory operations.\r
- @param[in] Address The base address of the I/O operation. The caller is responsible for\r
- aligning the Address if required.\r
- @param[in] Count The number of I/O operations to perform. Bytes moved is Width\r
- size * Count, starting at Address.\r
- @param[out] Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoIoRead (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer);\r
-}\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Width Signifies the width of the memory operations.\r
- @param[in] Address The base address of the I/O operation. The caller is responsible for\r
- aligning the Address if required.\r
- @param[in] Count The number of I/O operations to perform. Bytes moved is Width\r
- size * Count, starting at Address.\r
- @param[in] Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoIoWrite (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- )\r
-{\r
- return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer);\r
-}\r
-\r
-/**\r
- Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI\r
- root bridge memory space.\r
-\r
- The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory\r
- space to another region of PCI root bridge memory space. This is especially useful for video scroll\r
- operation on a memory mapped video buffer.\r
- The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
- any alignment and memory width restrictions that a PCI root bridge on a platform might require.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
- @param[in] Width Signifies the width of the memory operations.\r
- @param[in] DestAddress The destination address of the memory operation. The caller is\r
- responsible for aligning the DestAddress if required.\r
- @param[in] SrcAddress The source address of the memory operation. The caller is\r
- responsible for aligning the SrcAddress if required.\r
- @param[in] Count The number of memory operations to perform. Bytes moved is\r
- Width size * Count, starting at DestAddress and SrcAddress.\r
-\r
- @retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoCopyMem (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 DestAddress,\r
- IN UINT64 SrcAddress,\r
- IN UINTN Count\r
- )\r
-{\r
- EFI_STATUS Status;\r
- BOOLEAN Direction;\r
- UINTN Stride;\r
- UINTN Index;\r
- UINT64 Result;\r
-\r
- if ((UINT32)Width > EfiPciWidthUint64) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- if (DestAddress == SrcAddress) {\r
- return EFI_SUCCESS;\r
- }\r
-\r
- Stride = (UINTN)(1 << Width);\r
-\r
- Direction = TRUE;\r
- if ((DestAddress > SrcAddress) && (DestAddress < (SrcAddress + Count * Stride))) {\r
- Direction = FALSE;\r
- SrcAddress = SrcAddress + (Count-1) * Stride;\r
- DestAddress = DestAddress + (Count-1) * Stride;\r
- }\r
-\r
- for (Index = 0;Index < Count;Index++) {\r
- Status = RootBridgeIoMemRead (\r
- This,\r
- Width,\r
- SrcAddress,\r
- 1,\r
- &Result\r
- );\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- Status = RootBridgeIoMemWrite (\r
- This,\r
- Width,\r
- DestAddress,\r
- 1,\r
- &Result\r
- );\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- if (Direction) {\r
- SrcAddress += Stride;\r
- DestAddress += Stride;\r
- } else {\r
- SrcAddress -= Stride;\r
- DestAddress -= Stride;\r
- }\r
- }\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.\r
-\r
- The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration\r
- registers for a PCI controller.\r
- The PCI Configuration operations are carried out exactly as requested. The caller is responsible for\r
- any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might\r
- require.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Width Signifies the width of the memory operations.\r
- @param[in] Address The address within the PCI configuration space for the PCI controller.\r
- @param[in] Count The number of PCI configuration operations to perform. Bytes\r
- moved is Width size * Count, starting at Address.\r
- @param[out] Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoPciRead (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- return RootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);\r
-}\r
-\r
-/**\r
- Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.\r
-\r
- The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration\r
- registers for a PCI controller.\r
- The PCI Configuration operations are carried out exactly as requested. The caller is responsible for\r
- any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might\r
- require.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Width Signifies the width of the memory operations.\r
- @param[in] Address The address within the PCI configuration space for the PCI controller.\r
- @param[in] Count The number of PCI configuration operations to perform. Bytes\r
- moved is Width size * Count, starting at Address.\r
- @param[in] Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoPciWrite (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- )\r
-{\r
- return RootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);\r
-}\r
-\r
-/**\r
- Provides the PCI controller-specific addresses required to access system memory from a\r
- DMA bus master.\r
-\r
- The Map() function provides the PCI controller specific addresses needed to access system\r
- memory. This function is used to map system memory for PCI bus master DMA accesses.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Operation Indicates if the bus master is going to read or write to system memory.\r
- @param[in] HostAddress The system memory address to map to the PCI controller.\r
- @param[in, out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.\r
- @param[out] DeviceAddress The resulting map address for the bus master PCI controller to use\r
- to access the system memory's HostAddress.\r
- @param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete.\r
-\r
- @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
- @retval EFI_INVALID_PARAMETER Operation is invalid.\r
- @retval EFI_INVALID_PARAMETER HostAddress is NULL.\r
- @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL.\r
- @retval EFI_INVALID_PARAMETER DeviceAddress is NULL.\r
- @retval EFI_INVALID_PARAMETER Mapping is NULL.\r
- @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r
- @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoMap (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,\r
- IN VOID *HostAddress,\r
- IN OUT UINTN *NumberOfBytes,\r
- OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
- OUT VOID **Mapping\r
- )\r
-{\r
- EFI_STATUS Status;\r
- EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
- MAP_INFO *MapInfo;\r
-\r
- if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // Initialize the return values to their defaults\r
- //\r
- *Mapping = NULL;\r
-\r
- //\r
- // Make sure that Operation is valid\r
- //\r
- if ((UINT32)Operation >= EfiPciOperationMaximum) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // Most PCAT like chipsets can not handle performing DMA above 4GB.\r
- // If any part of the DMA transfer being mapped is above 4GB, then\r
- // map the DMA transfer to a buffer below 4GB.\r
- //\r
- PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress;\r
- if ((PhysicalAddress + *NumberOfBytes) > 0x100000000ULL) {\r
-\r
- //\r
- // Common Buffer operations can not be remapped. If the common buffer\r
- // if above 4GB, then it is not possible to generate a mapping, so return\r
- // an error.\r
- //\r
- if (Operation == EfiPciOperationBusMasterCommonBuffer || Operation == EfiPciOperationBusMasterCommonBuffer64) {\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- //\r
- // Allocate a MAP_INFO structure to remember the mapping when Unmap() is\r
- // called later.\r
- //\r
- Status = gBS->AllocatePool (\r
- EfiBootServicesData,\r
- sizeof(MAP_INFO),\r
- (VOID **)&MapInfo\r
- );\r
- if (EFI_ERROR (Status)) {\r
- *NumberOfBytes = 0;\r
- return Status;\r
- }\r
-\r
- //\r
- // Return a pointer to the MAP_INFO structure in Mapping\r
- //\r
- *Mapping = MapInfo;\r
-\r
- //\r
- // Initialize the MAP_INFO structure\r
- //\r
- MapInfo->Operation = Operation;\r
- MapInfo->NumberOfBytes = *NumberOfBytes;\r
- MapInfo->NumberOfPages = EFI_SIZE_TO_PAGES(*NumberOfBytes);\r
- MapInfo->HostAddress = PhysicalAddress;\r
- MapInfo->MappedHostAddress = 0x00000000ffffffff;\r
-\r
- //\r
- // Allocate a buffer below 4GB to map the transfer to.\r
- //\r
- Status = gBS->AllocatePages (\r
- AllocateMaxAddress,\r
- EfiBootServicesData,\r
- MapInfo->NumberOfPages,\r
- &MapInfo->MappedHostAddress\r
- );\r
- if (EFI_ERROR (Status)) {\r
- gBS->FreePool (MapInfo);\r
- *NumberOfBytes = 0;\r
- return Status;\r
- }\r
-\r
- //\r
- // If this is a read operation from the Bus Master's point of view,\r
- // then copy the contents of the real buffer into the mapped buffer\r
- // so the Bus Master can read the contents of the real buffer.\r
- //\r
- if (Operation == EfiPciOperationBusMasterRead || Operation == EfiPciOperationBusMasterRead64) {\r
- CopyMem (\r
- (VOID *)(UINTN)MapInfo->MappedHostAddress,\r
- (VOID *)(UINTN)MapInfo->HostAddress,\r
- MapInfo->NumberOfBytes\r
- );\r
- }\r
-\r
- //\r
- // The DeviceAddress is the address of the maped buffer below 4GB\r
- //\r
- *DeviceAddress = MapInfo->MappedHostAddress;\r
- } else {\r
- //\r
- // The transfer is below 4GB, so the DeviceAddress is simply the HostAddress\r
- //\r
- *DeviceAddress = PhysicalAddress;\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Completes the Map() operation and releases any corresponding resources.\r
-\r
- The Unmap() function completes the Map() operation and releases any corresponding resources.\r
- If the operation was an EfiPciOperationBusMasterWrite or\r
- EfiPciOperationBusMasterWrite64, the data is committed to the target system memory.\r
- Any resources used for the mapping are freed.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Mapping The mapping value returned from Map().\r
-\r
- @retval EFI_SUCCESS The range was unmapped.\r
- @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r
- @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoUnmap (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN VOID *Mapping\r
- )\r
-{\r
- MAP_INFO *MapInfo;\r
-\r
- //\r
- // See if the Map() operation associated with this Unmap() required a mapping buffer.\r
- // If a mapping buffer was not required, then this function simply returns EFI_SUCCESS.\r
- //\r
- if (Mapping != NULL) {\r
- //\r
- // Get the MAP_INFO structure from Mapping\r
- //\r
- MapInfo = (MAP_INFO *)Mapping;\r
-\r
- //\r
- // If this is a write operation from the Bus Master's point of view,\r
- // then copy the contents of the mapped buffer into the real buffer\r
- // so the processor can read the contents of the real buffer.\r
- //\r
- if (MapInfo->Operation == EfiPciOperationBusMasterWrite || MapInfo->Operation == EfiPciOperationBusMasterWrite64) {\r
- CopyMem (\r
- (VOID *)(UINTN)MapInfo->HostAddress,\r
- (VOID *)(UINTN)MapInfo->MappedHostAddress,\r
- MapInfo->NumberOfBytes\r
- );\r
- }\r
-\r
- //\r
- // Free the mapped buffer and the MAP_INFO structure.\r
- //\r
- gBS->FreePages (MapInfo->MappedHostAddress, MapInfo->NumberOfPages);\r
- gBS->FreePool (Mapping);\r
- }\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or\r
- EfiPciOperationBusMasterCommonBuffer64 mapping.\r
-\r
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param Type This parameter is not used and must be ignored.\r
- @param MemoryType The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.\r
- @param Pages The number of pages to allocate.\r
- @param HostAddress A pointer to store the base system memory address of the allocated range.\r
- @param Attributes The requested bit mask of attributes for the allocated range. Only\r
- the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED,\r
- and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.\r
-\r
- @retval EFI_SUCCESS The requested memory pages were allocated.\r
- @retval EFI_INVALID_PARAMETER MemoryType is invalid.\r
- @retval EFI_INVALID_PARAMETER HostAddress is NULL.\r
- @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
- MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.\r
- @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoAllocateBuffer (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_ALLOCATE_TYPE Type,\r
- IN EFI_MEMORY_TYPE MemoryType,\r
- IN UINTN Pages,\r
- OUT VOID **HostAddress,\r
- IN UINT64 Attributes\r
- )\r
-{\r
- EFI_STATUS Status;\r
- EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
-\r
- //\r
- // Validate Attributes\r
- //\r
- if ((Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) != 0) {\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- //\r
- // Check for invalid inputs\r
- //\r
- if (HostAddress == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData\r
- //\r
- if (MemoryType != EfiBootServicesData && MemoryType != EfiRuntimeServicesData) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // Limit allocations to memory below 4GB\r
- //\r
- PhysicalAddress = (EFI_PHYSICAL_ADDRESS)(0xffffffff);\r
-\r
- Status = gBS->AllocatePages (AllocateMaxAddress, MemoryType, Pages, &PhysicalAddress);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- *HostAddress = (VOID *)(UINTN)PhysicalAddress;\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Frees memory that was allocated with AllocateBuffer().\r
-\r
- The FreeBuffer() function frees memory that was allocated with AllocateBuffer().\r
-\r
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param Pages The number of pages to free.\r
- @param HostAddress The base system memory address of the allocated range.\r
-\r
- @retval EFI_SUCCESS The requested memory pages were freed.\r
- @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
- was not allocated with AllocateBuffer().\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoFreeBuffer (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN UINTN Pages,\r
- OUT VOID *HostAddress\r
- )\r
-{\r
- return gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress, Pages);\r
-}\r
-\r
-/**\r
- Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
-\r
- The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system\r
- memory. Posted write transactions are generated by PCI bus masters when they perform write\r
- transactions to target addresses in system memory.\r
- This function does not flush posted write transactions from any PCI bridges. A PCI controller\r
- specific action must be taken to guarantee that the posted write transactions have been flushed from\r
- the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with\r
- a PCI read transaction from the PCI controller prior to calling Flush().\r
-\r
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r
- bridge to system memory.\r
- @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r
- host bridge due to a hardware error.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoFlush (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This\r
- )\r
-{\r
- //\r
- // not supported yet\r
- //\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the\r
- attributes that a PCI root bridge is currently using.\r
-\r
- The GetAttributes() function returns the mask of attributes that this PCI root bridge supports\r
- and the mask of attributes that the PCI root bridge is currently using.\r
-\r
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param Supported A pointer to the mask of attributes that this PCI root bridge\r
- supports setting with SetAttributes().\r
- @param Attributes A pointer to the mask of attributes that this PCI root bridge is\r
- currently using.\r
-\r
- @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root\r
- bridge supports is returned in Supports. If Attributes is\r
- not NULL, then the attributes that the PCI root bridge is currently\r
- using is returned in Attributes.\r
- @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoGetAttributes (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- OUT UINT64 *Supported,\r
- OUT UINT64 *Attributes\r
- )\r
-{\r
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
-\r
- PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);\r
-\r
- if (Attributes == NULL && Supported == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // Set the return value for Supported and Attributes\r
- //\r
- if (Supported != NULL) {\r
- *Supported = PrivateData->Supports;\r
- }\r
-\r
- if (Attributes != NULL) {\r
- *Attributes = PrivateData->Attributes;\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Sets attributes for a resource range on a PCI root bridge.\r
-\r
- The SetAttributes() function sets the attributes specified in Attributes for the PCI root\r
- bridge on the resource range specified by ResourceBase and ResourceLength. Since the\r
- granularity of setting these attributes may vary from resource type to resource type, and from\r
- platform to platform, the actual resource range and the one passed in by the caller may differ. As a\r
- result, this function may set the attributes specified by Attributes on a larger resource range\r
- than the caller requested. The actual range is returned in ResourceBase and\r
- ResourceLength. The caller is responsible for verifying that the actual range for which the\r
- attributes were set is acceptable.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[in] Attributes The mask of attributes to set. If the attribute bit\r
- MEMORY_WRITE_COMBINE, MEMORY_CACHED, or\r
- MEMORY_DISABLE is set, then the resource range is specified by\r
- ResourceBase and ResourceLength. If\r
- MEMORY_WRITE_COMBINE, MEMORY_CACHED, and\r
- MEMORY_DISABLE are not set, then ResourceBase and\r
- ResourceLength are ignored, and may be NULL.\r
- @param[in, out] ResourceBase A pointer to the base address of the resource range to be modified\r
- by the attributes specified by Attributes.\r
- @param[in, out] ResourceLength A pointer to the length of the resource range to be modified by the\r
- attributes specified by Attributes.\r
-\r
- @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.\r
- @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.\r
- @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoSetAttributes (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN UINT64 Attributes,\r
- IN OUT UINT64 *ResourceBase,\r
- IN OUT UINT64 *ResourceLength\r
- )\r
-{\r
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
-\r
- PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);\r
-\r
- if (Attributes != 0) {\r
- if ((Attributes & (~(PrivateData->Supports))) != 0) {\r
- return EFI_UNSUPPORTED;\r
- }\r
- }\r
-\r
- //\r
- // This is a generic driver for a PC-AT class system. It does not have any\r
- // chipset specific knowlegde, so none of the attributes can be set or\r
- // cleared. Any attempt to set attribute that are already set will succeed,\r
- // and any attempt to set an attribute that is not supported will fail.\r
- //\r
- if (Attributes & (~PrivateData->Attributes)) {\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0\r
- resource descriptors.\r
-\r
- There are only two resource descriptor types from the ACPI Specification that may be used to\r
- describe the current resources allocated to a PCI root bridge. These are the QWORD Address\r
- Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The\r
- QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic\r
- or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD\r
- Address Space Descriptors followed by an End Tag.\r
-\r
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that describe the\r
- current configuration of this PCI root bridge. The storage for the\r
- ACPI 2.0 resource descriptors is allocated by this function. The\r
- caller must treat the return buffer as read-only data, and the buffer\r
- must not be freed by the caller.\r
-\r
- @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.\r
- @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.\r
- @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RootBridgeIoConfiguration (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- OUT VOID **Resources\r
- )\r
-{\r
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
- UINTN Index;\r
-\r
- PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
-\r
- for (Index = 0; Index < TypeMax; Index++) {\r
- if (PrivateData->ResAllocNode[Index].Status == ResAllocated) {\r
- Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base;\r
- Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1;\r
- Configuration.SpaceDesp[Index].AddrLen = PrivateData->ResAllocNode[Index].Length;\r
- }\r
- }\r
-\r
- *Resources = &Configuration;\r
- return EFI_SUCCESS;\r
-}\r
-\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include "PrePi.h"\r
-\r
-#include <Chipset/AArch64.h>\r
-\r
-VOID\r
-ArchInitialize (\r
- VOID\r
- )\r
-{\r
- // Enable Floating Point\r
- if (FixedPcdGet32 (PcdVFPEnabled)) {\r
- ArmEnableVFP ();\r
- }\r
-\r
- if (ArmReadCurrentEL () == AARCH64_EL2) {\r
- // Trap General Exceptions. All exceptions that would be routed to EL1 are routed to EL2\r
- ArmWriteHcr (ARM_HCR_TGE);\r
- }\r
-}\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-// Copyright (c) 2015, Linaro Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AsmMacroIoLibV8.h>\r
-#include <Base.h>\r
-#include <Library/PcdLib.h>\r
-#include <AutoGen.h>\r
-\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)\r
-GCC_ASM_IMPORT(ArmReadMpidr)\r
-GCC_ASM_IMPORT(ArmPlatformPeiBootAction)\r
-GCC_ASM_IMPORT(ArmPlatformStackSet)\r
-GCC_ASM_EXPORT(_ModuleEntryPoint)\r
-\r
-StartupAddr: .8byte ASM_PFX(CEntryPoint)\r
-\r
-ASM_PFX(_ModuleEntryPoint):\r
- //\r
- // We are built as a ET_DYN PIE executable, so we need to process all\r
- // relative relocations regardless of whether or not we are executing from\r
- // the same offset we were linked at. This is only possible if we are\r
- // running from RAM.\r
- //\r
- adr x8, __reloc_base\r
- adr x9, __reloc_start\r
- adr x10, __reloc_end\r
-\r
-.Lreloc_loop:\r
- cmp x9, x10\r
- bhs .Lreloc_done\r
-\r
- //\r
- // AArch64 uses the ELF64 RELA format, which means each entry in the\r
- // relocation table consists of\r
- //\r
- // UINT64 offset : the relative offset of the value that needs to\r
- // be relocated\r
- // UINT64 info : relocation type and symbol index (the latter is\r
- // not used for R_AARCH64_RELATIVE relocations)\r
- // UINT64 addend : value to be added to the value being relocated\r
- //\r
- ldp x11, x12, [x9], #24 // read offset into x11 and info into x12\r
- cmp x12, #0x403 // check info == R_AARCH64_RELATIVE?\r
- bne .Lreloc_loop // not a relative relocation? then skip\r
-\r
- ldr x12, [x9, #-8] // read addend into x12\r
- add x12, x12, x8 // add reloc base to addend to get relocated value\r
- str x12, [x11, x8] // write relocated value at offset\r
- b .Lreloc_loop\r
-.Lreloc_done:\r
-\r
- // Do early platform specific actions\r
- bl ASM_PFX(ArmPlatformPeiBootAction)\r
-\r
- // Get ID of this CPU in Multicore system\r
- bl ASM_PFX(ArmReadMpidr)\r
- // Keep a copy of the MpId register value\r
- mov x10, x0\r
-\r
-// Check if we can install the stack at the top of the System Memory or if we need\r
-// to install the stacks at the bottom of the Firmware Device (case the FD is located\r
-// at the top of the DRAM)\r
-_SetupStackPosition:\r
- // Compute Top of System Memory\r
- ldr x1, PcdGet64 (PcdSystemMemoryBase)\r
- ldr x2, PcdGet64 (PcdSystemMemorySize)\r
- sub x2, x2, #1\r
- add x1, x1, x2 // x1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize\r
-\r
- // Calculate Top of the Firmware Device\r
- ldr x2, PcdGet64 (PcdFdBaseAddress)\r
- ldr w3, PcdGet32 (PcdFdSize)\r
- sub x3, x3, #1\r
- add x3, x3, x2 // x3 = FdTop = PcdFdBaseAddress + PcdFdSize\r
-\r
- // UEFI Memory Size (stacks are allocated in this region)\r
- LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryUefiRegionSize), x4)\r
-\r
- //\r
- // Reserve the memory for the UEFI region (contain stacks on its top)\r
- //\r
-\r
- // Calculate how much space there is between the top of the Firmware and the Top of the System Memory\r
- subs x0, x1, x3 // x0 = SystemMemoryTop - FdTop\r
- b.mi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM\r
- cmp x0, x4\r
- b.ge _SetupStack\r
-\r
- // Case the top of stacks is the FdBaseAddress\r
- mov x1, x2\r
-\r
-_SetupStack:\r
- // x1 contains the top of the stack (and the UEFI Memory)\r
-\r
- // Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment\r
- // one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the\r
- // top of the memory space)\r
- adds x11, x1, #1\r
- b.cs _SetupOverflowStack\r
-\r
-_SetupAlignedStack:\r
- mov x1, x11\r
- b _GetBaseUefiMemory\r
-\r
-_SetupOverflowStack:\r
- // Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE\r
- // aligned (4KB)\r
- LoadConstantToReg (EFI_PAGE_MASK, x11)\r
- and x11, x11, x1\r
- sub x1, x1, x11\r
-\r
-_GetBaseUefiMemory:\r
- // Calculate the Base of the UEFI Memory\r
- sub x11, x1, x4\r
-\r
-_GetStackBase:\r
- // r1 = The top of the Mpcore Stacks\r
- // Stack for the primary core = PrimaryCoreStack\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), x2)\r
- sub x12, x1, x2\r
-\r
- // Stack for the secondary core = Number of Cores - 1\r
- LoadConstantToReg (FixedPcdGet32(PcdCoreCount), x0)\r
- sub x0, x0, #1\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), x1)\r
- mul x1, x1, x0\r
- sub x12, x12, x1\r
-\r
- // x12 = The base of the MpCore Stacks (primary stack & secondary stacks)\r
- mov x0, x12\r
- mov x1, x10\r
- //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), x2)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), x3)\r
- bl ASM_PFX(ArmPlatformStackSet)\r
-\r
- // Is it the Primary Core ?\r
- mov x0, x10\r
- bl ASM_PFX(ArmPlatformIsPrimaryCore)\r
- cmp x0, #1\r
- bne _PrepareArguments\r
-\r
-_ReserveGlobalVariable:\r
- LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), x0)\r
- // InitializePrimaryStack($GlobalVariableSize, $Tmp1, $Tmp2)\r
- InitializePrimaryStack(x0, x1, x2)\r
-\r
-_PrepareArguments:\r
- mov x0, x10\r
- mov x1, x11\r
- mov x2, x12\r
- mov x3, sp\r
-\r
- // Move sec startup address into a data register\r
- // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
- ldr x4, StartupAddr\r
-\r
- // Jump to PrePiCore C code\r
- // x0 = MpId\r
- // x1 = UefiMemoryBase\r
- // x2 = StacksBase\r
- // x3 = GlobalVariableBase\r
- blr x4\r
-\r
-_NeverReturn:\r
- b _NeverReturn\r
+++ /dev/null
-#/** @file\r
-#\r
-# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>\r
-# Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = ArmVirtPrePiUniCoreRelocatable\r
- FILE_GUID = f7d9fd14-9335-4389-80c5-334d6abfcced\r
- MODULE_TYPE = SEC\r
- VALID_ARCHITECTURES = AARCH64\r
- VERSION_STRING = 1.0\r
-\r
-[Sources]\r
- PrePi.c\r
-\r
-[Sources.AArch64]\r
- AArch64/ArchPrePi.c\r
- AArch64/ModuleEntryPoint.S\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
- ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationPkg.dec\r
- IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
-\r
-[LibraryClasses]\r
- BaseLib\r
- DebugLib\r
- ArmLib\r
- IoLib\r
- TimerLib\r
- SerialPortLib\r
- ExtractGuidedSectionLib\r
- LzmaDecompressLib\r
- PeCoffGetEntryPointLib\r
- PrePiLib\r
- ArmPlatformLib\r
- ArmPlatformStackLib\r
- MemoryAllocationLib\r
- HobLib\r
- PrePiHobListPointerLib\r
- PlatformPeiLib\r
- MemoryInitPeiLib\r
- CacheMaintenanceLib\r
-\r
-[Ppis]\r
- gArmMpCoreInfoPpiGuid\r
-\r
-[Guids]\r
- gArmGlobalVariableGuid\r
- gArmMpCoreInfoGuid\r
-\r
-[FeaturePcd]\r
- gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob\r
- gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores\r
-\r
-[FixedPcd]\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString\r
-\r
- gArmTokenSpaceGuid.PcdVFPEnabled\r
-\r
- gArmTokenSpaceGuid.PcdFdSize\r
- gArmTokenSpaceGuid.PcdFvSize\r
-\r
- gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize\r
-\r
- gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize\r
-\r
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize\r
-\r
- gArmPlatformTokenSpaceGuid.PcdCoreCount\r
-\r
- gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize\r
- gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize\r
-\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode\r
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData\r
-\r
-[Pcd]\r
- gArmTokenSpaceGuid.PcdSystemMemoryBase\r
- gArmTokenSpaceGuid.PcdSystemMemorySize\r
- gArmVirtualizationTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress\r
- gArmTokenSpaceGuid.PcdFdBaseAddress\r
- gArmTokenSpaceGuid.PcdFvBaseAddress\r
-\r
-[BuildOptions]\r
- GCC:*_*_AARCH64_DLINK_FLAGS = -pie -T $(MODULE_DIR)/Scripts/PrePi-PIE.lds\r
+++ /dev/null
-/** @file\r
- LZMA Decompress Library header file\r
-\r
- Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#ifndef __LZMA_DECOMPRESS_H___\r
-#define __LZMA_DECOMPRESS_H___\r
-\r
-/**\r
- Examines a GUIDed section and returns the size of the decoded buffer and the\r
- size of an scratch buffer required to actually decode the data in a GUIDed section.\r
-\r
- Examines a GUIDed section specified by InputSection.\r
- If GUID for InputSection does not match the GUID that this handler supports,\r
- then RETURN_UNSUPPORTED is returned.\r
- If the required information can not be retrieved from InputSection,\r
- then RETURN_INVALID_PARAMETER is returned.\r
- If the GUID of InputSection does match the GUID that this handler supports,\r
- then the size required to hold the decoded buffer is returned in OututBufferSize,\r
- the size of an optional scratch buffer is returned in ScratchSize, and the Attributes field\r
- from EFI_GUID_DEFINED_SECTION header of InputSection is returned in SectionAttribute.\r
-\r
- If InputSection is NULL, then ASSERT().\r
- If OutputBufferSize is NULL, then ASSERT().\r
- If ScratchBufferSize is NULL, then ASSERT().\r
- If SectionAttribute is NULL, then ASSERT().\r
-\r
-\r
- @param[in] InputSection A pointer to a GUIDed section of an FFS formatted file.\r
- @param[out] OutputBufferSize A pointer to the size, in bytes, of an output buffer required\r
- if the buffer specified by InputSection were decoded.\r
- @param[out] ScratchBufferSize A pointer to the size, in bytes, required as scratch space\r
- if the buffer specified by InputSection were decoded.\r
- @param[out] SectionAttribute A pointer to the attributes of the GUIDed section. See the Attributes\r
- field of EFI_GUID_DEFINED_SECTION in the PI Specification.\r
-\r
- @retval RETURN_SUCCESS The information about InputSection was returned.\r
- @retval RETURN_UNSUPPORTED The section specified by InputSection does not match the GUID this handler supports.\r
- @retval RETURN_INVALID_PARAMETER The information can not be retrieved from the section specified by InputSection.\r
-\r
-**/\r
-RETURN_STATUS\r
-EFIAPI\r
-LzmaGuidedSectionGetInfo (\r
- IN CONST VOID *InputSection,\r
- OUT UINT32 *OutputBufferSize,\r
- OUT UINT32 *ScratchBufferSize,\r
- OUT UINT16 *SectionAttribute\r
- );\r
-\r
-/**\r
- Decompress a LZAM compressed GUIDed section into a caller allocated output buffer.\r
-\r
- Decodes the GUIDed section specified by InputSection.\r
- If GUID for InputSection does not match the GUID that this handler supports, then RETURN_UNSUPPORTED is returned.\r
- If the data in InputSection can not be decoded, then RETURN_INVALID_PARAMETER is returned.\r
- If the GUID of InputSection does match the GUID that this handler supports, then InputSection\r
- is decoded into the buffer specified by OutputBuffer and the authentication status of this\r
- decode operation is returned in AuthenticationStatus. If the decoded buffer is identical to the\r
- data in InputSection, then OutputBuffer is set to point at the data in InputSection. Otherwise,\r
- the decoded data will be placed in caller allocated buffer specified by OutputBuffer.\r
-\r
- If InputSection is NULL, then ASSERT().\r
- If OutputBuffer is NULL, then ASSERT().\r
- If ScratchBuffer is NULL and this decode operation requires a scratch buffer, then ASSERT().\r
- If AuthenticationStatus is NULL, then ASSERT().\r
-\r
-\r
- @param[in] InputSection A pointer to a GUIDed section of an FFS formatted file.\r
- @param[out] OutputBuffer A pointer to a buffer that contains the result of a decode operation.\r
- @param[out] ScratchBuffer A caller allocated buffer that may be required by this function\r
- as a scratch buffer to perform the decode operation.\r
- @param[out] AuthenticationStatus\r
- A pointer to the authentication status of the decoded output buffer.\r
- See the definition of authentication status in the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI\r
- section of the PI Specification. EFI_AUTH_STATUS_PLATFORM_OVERRIDE must\r
- never be set by this handler.\r
-\r
- @retval RETURN_SUCCESS The buffer specified by InputSection was decoded.\r
- @retval RETURN_UNSUPPORTED The section specified by InputSection does not match the GUID this handler supports.\r
- @retval RETURN_INVALID_PARAMETER The section specified by InputSection can not be decoded.\r
-\r
-**/\r
-RETURN_STATUS\r
-EFIAPI\r
-LzmaGuidedSectionExtraction (\r
- IN CONST VOID *InputSection,\r
- OUT VOID **OutputBuffer,\r
- OUT VOID *ScratchBuffer, OPTIONAL\r
- OUT UINT32 *AuthenticationStatus\r
- );\r
-\r
-#endif // __LZMADECOMPRESS_H__\r
-\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <PiPei.h>\r
-\r
-#include <Library/PrePiLib.h>\r
-#include <Library/PrintLib.h>\r
-#include <Library/PeCoffGetEntryPointLib.h>\r
-#include <Library/PrePiHobListPointerLib.h>\r
-#include <Library/TimerLib.h>\r
-#include <Library/PerformanceLib.h>\r
-#include <Library/CacheMaintenanceLib.h>\r
-\r
-#include <Ppi/GuidedSectionExtraction.h>\r
-#include <Ppi/ArmMpCoreInfo.h>\r
-#include <Guid/LzmaDecompress.h>\r
-#include <Guid/ArmGlobalVariableHob.h>\r
-\r
-#include "PrePi.h"\r
-#include "LzmaDecompress.h"\r
-\r
-// Not used when PrePi in run in XIP mode\r
-UINTN mGlobalVariableBase = 0;\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-ExtractGuidedSectionLibConstructor (\r
- VOID\r
- );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-LzmaDecompressLibConstructor (\r
- VOID\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-BuildGlobalVariableHob (\r
- IN EFI_PHYSICAL_ADDRESS GlobalVariableBase,\r
- IN UINT32 GlobalVariableSize\r
- )\r
-{\r
- ARM_HOB_GLOBAL_VARIABLE *Hob;\r
-\r
- Hob = CreateHob (EFI_HOB_TYPE_GUID_EXTENSION, sizeof (ARM_HOB_GLOBAL_VARIABLE));\r
- ASSERT(Hob != NULL);\r
-\r
- CopyGuid (&(Hob->Header.Name), &gArmGlobalVariableGuid);\r
- Hob->GlobalVariableBase = GlobalVariableBase;\r
- Hob->GlobalVariableSize = GlobalVariableSize;\r
-}\r
-\r
-EFI_STATUS\r
-GetPlatformPpi (\r
- IN EFI_GUID *PpiGuid,\r
- OUT VOID **Ppi\r
- )\r
-{\r
- UINTN PpiListSize;\r
- UINTN PpiListCount;\r
- EFI_PEI_PPI_DESCRIPTOR *PpiList;\r
- UINTN Index;\r
-\r
- PpiListSize = 0;\r
- ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);\r
- PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);\r
- for (Index = 0; Index < PpiListCount; Index++, PpiList++) {\r
- if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {\r
- *Ppi = PpiList->Ppi;\r
- return EFI_SUCCESS;\r
- }\r
- }\r
-\r
- return EFI_NOT_FOUND;\r
-}\r
-\r
-VOID\r
-PrePiMain (\r
- IN UINTN UefiMemoryBase,\r
- IN UINTN StacksBase,\r
- IN UINTN GlobalVariableBase,\r
- IN UINT64 StartTimeStamp\r
- )\r
-{\r
- EFI_HOB_HANDOFF_INFO_TABLE* HobList;\r
- EFI_STATUS Status;\r
- CHAR8 Buffer[100];\r
- UINTN CharCount;\r
- UINTN StacksSize;\r
-\r
- // Initialize the architecture specific bits\r
- ArchInitialize ();\r
-\r
- // Declare the PI/UEFI memory region\r
- HobList = HobConstructor (\r
- (VOID*)UefiMemoryBase,\r
- FixedPcdGet32 (PcdSystemMemoryUefiRegionSize),\r
- (VOID*)UefiMemoryBase,\r
- (VOID*)StacksBase // The top of the UEFI Memory is reserved for the stacks\r
- );\r
- PrePeiSetHobList (HobList);\r
-\r
- //\r
- // Ensure that the loaded image is invalidated in the caches, so that any\r
- // modifications we made with the caches and MMU off (such as the applied\r
- // relocations) don't become invisible once we turn them on.\r
- //\r
- InvalidateDataCacheRange((VOID *)(UINTN)PcdGet64 (PcdFdBaseAddress), PcdGet32 (PcdFdSize));\r
-\r
- // Initialize MMU and Memory HOBs (Resource Descriptor HOBs)\r
- Status = MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- // Initialize the Serial Port\r
- SerialPortInitialize ();\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware (version %s built at %a on %a)\n\r",\r
- (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);\r
- SerialPortWrite ((UINT8 *) Buffer, CharCount);\r
-\r
- // Create the Stacks HOB (reserve the memory for all stacks)\r
- StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);\r
- BuildStackHob (StacksBase, StacksSize);\r
-\r
- // Declare the Global Variable HOB\r
- BuildGlobalVariableHob (GlobalVariableBase, FixedPcdGet32 (PcdPeiGlobalVariableSize));\r
-\r
- //TODO: Call CpuPei as a library\r
- BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize), PcdGet8 (PcdPrePiCpuIoSize));\r
-\r
- // Set the Boot Mode\r
- SetBootMode (ArmPlatformGetBootMode ());\r
-\r
- // Initialize Platform HOBs (CpuHob and FvHob)\r
- Status = PlatformPeim ();\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- // Now, the HOB List has been initialized, we can register performance information\r
- PERF_START (NULL, "PEI", NULL, StartTimeStamp);\r
-\r
- // SEC phase needs to run library constructors by hand.\r
- ExtractGuidedSectionLibConstructor ();\r
- LzmaDecompressLibConstructor ();\r
-\r
- // Build HOBs to pass up our version of stuff the DXE Core needs to save space\r
- BuildPeCoffLoaderHob ();\r
- BuildExtractSectionHob (\r
- &gLzmaCustomDecompressGuid,\r
- LzmaGuidedSectionGetInfo,\r
- LzmaGuidedSectionExtraction\r
- );\r
-\r
- // Assume the FV that contains the SEC (our code) also contains a compressed FV.\r
- Status = DecompressFirstFv ();\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- // Load the DXE Core and transfer control to it\r
- Status = LoadDxeCoreFromFv (NULL, 0);\r
- ASSERT_EFI_ERROR (Status);\r
-}\r
-\r
-VOID\r
-CEntryPoint (\r
- IN UINTN MpId,\r
- IN UINTN UefiMemoryBase,\r
- IN UINTN StacksBase,\r
- IN UINTN GlobalVariableBase\r
- )\r
-{\r
- UINT64 StartTimeStamp;\r
-\r
- // Initialize the platform specific controllers\r
- ArmPlatformInitialize (MpId);\r
-\r
- if (PerformanceMeasurementEnabled ()) {\r
- // Initialize the Timer Library to setup the Timer HW controller\r
- TimerConstructor ();\r
- // We cannot call yet the PerformanceLib because the HOB List has not been initialized\r
- StartTimeStamp = GetPerformanceCounter ();\r
- } else {\r
- StartTimeStamp = 0;\r
- }\r
-\r
- // Data Cache enabled on Primary core when MMU is enabled.\r
- ArmDisableDataCache ();\r
- // Invalidate Data cache\r
- ArmInvalidateDataCache ();\r
- // Invalidate instruction cache\r
- ArmInvalidateInstructionCache ();\r
- // Enable Instruction Caches on all cores.\r
- ArmEnableInstructionCache ();\r
-\r
- // Define the Global Variable region\r
- mGlobalVariableBase = GlobalVariableBase;\r
-\r
- PrePiMain (UefiMemoryBase, StacksBase, GlobalVariableBase, StartTimeStamp);\r
-\r
- // DXE Core should always load and never return\r
- ASSERT (FALSE);\r
-}\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#ifndef _PREPI_H_\r
-#define _PREPI_H_\r
-\r
-#include <PiPei.h>\r
-\r
-#include <Library/PcdLib.h>\r
-#include <Library/ArmLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <Library/HobLib.h>\r
-#include <Library/SerialPortLib.h>\r
-#include <Library/ArmPlatformLib.h>\r
-\r
-#define SerialPrint(txt) SerialPortWrite (txt, AsciiStrLen(txt)+1);\r
-\r
-RETURN_STATUS\r
-EFIAPI\r
-TimerConstructor (\r
- VOID\r
- );\r
-\r
-VOID\r
-PrePiMain (\r
- IN UINTN UefiMemoryBase,\r
- IN UINTN StacksBase,\r
- IN UINTN GlobalVariableBase,\r
- IN UINT64 StartTimeStamp\r
- );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-MemoryPeim (\r
- IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,\r
- IN UINT64 UefiMemorySize\r
- );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-PlatformPeim (\r
- VOID\r
- );\r
-\r
-// Either implemented by PrePiLib or by MemoryInitPei\r
-VOID\r
-BuildMemoryTypeInformationHob (\r
- VOID\r
- );\r
-\r
-EFI_STATUS\r
-GetPlatformPpi (\r
- IN EFI_GUID *PpiGuid,\r
- OUT VOID **Ppi\r
- );\r
-\r
-// Initialize the Architecture specific controllers\r
-VOID\r
-ArchInitialize (\r
- VOID\r
- );\r
-\r
-#endif /* _PREPI_H_ */\r
+++ /dev/null
-#/** @file\r
-#\r
-# Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#**/\r
-\r
-SECTIONS\r
-{\r
- .text 0x0 : {\r
- PROVIDE(__reloc_base = .);\r
-\r
- *(.text .text*)\r
- *(.got .got*)\r
- *(.rodata .rodata*)\r
- *(.data .data*)\r
-\r
- . = ALIGN(0x20);\r
- PROVIDE(__reloc_start = .);\r
- *(.rela .rela*)\r
- PROVIDE(__reloc_end = .);\r
- }\r
- .bss ALIGN(0x20) : { *(.bss .bss*) }\r
-\r
- /DISCARD/ : {\r
- *(.note.GNU-stack)\r
- *(.gnu_debuglink)\r
- *(.interp)\r
- *(.dynamic)\r
- *(.dynsym)\r
- *(.dynstr)\r
- *(.hash)\r
- *(.comment)\r
- }\r
-}\r
+++ /dev/null
-/** @file\r
-* Device tree enumeration DXE driver for ARM Virtual Machines\r
-*\r
-* Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
-*\r
-* This program and the accompanying materials are\r
-* licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Library/BaseLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/UefiLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
-#include <Library/UefiDriverEntryPoint.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <Library/UefiBootServicesTableLib.h>\r
-#include <Library/VirtioMmioDeviceLib.h>\r
-#include <Library/DevicePathLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/DxeServicesLib.h>\r
-#include <Library/HobLib.h>\r
-#include <libfdt.h>\r
-#include <Library/XenIoMmioLib.h>\r
-\r
-#include <Guid/Fdt.h>\r
-#include <Guid/VirtioMmioTransport.h>\r
-#include <Guid/FdtHob.h>\r
-\r
-#pragma pack (1)\r
-typedef struct {\r
- VENDOR_DEVICE_PATH Vendor;\r
- UINT64 PhysBase;\r
- EFI_DEVICE_PATH_PROTOCOL End;\r
-} VIRTIO_TRANSPORT_DEVICE_PATH;\r
-#pragma pack ()\r
-\r
-typedef enum {\r
- PropertyTypeUnknown,\r
- PropertyTypeGic,\r
- PropertyTypeRtc,\r
- PropertyTypeVirtio,\r
- PropertyTypeUart,\r
- PropertyTypeTimer,\r
- PropertyTypePsci,\r
- PropertyTypeFwCfg,\r
- PropertyTypePciHost,\r
- PropertyTypeGicV3,\r
- PropertyTypeXen,\r
-} PROPERTY_TYPE;\r
-\r
-typedef struct {\r
- PROPERTY_TYPE Type;\r
- CHAR8 Compatible[32];\r
-} PROPERTY;\r
-\r
-STATIC CONST PROPERTY CompatibleProperties[] = {\r
- { PropertyTypeGic, "arm,cortex-a15-gic" },\r
- { PropertyTypeRtc, "arm,pl031" },\r
- { PropertyTypeVirtio, "virtio,mmio" },\r
- { PropertyTypeUart, "arm,pl011" },\r
- { PropertyTypeTimer, "arm,armv7-timer" },\r
- { PropertyTypeTimer, "arm,armv8-timer" },\r
- { PropertyTypePsci, "arm,psci-0.2" },\r
- { PropertyTypeFwCfg, "qemu,fw-cfg-mmio" },\r
- { PropertyTypePciHost, "pci-host-ecam-generic" },\r
- { PropertyTypeGicV3, "arm,gic-v3" },\r
- { PropertyTypeXen, "xen,xen" },\r
- { PropertyTypeUnknown, "" }\r
-};\r
-\r
-typedef struct {\r
- UINT32 Type;\r
- UINT32 Number;\r
- UINT32 Flags;\r
-} INTERRUPT_PROPERTY;\r
-\r
-STATIC\r
-PROPERTY_TYPE\r
-GetTypeFromNode (\r
- IN CONST CHAR8 *NodeType,\r
- IN UINTN Size\r
- )\r
-{\r
- CONST CHAR8 *Compatible;\r
- CONST PROPERTY *CompatibleProperty;\r
-\r
- //\r
- // A 'compatible' node may contain a sequence of NULL terminated\r
- // compatible strings so check each one\r
- //\r
- for (Compatible = NodeType; Compatible < NodeType + Size && *Compatible;\r
- Compatible += 1 + AsciiStrLen (Compatible)) {\r
- for (CompatibleProperty = CompatibleProperties; CompatibleProperty->Compatible[0]; CompatibleProperty++) {\r
- if (AsciiStrCmp (CompatibleProperty->Compatible, Compatible) == 0) {\r
- return CompatibleProperty->Type;\r
- }\r
- }\r
- }\r
- return PropertyTypeUnknown;\r
-}\r
-\r
-//\r
-// We expect the "ranges" property of "pci-host-ecam-generic" to consist of\r
-// records like this.\r
-//\r
-#pragma pack (1)\r
-typedef struct {\r
- UINT32 Type;\r
- UINT64 ChildBase;\r
- UINT64 CpuBase;\r
- UINT64 Size;\r
-} DTB_PCI_HOST_RANGE_RECORD;\r
-#pragma pack ()\r
-\r
-#define DTB_PCI_HOST_RANGE_RELOCATABLE BIT31\r
-#define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30\r
-#define DTB_PCI_HOST_RANGE_ALIASED BIT29\r
-#define DTB_PCI_HOST_RANGE_MMIO32 BIT25\r
-#define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24)\r
-#define DTB_PCI_HOST_RANGE_IO BIT24\r
-#define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)\r
-\r
-/**\r
- Process the device tree node describing the generic PCI host controller.\r
-\r
- param[in] DeviceTreeBase Pointer to the device tree.\r
-\r
- param[in] Node Offset of the device tree node whose "compatible"\r
- property is "pci-host-ecam-generic".\r
-\r
- param[in] RegProp Pointer to the "reg" property of Node. The caller\r
- is responsible for ensuring that the size of the\r
- property is 4 UINT32 cells.\r
-\r
- @retval EFI_SUCCESS Parsing successful, properties parsed from Node\r
- have been stored in dynamic PCDs.\r
-\r
- @retval EFI_PROTOCOL_ERROR Parsing failed. PCDs are left unchanged.\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-EFIAPI\r
-ProcessPciHost (\r
- IN CONST VOID *DeviceTreeBase,\r
- IN INT32 Node,\r
- IN CONST VOID *RegProp\r
- )\r
-{\r
- UINT64 ConfigBase, ConfigSize;\r
- CONST VOID *Prop;\r
- INT32 Len;\r
- UINT32 BusMin, BusMax;\r
- UINT32 RecordIdx;\r
- UINT64 IoBase, IoSize, IoTranslation;\r
- UINT64 MmioBase, MmioSize, MmioTranslation;\r
-\r
- //\r
- // Fetch the ECAM window.\r
- //\r
- ConfigBase = fdt64_to_cpu (((CONST UINT64 *)RegProp)[0]);\r
- ConfigSize = fdt64_to_cpu (((CONST UINT64 *)RegProp)[1]);\r
-\r
- //\r
- // Fetch the bus range (note: inclusive).\r
- //\r
- Prop = fdt_getprop (DeviceTreeBase, Node, "bus-range", &Len);\r
- if (Prop == NULL || Len != 2 * sizeof(UINT32)) {\r
- DEBUG ((EFI_D_ERROR, "%a: 'bus-range' not found or invalid\n",\r
- __FUNCTION__));\r
- return EFI_PROTOCOL_ERROR;\r
- }\r
- BusMin = fdt32_to_cpu (((CONST UINT32 *)Prop)[0]);\r
- BusMax = fdt32_to_cpu (((CONST UINT32 *)Prop)[1]);\r
-\r
- //\r
- // Sanity check: the config space must accommodate all 4K register bytes of\r
- // all 8 functions of all 32 devices of all buses.\r
- //\r
- if (BusMax < BusMin || BusMax - BusMin == MAX_UINT32 ||\r
- DivU64x32 (ConfigSize, SIZE_4KB * 8 * 32) < BusMax - BusMin + 1) {\r
- DEBUG ((EFI_D_ERROR, "%a: invalid 'bus-range' and/or 'reg'\n",\r
- __FUNCTION__));\r
- return EFI_PROTOCOL_ERROR;\r
- }\r
-\r
- //\r
- // Iterate over "ranges".\r
- //\r
- Prop = fdt_getprop (DeviceTreeBase, Node, "ranges", &Len);\r
- if (Prop == NULL || Len == 0 ||\r
- Len % sizeof (DTB_PCI_HOST_RANGE_RECORD) != 0) {\r
- DEBUG ((EFI_D_ERROR, "%a: 'ranges' not found or invalid\n", __FUNCTION__));\r
- return EFI_PROTOCOL_ERROR;\r
- }\r
-\r
- //\r
- // IoBase, IoTranslation, MmioBase and MmioTranslation are initialized only\r
- // in order to suppress '-Werror=maybe-uninitialized' warnings *incorrectly*\r
- // emitted by some gcc versions.\r
- //\r
- IoBase = 0;\r
- IoTranslation = 0;\r
- MmioBase = 0;\r
- MmioTranslation = 0;\r
-\r
- //\r
- // IoSize and MmioSize are initialized to zero because the logic below\r
- // requires it.\r
- //\r
- IoSize = 0;\r
- MmioSize = 0;\r
- for (RecordIdx = 0; RecordIdx < Len / sizeof (DTB_PCI_HOST_RANGE_RECORD);\r
- ++RecordIdx) {\r
- CONST DTB_PCI_HOST_RANGE_RECORD *Record;\r
-\r
- Record = (CONST DTB_PCI_HOST_RANGE_RECORD *)Prop + RecordIdx;\r
- switch (fdt32_to_cpu (Record->Type) & DTB_PCI_HOST_RANGE_TYPEMASK) {\r
- case DTB_PCI_HOST_RANGE_IO:\r
- IoBase = fdt64_to_cpu (Record->ChildBase);\r
- IoSize = fdt64_to_cpu (Record->Size);\r
- IoTranslation = fdt64_to_cpu (Record->CpuBase) - IoBase;\r
- break;\r
-\r
- case DTB_PCI_HOST_RANGE_MMIO32:\r
- MmioBase = fdt64_to_cpu (Record->ChildBase);\r
- MmioSize = fdt64_to_cpu (Record->Size);\r
- MmioTranslation = fdt64_to_cpu (Record->CpuBase) - MmioBase;\r
-\r
- if (MmioBase > MAX_UINT32 || MmioSize > MAX_UINT32 ||\r
- MmioBase + MmioSize > SIZE_4GB) {\r
- DEBUG ((EFI_D_ERROR, "%a: MMIO32 space invalid\n", __FUNCTION__));\r
- return EFI_PROTOCOL_ERROR;\r
- }\r
-\r
- if (MmioTranslation != 0) {\r
- DEBUG ((EFI_D_ERROR, "%a: unsupported nonzero MMIO32 translation "\r
- "0x%Lx\n", __FUNCTION__, MmioTranslation));\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- break;\r
- }\r
- }\r
- if (IoSize == 0 || MmioSize == 0) {\r
- DEBUG ((EFI_D_ERROR, "%a: %a space empty\n", __FUNCTION__,\r
- (IoSize == 0) ? "IO" : "MMIO32"));\r
- return EFI_PROTOCOL_ERROR;\r
- }\r
-\r
- PcdSet64 (PcdPciExpressBaseAddress, ConfigBase);\r
-\r
- PcdSet32 (PcdPciBusMin, BusMin);\r
- PcdSet32 (PcdPciBusMax, BusMax);\r
-\r
- PcdSet64 (PcdPciIoBase, IoBase);\r
- PcdSet64 (PcdPciIoSize, IoSize);\r
- PcdSet64 (PcdPciIoTranslation, IoTranslation);\r
-\r
- PcdSet32 (PcdPciMmio32Base, (UINT32)MmioBase);\r
- PcdSet32 (PcdPciMmio32Size, (UINT32)MmioSize);\r
-\r
- PcdSetBool (PcdPciDisableBusEnumeration, FALSE);\r
-\r
- DEBUG ((EFI_D_INFO, "%a: Config[0x%Lx+0x%Lx) Bus[0x%x..0x%x] "\r
- "Io[0x%Lx+0x%Lx)@0x%Lx Mem[0x%Lx+0x%Lx)@0x%Lx\n", __FUNCTION__, ConfigBase,\r
- ConfigSize, BusMin, BusMax, IoBase, IoSize, IoTranslation, MmioBase,\r
- MmioSize, MmioTranslation));\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-InitializeVirtFdtDxe (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-{\r
- VOID *Hob;\r
- VOID *DeviceTreeBase;\r
- INT32 Node, Prev;\r
- INT32 RtcNode;\r
- EFI_STATUS Status;\r
- CONST CHAR8 *Type;\r
- INT32 Len;\r
- PROPERTY_TYPE PropType;\r
- CONST VOID *RegProp;\r
- VIRTIO_TRANSPORT_DEVICE_PATH *DevicePath;\r
- EFI_HANDLE Handle;\r
- UINT64 RegBase;\r
- UINT64 DistBase, CpuBase, RedistBase;\r
- CONST INTERRUPT_PROPERTY *InterruptProp;\r
- INT32 SecIntrNum, IntrNum, VirtIntrNum, HypIntrNum;\r
- CONST CHAR8 *PsciMethod;\r
- UINT64 FwCfgSelectorAddress;\r
- UINT64 FwCfgSelectorSize;\r
- UINT64 FwCfgDataAddress;\r
- UINT64 FwCfgDataSize;\r
-\r
- Hob = GetFirstGuidHob(&gFdtHobGuid);\r
- if (Hob == NULL || GET_GUID_HOB_DATA_SIZE (Hob) != sizeof (UINT64)) {\r
- return EFI_NOT_FOUND;\r
- }\r
- DeviceTreeBase = (VOID *)(UINTN)*(UINT64 *)GET_GUID_HOB_DATA (Hob);\r
-\r
- if (fdt_check_header (DeviceTreeBase) != 0) {\r
- DEBUG ((EFI_D_ERROR, "%a: No DTB found @ 0x%p\n", __FUNCTION__, DeviceTreeBase));\r
- return EFI_NOT_FOUND;\r
- }\r
-\r
- Status = gBS->InstallConfigurationTable (&gFdtTableGuid, DeviceTreeBase);\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- DEBUG ((EFI_D_INFO, "%a: DTB @ 0x%p\n", __FUNCTION__, DeviceTreeBase));\r
-\r
- RtcNode = -1;\r
- //\r
- // Now enumerate the nodes and install peripherals that we are interested in,\r
- // i.e., GIC, RTC and virtio MMIO nodes\r
- //\r
- for (Prev = 0;; Prev = Node) {\r
- Node = fdt_next_node (DeviceTreeBase, Prev, NULL);\r
- if (Node < 0) {\r
- break;\r
- }\r
-\r
- Type = fdt_getprop (DeviceTreeBase, Node, "compatible", &Len);\r
- if (Type == NULL) {\r
- continue;\r
- }\r
-\r
- PropType = GetTypeFromNode (Type, Len);\r
- if (PropType == PropertyTypeUnknown) {\r
- continue;\r
- }\r
-\r
- //\r
- // Get the 'reg' property of this node. For now, we will assume\r
- // 8 byte quantities for base and size, respectively.\r
- // TODO use #cells root properties instead\r
- //\r
- RegProp = fdt_getprop (DeviceTreeBase, Node, "reg", &Len);\r
- ASSERT ((RegProp != NULL) || (PropType == PropertyTypeTimer) ||\r
- (PropType == PropertyTypePsci));\r
-\r
- switch (PropType) {\r
- case PropertyTypePciHost:\r
- ASSERT (Len == 2 * sizeof (UINT64));\r
- Status = ProcessPciHost (DeviceTreeBase, Node, RegProp);\r
- ASSERT_EFI_ERROR (Status);\r
- break;\r
-\r
- case PropertyTypeFwCfg:\r
- ASSERT (Len == 2 * sizeof (UINT64));\r
-\r
- FwCfgDataAddress = fdt64_to_cpu (((UINT64 *)RegProp)[0]);\r
- FwCfgDataSize = 8;\r
- FwCfgSelectorAddress = FwCfgDataAddress + FwCfgDataSize;\r
- FwCfgSelectorSize = 2;\r
-\r
- //\r
- // The following ASSERT()s express\r
- //\r
- // Address + Size - 1 <= MAX_UINTN\r
- //\r
- // for both registers, that is, that the last byte in each MMIO range is\r
- // expressible as a MAX_UINTN. The form below is mathematically\r
- // equivalent, and it also prevents any unsigned overflow before the\r
- // comparison.\r
- //\r
- ASSERT (FwCfgSelectorAddress <= MAX_UINTN - FwCfgSelectorSize + 1);\r
- ASSERT (FwCfgDataAddress <= MAX_UINTN - FwCfgDataSize + 1);\r
-\r
- PcdSet64 (PcdFwCfgSelectorAddress, FwCfgSelectorAddress);\r
- PcdSet64 (PcdFwCfgDataAddress, FwCfgDataAddress);\r
-\r
- DEBUG ((EFI_D_INFO, "Found FwCfg @ 0x%Lx/0x%Lx\n", FwCfgSelectorAddress,\r
- FwCfgDataAddress));\r
- break;\r
-\r
- case PropertyTypeVirtio:\r
- ASSERT (Len == 16);\r
- //\r
- // Create a unique device path for this transport on the fly\r
- //\r
- RegBase = fdt64_to_cpu (((UINT64 *)RegProp)[0]);\r
- DevicePath = (VIRTIO_TRANSPORT_DEVICE_PATH *)CreateDeviceNode (\r
- HARDWARE_DEVICE_PATH,\r
- HW_VENDOR_DP,\r
- sizeof (VIRTIO_TRANSPORT_DEVICE_PATH));\r
- if (DevicePath == NULL) {\r
- DEBUG ((EFI_D_ERROR, "%a: Out of memory\n", __FUNCTION__));\r
- break;\r
- }\r
-\r
- CopyMem (&DevicePath->Vendor.Guid, &gVirtioMmioTransportGuid,\r
- sizeof (EFI_GUID));\r
- DevicePath->PhysBase = RegBase;\r
- SetDevicePathNodeLength (&DevicePath->Vendor,\r
- sizeof (*DevicePath) - sizeof (DevicePath->End));\r
- SetDevicePathEndNode (&DevicePath->End);\r
-\r
- Handle = NULL;\r
- Status = gBS->InstallProtocolInterface (&Handle,\r
- &gEfiDevicePathProtocolGuid, EFI_NATIVE_INTERFACE,\r
- DevicePath);\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "%a: Failed to install the EFI_DEVICE_PATH "\r
- "protocol on a new handle (Status == %r)\n",\r
- __FUNCTION__, Status));\r
- FreePool (DevicePath);\r
- break;\r
- }\r
-\r
- Status = VirtioMmioInstallDevice (RegBase, Handle);\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "%a: Failed to install VirtIO transport @ 0x%Lx "\r
- "on handle %p (Status == %r)\n", __FUNCTION__, RegBase,\r
- Handle, Status));\r
-\r
- Status = gBS->UninstallProtocolInterface (Handle,\r
- &gEfiDevicePathProtocolGuid, DevicePath);\r
- ASSERT_EFI_ERROR (Status);\r
- FreePool (DevicePath);\r
- }\r
- break;\r
-\r
- case PropertyTypeGic:\r
- ASSERT (Len == 32);\r
-\r
- DistBase = fdt64_to_cpu (((UINT64 *)RegProp)[0]);\r
- CpuBase = fdt64_to_cpu (((UINT64 *)RegProp)[2]);\r
- ASSERT (DistBase < MAX_UINT32);\r
- ASSERT (CpuBase < MAX_UINT32);\r
-\r
- PcdSet32 (PcdGicDistributorBase, (UINT32)DistBase);\r
- PcdSet32 (PcdGicInterruptInterfaceBase, (UINT32)CpuBase);\r
-\r
- DEBUG ((EFI_D_INFO, "Found GIC @ 0x%Lx/0x%Lx\n", DistBase, CpuBase));\r
- break;\r
-\r
- case PropertyTypeGicV3:\r
- //\r
- // The GIC v3 DT binding describes a series of at least 3 physical (base\r
- // addresses, size) pairs: the distributor interface (GICD), at least one\r
- // redistributor region (GICR) containing dedicated redistributor\r
- // interfaces for all individual CPUs, and the CPU interface (GICC).\r
- // Under virtualization, we assume that the first redistributor region\r
- // listed covers the boot CPU. Also, our GICv3 driver only supports the\r
- // system register CPU interface, so we can safely ignore the MMIO version\r
- // which is listed after the sequence of redistributor interfaces.\r
- // This means we are only interested in the first two memory regions\r
- // supplied, and ignore everything else.\r
- //\r
- ASSERT (Len >= 32);\r
-\r
- // RegProp[0..1] == { GICD base, GICD size }\r
- DistBase = fdt64_to_cpu (((UINT64 *)RegProp)[0]);\r
- ASSERT (DistBase < MAX_UINT32);\r
-\r
- // RegProp[2..3] == { GICR base, GICR size }\r
- RedistBase = fdt64_to_cpu (((UINT64 *)RegProp)[2]);\r
- ASSERT (RedistBase < MAX_UINT32);\r
-\r
- PcdSet32 (PcdGicDistributorBase, (UINT32)DistBase);\r
- PcdSet32 (PcdGicRedistributorsBase, (UINT32)RedistBase);\r
-\r
- DEBUG ((EFI_D_INFO, "Found GIC v3 (re)distributor @ 0x%Lx (0x%Lx)\n",\r
- DistBase, RedistBase));\r
- break;\r
-\r
- case PropertyTypeRtc:\r
- ASSERT (Len == 16);\r
-\r
- RegBase = fdt64_to_cpu (((UINT64 *)RegProp)[0]);\r
- ASSERT (RegBase < MAX_UINT32);\r
-\r
- PcdSet32 (PcdPL031RtcBase, (UINT32)RegBase);\r
-\r
- DEBUG ((EFI_D_INFO, "Found PL031 RTC @ 0x%Lx\n", RegBase));\r
- RtcNode = Node;\r
- break;\r
-\r
- case PropertyTypeTimer:\r
- //\r
- // - interrupts : Interrupt list for secure, non-secure, virtual and\r
- // hypervisor timers, in that order.\r
- //\r
- InterruptProp = fdt_getprop (DeviceTreeBase, Node, "interrupts", &Len);\r
- ASSERT (Len == 36 || Len == 48);\r
-\r
- SecIntrNum = fdt32_to_cpu (InterruptProp[0].Number)\r
- + (InterruptProp[0].Type ? 16 : 0);\r
- IntrNum = fdt32_to_cpu (InterruptProp[1].Number)\r
- + (InterruptProp[1].Type ? 16 : 0);\r
- VirtIntrNum = fdt32_to_cpu (InterruptProp[2].Number)\r
- + (InterruptProp[2].Type ? 16 : 0);\r
- HypIntrNum = Len < 48 ? 0 : fdt32_to_cpu (InterruptProp[3].Number)\r
- + (InterruptProp[3].Type ? 16 : 0);\r
-\r
- DEBUG ((EFI_D_INFO, "Found Timer interrupts %d, %d, %d, %d\n",\r
- SecIntrNum, IntrNum, VirtIntrNum, HypIntrNum));\r
-\r
- PcdSet32 (PcdArmArchTimerSecIntrNum, SecIntrNum);\r
- PcdSet32 (PcdArmArchTimerIntrNum, IntrNum);\r
- PcdSet32 (PcdArmArchTimerVirtIntrNum, VirtIntrNum);\r
- PcdSet32 (PcdArmArchTimerHypIntrNum, HypIntrNum);\r
- break;\r
-\r
- case PropertyTypePsci:\r
- PsciMethod = fdt_getprop (DeviceTreeBase, Node, "method", &Len);\r
-\r
- if (PsciMethod && AsciiStrnCmp (PsciMethod, "hvc", 3) == 0) {\r
- PcdSet32 (PcdArmPsciMethod, 1);\r
- } else if (PsciMethod && AsciiStrnCmp (PsciMethod, "smc", 3) == 0) {\r
- PcdSet32 (PcdArmPsciMethod, 2);\r
- } else {\r
- DEBUG ((EFI_D_ERROR, "%a: Unknown PSCI method \"%a\"\n", __FUNCTION__,\r
- PsciMethod));\r
- }\r
- break;\r
-\r
- case PropertyTypeXen:\r
- ASSERT (Len == 16);\r
-\r
- //\r
- // Retrieve the reg base from this node and wire it up to the\r
- // MMIO flavor of the XenBus root device I/O protocol\r
- //\r
- RegBase = fdt64_to_cpu (((UINT64 *)RegProp)[0]);\r
- Handle = NULL;\r
- Status = XenIoMmioInstall (&Handle, RegBase);\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "%a: XenIoMmioInstall () failed on a new handle "\r
- "(Status == %r)\n", __FUNCTION__, Status));\r
- break;\r
- }\r
-\r
- DEBUG ((EFI_D_INFO, "Found Xen node with Grant table @ 0x%Lx\n", RegBase));\r
-\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
- }\r
-\r
- //\r
- // UEFI takes ownership of the RTC hardware, and exposes its functionality\r
- // through the UEFI Runtime Services GetTime, SetTime, etc. This means we\r
- // need to disable it in the device tree to prevent the OS from attaching its\r
- // device driver as well.\r
- //\r
- if ((RtcNode != -1) &&\r
- fdt_setprop_string (DeviceTreeBase, RtcNode, "status",\r
- "disabled") != 0) {\r
- DEBUG ((EFI_D_WARN, "Failed to set PL031 status to 'disabled'\n"));\r
- }\r
- return EFI_SUCCESS;\r
-}\r
+++ /dev/null
-## @file\r
-# Device tree enumeration DXE driver for ARM Virtual Machines\r
-#\r
-# Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials are\r
-# licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-##\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = VirtFdtDxe\r
- FILE_GUID = 9AD7DCB4-E6EC-472E-96BF-81C219A3F77E\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
-\r
- ENTRY_POINT = InitializeVirtFdtDxe\r
-\r
-[Sources]\r
- VirtFdtDxe.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
- ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationPkg.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
- OvmfPkg/OvmfPkg.dec\r
-\r
-[LibraryClasses]\r
- BaseLib\r
- PcdLib\r
- UefiDriverEntryPoint\r
- DxeServicesLib\r
- FdtLib\r
- VirtioMmioDeviceLib\r
- HobLib\r
- XenIoMmioLib\r
-\r
-[Guids]\r
- gFdtTableGuid\r
- gVirtioMmioTransportGuid\r
- gFdtHobGuid\r
-\r
-[Pcd]\r
- gArmVirtualizationTokenSpaceGuid.PcdArmPsciMethod\r
- gArmVirtualizationTokenSpaceGuid.PcdFwCfgSelectorAddress\r
- gArmVirtualizationTokenSpaceGuid.PcdFwCfgDataAddress\r
- gArmTokenSpaceGuid.PcdGicDistributorBase\r
- gArmTokenSpaceGuid.PcdGicRedistributorsBase\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
- gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum\r
- gArmTokenSpaceGuid.PcdArmArchTimerIntrNum\r
- gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum\r
- gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum\r
- gArmPlatformTokenSpaceGuid.PcdPL031RtcBase\r
- gArmPlatformTokenSpaceGuid.PcdPciBusMin\r
- gArmPlatformTokenSpaceGuid.PcdPciBusMax\r
- gArmPlatformTokenSpaceGuid.PcdPciIoBase\r
- gArmPlatformTokenSpaceGuid.PcdPciIoSize\r
- gArmPlatformTokenSpaceGuid.PcdPciIoTranslation\r
- gArmPlatformTokenSpaceGuid.PcdPciMmio32Base\r
- gArmPlatformTokenSpaceGuid.PcdPciMmio32Size\r
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration\r
-\r
-[Protocols]\r
- gEfiDevicePathProtocolGuid\r
-\r
-[Depex]\r
- TRUE\r
--- /dev/null
+#\r
+# Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
+# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+\r
+[Defines]\r
+ DEFINE DEBUG_PRINT_ERROR_LEVEL = 0x8000004F\r
+\r
+[LibraryClasses.common]\r
+!if $(TARGET) == RELEASE\r
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf\r
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf\r
+!else\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ UncachedMemoryAllocationLib|ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf\r
+!endif\r
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf\r
+\r
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf\r
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf\r
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf\r
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf\r
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf\r
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf\r
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf\r
+\r
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf\r
+ HobLib|ArmVirtPkg/Library/ArmVirtDxeHobLib/ArmVirtDxeHobLib.inf\r
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf\r
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf\r
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf\r
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf\r
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf\r
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf\r
+\r
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf\r
+ OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf\r
+\r
+ #\r
+ # Allow dynamic PCDs\r
+ #\r
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
+\r
+ # 1/123 faster than Stm or Vstm version\r
+ #BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf\r
+ BaseMemoryLib|ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf\r
+\r
+ # Networking Requirements\r
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf\r
+ DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf\r
+ UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf\r
+ IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf\r
+\r
+ # ARM Architectural Libraries\r
+ CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf\r
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf\r
+ CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf\r
+ ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf\r
+ DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf\r
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf\r
+ ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf\r
+ ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf\r
+ ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf\r
+ ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.inf\r
+\r
+ PlatformPeiLib|ArmVirtPkg/Library/PlatformPeiLib/PlatformPeiLib.inf\r
+ MemoryInitPeiLib|ArmVirtPkg/Library/ArmVirtMemoryInitPeiLib/ArmVirtMemoryInitPeiLib.inf\r
+ EfiResetSystemLib|ArmVirtPkg/Library/ArmVirtPsciResetSystemLib/ArmVirtPsciResetSystemLib.inf\r
+\r
+ # ARM PL031 RTC Driver\r
+ RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf\r
+ # ARM PL011 UART Driver\r
+ PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf\r
+ SerialPortLib|ArmVirtPkg/Library/FdtPL011SerialPortLib/FdtPL011SerialPortLib.inf\r
+ SerialPortExtLib|EmbeddedPkg/Library/SerialPortExtLibNull/SerialPortExtLibNull.inf\r
+\r
+ #\r
+ # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window\r
+ # in the debugger will show load and unload commands for symbols. You can cut and paste this\r
+ # into the command window to load symbols. We should be able to use a script to do this, but\r
+ # the version of RVD I have does not support scripts accessing system memory.\r
+ #\r
+ #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf\r
+ PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf\r
+ #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf\r
+\r
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf\r
+ DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf\r
+\r
+ # BDS Libraries\r
+ BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf\r
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf\r
+\r
+ # PCI Libraries\r
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf\r
+ PciExpressLib|ArmVirtPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpressLib.inf\r
+\r
+ # USB Libraries\r
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf\r
+\r
+ XenIoMmioLib|OvmfPkg/Library/XenIoMmioLib/XenIoMmioLib.inf\r
+\r
+ #\r
+ # Secure Boot dependencies\r
+ #\r
+!if $(SECURE_BOOT_ENABLE) == TRUE\r
+ IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf\r
+ OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf\r
+ TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf\r
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf\r
+\r
+ # re-use the UserPhysicalPresent() dummy implementation from the ovmf tree\r
+ PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf\r
+!endif\r
+\r
+[LibraryClasses.common.SEC]\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ ArmPlatformSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf\r
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Sec/SecArmPlatformGlobalVariableLib.inf\r
+\r
+ DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf\r
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf\r
+ SerialPortLib|ArmVirtPkg/Library/FdtPL011SerialPortLib/EarlyFdtPL011SerialPortLib.inf\r
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf\r
+ PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
+\r
+[LibraryClasses.common.PEI_CORE]\r
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf\r
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf\r
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf\r
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf\r
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf\r
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf\r
+\r
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.inf\r
+ PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf\r
+ SerialPortLib|ArmVirtPkg/Library/FdtPL011SerialPortLib/EarlyFdtPL011SerialPortLib.inf\r
+\r
+[LibraryClasses.common.PEIM]\r
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf\r
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf\r
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf\r
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf\r
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf\r
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+ PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf\r
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf\r
+\r
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.inf\r
+ PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf\r
+ SerialPortLib|ArmVirtPkg/Library/FdtPL011SerialPortLib/EarlyFdtPL011SerialPortLib.inf\r
+\r
+[LibraryClasses.common.DXE_CORE]\r
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf\r
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf\r
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf\r
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf\r
+ PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf\r
+\r
+[LibraryClasses.common.DXE_DRIVER]\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf\r
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf\r
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Dxe/DxeArmPlatformGlobalVariableLib.inf\r
+\r
+[LibraryClasses.common.UEFI_APPLICATION]\r
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf\r
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf\r
+\r
+[LibraryClasses.common.UEFI_DRIVER]\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf\r
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+\r
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf\r
+\r
+!if $(SECURE_BOOT_ENABLE) == TRUE\r
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf\r
+!endif\r
+\r
+[LibraryClasses.ARM]\r
+ #\r
+ # It is not possible to prevent the ARM compiler for generic intrinsic functions.\r
+ # This library provides the instrinsic functions generate by a given compiler.\r
+ # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.\r
+ #\r
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf\r
+\r
+ # Add support for GCC stack protector\r
+ NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf\r
+\r
+[LibraryClasses.AARCH64]\r
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf\r
+\r
+\r
+[BuildOptions]\r
+ RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG\r
+\r
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG\r
+\r
+################################################################################\r
+#\r
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform\r
+#\r
+################################################################################\r
+\r
+[PcdsFeatureFlag.common]\r
+ gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE\r
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE\r
+ gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE\r
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE\r
+\r
+ #\r
+ # Control what commands are supported from the UI\r
+ # Turn these on and off to add features or save size\r
+ #\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE\r
+\r
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE\r
+\r
+ # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress\r
+ gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE\r
+\r
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE\r
+\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE\r
+\r
+[PcdsFixedAtBuild.common]\r
+ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Virtualization Platform"\r
+\r
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000\r
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000\r
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000\r
+ gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF\r
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1\r
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0\r
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320\r
+\r
+ # DEBUG_ASSERT_ENABLED 0x01\r
+ # DEBUG_PRINT_ENABLED 0x02\r
+ # DEBUG_CODE_ENABLED 0x04\r
+ # CLEAR_MEMORY_ENABLED 0x08\r
+ # ASSERT_BREAKPOINT_ENABLED 0x10\r
+ # ASSERT_DEADLOOP_ENABLED 0x20\r
+!if $(TARGET) == RELEASE\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21\r
+!else\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f\r
+!endif\r
+\r
+ # DEBUG_INIT 0x00000001 // Initialization\r
+ # DEBUG_WARN 0x00000002 // Warnings\r
+ # DEBUG_LOAD 0x00000004 // Load events\r
+ # DEBUG_FS 0x00000008 // EFI File system\r
+ # DEBUG_POOL 0x00000010 // Alloc & Free's\r
+ # DEBUG_PAGE 0x00000020 // Alloc & Free's\r
+ # DEBUG_INFO 0x00000040 // Informational debug messages\r
+ # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers\r
+ # DEBUG_VARIABLE 0x00000100 // Variable\r
+ # DEBUG_BM 0x00000400 // Boot Manager\r
+ # DEBUG_BLKIO 0x00001000 // BlkIo Driver\r
+ # DEBUG_NET 0x00004000 // SNI Driver\r
+ # DEBUG_UNDI 0x00010000 // UNDI Driver\r
+ # DEBUG_LOADFILE 0x00020000 // UNDI Driver\r
+ # DEBUG_EVENT 0x00080000 // Event messages\r
+ # DEBUG_GCD 0x00100000 // Global Coherency Database changes\r
+ # DEBUG_CACHE 0x00200000 // Memory range cachability changes\r
+ # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may\r
+ # // significantly impact boot performance\r
+ # DEBUG_ERROR 0x80000000 // Error\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|$(DEBUG_PRINT_ERROR_LEVEL)\r
+\r
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07\r
+\r
+ #\r
+ # Optional feature to help prevent EFI memory map fragments\r
+ # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob\r
+ # Values are in EFI Pages (4K). DXE Core will make sure that\r
+ # at least this much of each type of memory can be allocated\r
+ # from a single memory range. This way you only end up with\r
+ # maximum of two fragements for each type in the memory map\r
+ # (the memory used, and the free memory that was prereserved\r
+ # but not used).\r
+ #\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|50\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|20\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0\r
+\r
+ #\r
+ # ARM Pcds\r
+ #\r
+ gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000000000000\r
+\r
+!if $(SECURE_BOOT_ENABLE) == TRUE\r
+ # override the default values from SecurityPkg to ensure images from all sources are verified in secure boot\r
+ gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04\r
+ gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04\r
+ gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04\r
+!endif\r
+\r
+[Components.common]\r
+ #\r
+ # Networking stack\r
+ #\r
+ MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf\r
+ MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf\r
+ MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf\r
+ MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf\r
+ MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf\r
+ MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf\r
+ MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf\r
+ MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf\r
+ MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf\r
+ MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf\r
+ MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf\r
+ MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf\r
+\r
+ #\r
+ # UEFI application (Shell Embedded Boot Loader)\r
+ #\r
+ ShellPkg/Application/Shell/Shell.inf {\r
+ <LibraryClasses>\r
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf\r
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf\r
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf\r
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf\r
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf\r
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf\r
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf\r
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf\r
+\r
+ <PcdsFixedAtBuild>\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF\r
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE\r
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000\r
+ }\r
--- /dev/null
+#/** @file\r
+#\r
+# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ DEC_SPECIFICATION = 0x00010005\r
+ PACKAGE_NAME = ArmVirtPkg\r
+ PACKAGE_GUID = A0B31216-508E-4025-BEAB-56D836C66F0A\r
+ PACKAGE_VERSION = 0.1\r
+\r
+################################################################################\r
+#\r
+# Include Section - list of Include Paths that are provided by this package.\r
+# Comments are used for Keywords and Module Types.\r
+#\r
+# Supported Module Types:\r
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
+#\r
+################################################################################\r
+[Includes.common]\r
+ Include # Root include for the package\r
+\r
+[Guids.common]\r
+ gArmVirtTokenSpaceGuid = { 0x0B6F5CA7, 0x4F53, 0x445A, { 0xB7, 0x6E, 0x2E, 0x36, 0x5B, 0x80, 0x63, 0x66 } }\r
+ gEarlyPL011BaseAddressGuid = { 0xB199DEA9, 0xFD5C, 0x4A84, { 0x80, 0x82, 0x2F, 0x41, 0x70, 0x78, 0x03, 0x05 } }\r
+\r
+[PcdsFixedAtBuild, PcdsPatchableInModule]\r
+ #\r
+ # This is the physical address where the device tree is expected to be stored\r
+ # upon first entry into UEFI. This needs to be a FixedAtBuild PCD, so that we\r
+ # can do a first pass over the device tree in the SEC phase to discover the\r
+ # UART base address.\r
+ #\r
+ gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x0|UINT64|0x00000001\r
+\r
+ #\r
+ # Padding in bytes to add to the device tree allocation, so that the DTB can\r
+ # be modified in place (default: 256 bytes)\r
+ #\r
+ gArmVirtTokenSpaceGuid.PcdDeviceTreeAllocationPadding|256|UINT32|0x00000002\r
+\r
+[PcdsDynamic, PcdsFixedAtBuild]\r
+ #\r
+ # ARM PSCI function invocations can be done either through hypervisor\r
+ # calls (HVC) or secure monitor calls (SMC).\r
+ # PcdArmPsciMethod == 1 : use HVC\r
+ # PcdArmPsciMethod == 2 : use SMC\r
+ #\r
+ gArmVirtTokenSpaceGuid.PcdArmPsciMethod|0|UINT32|0x00000003\r
+\r
+ gArmVirtTokenSpaceGuid.PcdFwCfgSelectorAddress|0x0|UINT64|0x00000004\r
+ gArmVirtTokenSpaceGuid.PcdFwCfgDataAddress|0x0|UINT64|0x00000005\r
+\r
+[PcdsFeatureFlag]\r
+ #\r
+ # "Map PCI MMIO as Cached"\r
+ #\r
+ # Due to the way Stage1 and Stage2 mappings are combined on Aarch64, and\r
+ # because KVM -- for the time being -- does not try to interfere with the\r
+ # Stage1 mappings, we must not set EFI_MEMORY_UC for emulated PCI MMIO\r
+ # regions.\r
+ #\r
+ # EFI_MEMORY_UC is mapped to Device-nGnRnE, and that Stage1 attribute would\r
+ # direct guest writes to host DRAM immediately, bypassing the cache\r
+ # regardless of Stage2 attributes. However, QEMU's reads of the same range\r
+ # can easily be served from the (stale) CPU cache.\r
+ #\r
+ # Setting this PCD to TRUE will use EFI_MEMORY_WB for mapping PCI MMIO\r
+ # regions, which ensures that guest writes to such regions go through the CPU\r
+ # cache. Strictly speaking this is wrong, but it is needed as a temporary\r
+ # workaround for emulated PCI devices. Setting the PCD to FALSE results in\r
+ # the theoretically correct EFI_MEMORY_UC mapping, and should be the long\r
+ # term choice, especially with assigned devices.\r
+ #\r
+ # The default is to turn off the kludge; DSC's can selectively enable it.\r
+ #\r
+ gArmVirtTokenSpaceGuid.PcdKludgeMapPciMmioAsCached|FALSE|BOOLEAN|0x00000006\r
--- /dev/null
+#\r
+# Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
+# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ PLATFORM_NAME = ArmVirtQemu\r
+ PLATFORM_GUID = 37d7e986-f7e9-45c2-8067-e371421a626c\r
+ PLATFORM_VERSION = 0.1\r
+ DSC_SPECIFICATION = 0x00010005\r
+ OUTPUT_DIRECTORY = Build/ArmVirtQemu-$(ARCH)\r
+ SUPPORTED_ARCHITECTURES = AARCH64|ARM\r
+ BUILD_TARGETS = DEBUG|RELEASE\r
+ SKUID_IDENTIFIER = DEFAULT\r
+ FLASH_DEFINITION = ArmVirtPkg/ArmVirtQemu.fdf\r
+\r
+ #\r
+ # Defines for default states. These can be changed on the command line.\r
+ # -D FLAG=VALUE\r
+ #\r
+ DEFINE SECURE_BOOT_ENABLE = FALSE\r
+\r
+!include ArmVirtPkg/ArmVirt.dsc.inc\r
+\r
+[LibraryClasses.AARCH64]\r
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf\r
+ ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexAEMv8Lib/ArmCortexAEMv8Lib.inf\r
+\r
+[LibraryClasses.ARM]\r
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
+ ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf\r
+\r
+[LibraryClasses.common]\r
+ # Virtio Support\r
+ VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf\r
+ VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDeviceLib.inf\r
+ QemuFwCfgLib|ArmVirtPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf\r
+\r
+ ArmPlatformLib|ArmVirtPkg/Library/ArmVirtPlatformLib/ArmVirtPlatformLib.inf\r
+ ArmPlatformSysConfigLib|ArmPlatformPkg/Library/ArmPlatformSysConfigLibNull/ArmPlatformSysConfigLibNull.inf\r
+\r
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf\r
+ NorFlashPlatformLib|ArmVirtPkg/Library/NorFlashQemuLib/NorFlashQemuLib.inf\r
+\r
+!ifdef INTEL_BDS\r
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf\r
+ GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf\r
+ PlatformBdsLib|ArmVirtPkg/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf\r
+ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf\r
+ QemuBootOrderLib|OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.inf\r
+!endif\r
+\r
+[LibraryClasses.common.UEFI_DRIVER]\r
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf\r
+\r
+[LibraryClasses.AARCH64.SEC]\r
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf\r
+\r
+[LibraryClasses.ARM.SEC]\r
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf\r
+\r
+[BuildOptions]\r
+ RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A15 -I$(WORKSPACE)/ArmVirtPkg/Include\r
+ GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a15 -I$(WORKSPACE)/ArmVirtPkg/Include\r
+ *_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmVirtPkg/Include\r
+\r
+\r
+################################################################################\r
+#\r
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform\r
+#\r
+################################################################################\r
+\r
+[PcdsFeatureFlag.common]\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|TRUE\r
+\r
+ ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.\r
+ # It could be set FALSE to save size.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE\r
+\r
+ # Activate KVM workaround for now.\r
+ gArmVirtTokenSpaceGuid.PcdKludgeMapPciMmioAsCached|TRUE\r
+\r
+[PcdsFixedAtBuild.common]\r
+ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"QEMU"\r
+\r
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|1\r
+!if $(ARCH) == AARCH64\r
+ gArmTokenSpaceGuid.PcdVFPEnabled|1\r
+!endif\r
+\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x4007c000\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000\r
+\r
+ # Size of the region used by UEFI in permanent memory (Reserved 64MB)\r
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000\r
+\r
+ #\r
+ # ARM Pcds\r
+ #\r
+ gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000\r
+\r
+ ## Trustzone enable (to make the transition from EL3 to EL2 in ArmPlatformPkg/Sec)\r
+ gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE\r
+\r
+ #\r
+ # ARM PrimeCell\r
+ #\r
+\r
+ ## PL011 - Serial Terminal\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400\r
+\r
+ #\r
+ # ARM OS Loader\r
+ #\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux (EFI stub) on virtio31:hd0:part0"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(837DCA9E-E874-4D82-B29A-23FE0E23D1E2,003E000A00000000)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/Image"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"root=/dev/vda2 console=ttyAMA0 earlycon uefi_debug"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootType|0\r
+\r
+ #\r
+ # Settings for ARM BDS -- use the serial console (ConIn & ConOut).\r
+ #\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenVt100()"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenVt100()"\r
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3\r
+\r
+ #\r
+ # ARM Virtual Architectural Timer -- fetch frequency from QEMU (TCG) or KVM\r
+ #\r
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0\r
+\r
+ #\r
+ # NV Storage PCDs. Use base of 0x04000000 for NOR1\r
+ #\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x04000000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00040000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x04040000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00040000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x04080000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00040000\r
+\r
+ # System Memory Base -- fixed at 0x4000_0000\r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x40000000\r
+\r
+ # initial location of the device tree blob passed by QEMU -- base of DRAM\r
+ gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x40000000\r
+\r
+!ifdef INTEL_BDS\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }\r
+!endif\r
+\r
+ #\r
+ # The maximum physical I/O addressability of the processor, set with\r
+ # BuildCpuHob().\r
+ #\r
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16\r
+\r
+[PcdsDynamicDefault.common]\r
+ ## If TRUE, OvmfPkg/AcpiPlatformDxe will not wait for PCI\r
+ # enumeration to complete before installing ACPI tables.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE\r
+\r
+ # System Memory Size -- 1 MB initially, actual size will be fetched from DT\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x00100000\r
+\r
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|0x0\r
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|0x0\r
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|0x0\r
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|0x0\r
+\r
+ #\r
+ # ARM General Interrupt Controller\r
+ #\r
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x0\r
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x0\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x0\r
+\r
+ ## PL031 RealTimeClock\r
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0\r
+\r
+ gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0\r
+ gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0\r
+ gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0\r
+ gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0\r
+ gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0\r
+ gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0\r
+ gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0\r
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x0\r
+\r
+ gArmVirtTokenSpaceGuid.PcdArmPsciMethod|0\r
+\r
+ gArmVirtTokenSpaceGuid.PcdFwCfgSelectorAddress|0x0\r
+ gArmVirtTokenSpaceGuid.PcdFwCfgDataAddress|0x0\r
+\r
+ #\r
+ # Set video resolution for boot options and for text setup.\r
+ # PlatformDxe can set the former at runtime.\r
+ #\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480\r
+\r
+################################################################################\r
+#\r
+# Components Section - list of all EDK II Modules needed by this Platform\r
+#\r
+################################################################################\r
+[Components.common]\r
+ #\r
+ # PEI Phase modules\r
+ #\r
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf {\r
+ <LibraryClasses>\r
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.inf\r
+ }\r
+ MdeModulePkg/Core/Pei/PeiMain.inf\r
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
+ ArmPlatformPkg/PlatformPei/PlatformPeim.inf\r
+ ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf\r
+ ArmPkg/Drivers/CpuPei/CpuPei.inf\r
+\r
+!if $(SECURE_BOOT_ENABLE) == TRUE\r
+ SecurityPkg/VariableAuthenticated/Pei/VariablePei.inf {\r
+ <LibraryClasses>\r
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf\r
+ }\r
+!else\r
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
+!endif\r
+\r
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {\r
+ <LibraryClasses>\r
+ NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf\r
+ }\r
+\r
+ #\r
+ # DXE\r
+ #\r
+ MdeModulePkg/Core/Dxe/DxeMain.inf {\r
+ <LibraryClasses>\r
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf\r
+ }\r
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
+\r
+ #\r
+ # Architectural Protocols\r
+ #\r
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+!if $(SECURE_BOOT_ENABLE) == TRUE\r
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {\r
+ <LibraryClasses>\r
+ NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf\r
+ }\r
+ SecurityPkg/VariableAuthenticated/RuntimeDxe/VariableRuntimeDxe.inf {\r
+ <LibraryClasses>\r
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf\r
+ OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf\r
+ }\r
+ SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf\r
+!else\r
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
+!endif\r
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
+\r
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+ EmbeddedPkg/SerialDxe/SerialDxe.inf\r
+\r
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+\r
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
+!if $(SECURE_BOOT_ENABLE) == TRUE\r
+ ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashAuthenticatedDxe.inf\r
+!else\r
+ ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
+!endif\r
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
+\r
+ #\r
+ # Platform Driver\r
+ #\r
+ ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.inf\r
+ OvmfPkg/VirtioBlkDxe/VirtioBlk.inf\r
+ OvmfPkg/VirtioScsiDxe/VirtioScsi.inf\r
+ OvmfPkg/VirtioNetDxe/VirtioNet.inf\r
+\r
+ #\r
+ # FAT filesystem + GPT/MBR partitioning\r
+ #\r
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+\r
+ #\r
+ # Bds\r
+ #\r
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+!ifdef INTEL_BDS\r
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf\r
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
+ IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf\r
+!else\r
+ ArmPlatformPkg/Bds/Bds.inf\r
+!endif\r
+\r
+ #\r
+ # SCSI Bus and Disk Driver\r
+ #\r
+ MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf\r
+ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf\r
+\r
+ #\r
+ # ACPI Support\r
+ #\r
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf\r
+ OvmfPkg/AcpiPlatformDxe/QemuFwCfgAcpiPlatformDxe.inf\r
+\r
+ #\r
+ # PCI support\r
+ #\r
+ ArmVirtPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf\r
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf\r
+ OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf\r
+\r
+ #\r
+ # Video support\r
+ #\r
+ OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf {\r
+ <LibraryClasses>\r
+ BltLib|OptionRomPkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf\r
+ }\r
+ OvmfPkg/PlatformDxe/Platform.inf\r
+\r
+ #\r
+ # USB Support\r
+ #\r
+ MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf\r
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf\r
+ MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf\r
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf\r
+ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf\r
--- /dev/null
+#\r
+# Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
+# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+\r
+################################################################################\r
+#\r
+# FD Section\r
+# The [FD] Section is made up of the definition statements and a\r
+# description of what goes into the Flash Device Image. Each FD section\r
+# defines one flash "device" image. A flash device image may be one of\r
+# the following: Removable media bootable image (like a boot floppy\r
+# image,) an Option ROM image (that would be "flashed" into an add-in\r
+# card,) a System "Flash" image (that would be burned into a system's\r
+# flash) or an Update ("Capsule") image that will be used to update and\r
+# existing system flash.\r
+#\r
+################################################################################\r
+\r
+[FD.QEMU_EFI]\r
+BaseAddress = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress # QEMU assigns 0 - 0x8000000 for a BootROM\r
+Size = 0x00200000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device\r
+ErasePolarity = 1\r
+\r
+# This one is tricky, it must be: BlockSize * NumBlocks = Size\r
+BlockSize = 0x00001000\r
+NumBlocks = 0x200\r
+\r
+################################################################################\r
+#\r
+# Following are lists of FD Region layout which correspond to the locations of different\r
+# images within the flash device.\r
+#\r
+# Regions must be defined in ascending order and may not overlap.\r
+#\r
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by\r
+# the pipe "|" character, followed by the size of the region, also in hex with the leading\r
+# "0x" characters. Like:\r
+# Offset|Size\r
+# PcdOffsetCName|PcdSizeCName\r
+# RegionType <FV, DATA, or FILE>\r
+#\r
+################################################################################\r
+\r
+#\r
+# UEFI has trouble dealing with FVs that reside at physical address 0x0.\r
+# So instead, put a hardcoded 'jump to 0x1000' at offset 0x0, and put the\r
+# real FV at offset 0x1000\r
+#\r
+0x00000000|0x00001000\r
+DATA = {\r
+!if $(ARCH) == AARCH64\r
+ 0x00, 0x04, 0x00, 0x14 # 'b 0x1000' in AArch64 ASM\r
+!else\r
+ 0xfe, 0x03, 0x00, 0xea # 'b 0x1000' in AArch32 ASM\r
+!endif\r
+}\r
+\r
+0x00001000|0x001ff000\r
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize\r
+FV = FVMAIN_COMPACT\r
+\r
+\r
+################################################################################\r
+#\r
+# FV Section\r
+#\r
+# [FV] section is used to define what components or modules are placed within a flash\r
+# device file. This section also defines order the components and modules are positioned\r
+# within the image. The [FV] section consists of define statements, set statements and\r
+# module statements.\r
+#\r
+################################################################################\r
+\r
+[FV.FvMain]\r
+BlockSize = 0x40\r
+NumBlocks = 0 # This FV gets compressed so make it just big enough\r
+FvAlignment = 16 # FV alignment and FV attributes setting.\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+ APRIORI DXE {\r
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
+ INF ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.inf\r
+ }\r
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf\r
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
+ INF ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.inf\r
+\r
+ #\r
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)\r
+ #\r
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
+!if $(SECURE_BOOT_ENABLE) == TRUE\r
+ INF SecurityPkg/VariableAuthenticated/RuntimeDxe/VariableRuntimeDxe.inf\r
+ INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf\r
+!else\r
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
+!endif\r
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+\r
+ #\r
+ # Multiple Console IO support\r
+ #\r
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+ INF EmbeddedPkg/SerialDxe/SerialDxe.inf\r
+\r
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
+!if $(SECURE_BOOT_ENABLE) == TRUE\r
+ INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashAuthenticatedDxe.inf\r
+!else\r
+ INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
+!endif\r
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
+\r
+ #\r
+ # FAT filesystem + GPT/MBR partitioning\r
+ #\r
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+ INF FatBinPkg/EnhancedFatDxe/Fat.inf\r
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+\r
+ #\r
+ # Platform Driver\r
+ #\r
+ INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf\r
+ INF OvmfPkg/VirtioNetDxe/VirtioNet.inf\r
+ INF OvmfPkg/VirtioScsiDxe/VirtioScsi.inf\r
+\r
+ #\r
+ # UEFI application (Shell Embedded Boot Loader)\r
+ #\r
+ INF ShellPkg/Application/Shell/Shell.inf\r
+\r
+ #\r
+ # Bds\r
+ #\r
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+!ifdef INTEL_BDS\r
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf\r
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
+ INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf\r
+!else\r
+ INF ArmPlatformPkg/Bds/Bds.inf\r
+!endif\r
+\r
+ #\r
+ # Networking stack\r
+ #\r
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf\r
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf\r
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf\r
+ INF MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf\r
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf\r
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf\r
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf\r
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf\r
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf\r
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf\r
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf\r
+ INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf\r
+\r
+ #\r
+ # SCSI Bus and Disk Driver\r
+ #\r
+ INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf\r
+ INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf\r
+\r
+ #\r
+ # ACPI Support\r
+ #\r
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf\r
+ INF OvmfPkg/AcpiPlatformDxe/QemuFwCfgAcpiPlatformDxe.inf\r
+\r
+ #\r
+ # PCI support\r
+ #\r
+ INF ArmVirtPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf\r
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf\r
+ INF OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf\r
+\r
+ #\r
+ # Video support\r
+ #\r
+ INF OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf\r
+ INF OvmfPkg/PlatformDxe/Platform.inf\r
+\r
+ #\r
+ # USB Support\r
+ #\r
+ INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf\r
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf\r
+ INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf\r
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf\r
+ INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf\r
+\r
+!ifdef INTEL_BDS\r
+ #\r
+ # TianoCore logo (splash screen)\r
+ #\r
+ FILE FREEFORM = PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile) {\r
+ SECTION RAW = MdeModulePkg/Logo/Logo.bmp\r
+ }\r
+!endif\r
+\r
+[FV.FVMAIN_COMPACT]\r
+FvAlignment = 16\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+ APRIORI PEI {\r
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
+ }\r
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf\r
+ INF MdeModulePkg/Core/Pei/PeiMain.inf\r
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf\r
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf\r
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf\r
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
+!if $(SECURE_BOOT_ENABLE) == TRUE\r
+ INF SecurityPkg/VariableAuthenticated/Pei/VariablePei.inf\r
+!else\r
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
+!endif\r
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf\r
+\r
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {\r
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {\r
+ SECTION FV_IMAGE = FVMAIN\r
+ }\r
+ }\r
+\r
+\r
+################################################################################\r
+#\r
+# Rules are use with the [FV] section's module INF type to define\r
+# how an FFS file is created for a given INF file. The following Rule are the default\r
+# rules for the different module type. User can add the customized rules to define the\r
+# content of the FFS file.\r
+#\r
+################################################################################\r
+\r
+\r
+############################################################################\r
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #\r
+############################################################################\r
+#\r
+#[Rule.Common.DXE_DRIVER]\r
+# FILE DRIVER = $(NAMED_GUID) {\r
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+# COMPRESS PI_STD {\r
+# GUIDED {\r
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+# UI STRING="$(MODULE_NAME)" Optional\r
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+# }\r
+# }\r
+# }\r
+#\r
+############################################################################\r
+\r
+[Rule.Common.SEC]\r
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {\r
+ TE TE Align = 128 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ }\r
+\r
+[Rule.Common.PEI_CORE]\r
+ FILE PEI_CORE = $(NAMED_GUID) {\r
+ TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING ="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.PEIM]\r
+ FILE PEIM = $(NAMED_GUID) {\r
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.PEIM.TIANOCOMPRESSED]\r
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {\r
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+ }\r
+\r
+[Rule.Common.DXE_CORE]\r
+ FILE DXE_CORE = $(NAMED_GUID) {\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.UEFI_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.DXE_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.DXE_RUNTIME_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.UEFI_APPLICATION]\r
+ FILE APPLICATION = $(NAMED_GUID) {\r
+ UI STRING ="$(MODULE_NAME)" Optional\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ }\r
+\r
+[Rule.Common.UEFI_DRIVER.BINARY]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional |.depex\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.UEFI_APPLICATION.BINARY]\r
+ FILE APPLICATION = $(NAMED_GUID) {\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.USER_DEFINED.ACPITABLE]\r
+ FILE FREEFORM = $(NAMED_GUID) {\r
+ RAW ACPI |.acpi\r
+ RAW ASL |.aml\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
--- /dev/null
+#\r
+# Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
+# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ PLATFORM_NAME = ArmVirtXen\r
+ PLATFORM_GUID = d1c43be3-3373-4a06-86fb-d1cb3083a207\r
+ PLATFORM_VERSION = 0.1\r
+ DSC_SPECIFICATION = 0x00010005\r
+ OUTPUT_DIRECTORY = Build/ArmVirtXen-$(ARCH)\r
+ SUPPORTED_ARCHITECTURES = AARCH64\r
+ BUILD_TARGETS = DEBUG|RELEASE\r
+ SKUID_IDENTIFIER = DEFAULT\r
+ FLASH_DEFINITION = ArmVirtPkg/ArmVirtXen.fdf\r
+\r
+!include ArmVirtPkg/ArmVirt.dsc.inc\r
+\r
+[LibraryClasses]\r
+ SerialPortLib|OvmfPkg/Library/XenConsoleSerialPortLib/XenConsoleSerialPortLib.inf\r
+ RealTimeClockLib|ArmVirtPkg/Library/XenRealTimeClockLib/XenRealTimeClockLib.inf\r
+ XenHypercallLib|OvmfPkg/Library/XenHypercallLib/XenHypercallLib.inf\r
+\r
+[LibraryClasses.AARCH64]\r
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf\r
+ ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexAEMv8Lib/ArmCortexAEMv8Lib.inf\r
+\r
+[LibraryClasses.ARM]\r
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
+ ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf\r
+\r
+[LibraryClasses.common]\r
+ # Virtio Support\r
+ VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf\r
+ VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDeviceLib.inf\r
+\r
+ ArmPlatformLib|ArmVirtPkg/Library/ArmXenRelocatablePlatformLib/ArmXenRelocatablePlatformLib.inf\r
+ ArmPlatformSysConfigLib|ArmPlatformPkg/Library/ArmPlatformSysConfigLibNull/ArmPlatformSysConfigLibNull.inf\r
+\r
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf\r
+\r
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf\r
+ GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf\r
+ PlatformBdsLib|ArmPlatformPkg/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf\r
+ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf\r
+\r
+[LibraryClasses.common.UEFI_DRIVER]\r
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf\r
+\r
+[LibraryClasses.AARCH64.SEC]\r
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf\r
+\r
+[LibraryClasses.ARM.SEC]\r
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf\r
+\r
+[BuildOptions]\r
+ RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A15 -I$(WORKSPACE)/ArmVirtPkg/Include\r
+ GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a15 -I$(WORKSPACE)/ArmVirtPkg/Include\r
+ GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmVirtPkg/Include\r
+\r
+################################################################################\r
+#\r
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform\r
+#\r
+################################################################################\r
+\r
+[PcdsFixedAtBuild.common]\r
+ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"XEN-UEFI"\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"\r
+\r
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|1\r
+!if $(ARCH) == AARCH64\r
+ gArmTokenSpaceGuid.PcdVFPEnabled|1\r
+!endif\r
+\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000\r
+\r
+ # Size of the region used by UEFI in permanent memory (Reserved 64MB)\r
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000\r
+\r
+ #\r
+ # ARM Virtual Architectural Timer\r
+ #\r
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0\r
+\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }\r
+\r
+[PcdsPatchableInModule.common]\r
+ #\r
+ # This will be overridden in the code\r
+ #\r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x0\r
+ gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x0\r
+\r
+ gArmTokenSpaceGuid.PcdFdBaseAddress|0x0\r
+ gArmTokenSpaceGuid.PcdFvBaseAddress|0x0\r
+\r
+[PcdsDynamicDefault.common]\r
+ ## If TRUE, OvmfPkg/AcpiPlatformDxe will not wait for PCI\r
+ # enumeration to complete before installing ACPI tables.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE\r
+\r
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|0x0\r
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|0x0\r
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|0x0\r
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|0x0\r
+\r
+ #\r
+ # ARM General Interrupt Controller\r
+ #\r
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x0\r
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x0\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x0\r
+\r
+ ## PL031 RealTimeClock\r
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0\r
+\r
+ gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0\r
+ gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0\r
+ gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0\r
+ gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0\r
+ gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0\r
+ gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0\r
+ gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0\r
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x0\r
+\r
+ gArmVirtTokenSpaceGuid.PcdFwCfgSelectorAddress|0x0\r
+ gArmVirtTokenSpaceGuid.PcdFwCfgDataAddress|0x0\r
+\r
+ gArmVirtTokenSpaceGuid.PcdArmPsciMethod|0\r
+\r
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3\r
+\r
+################################################################################\r
+#\r
+# Components Section - list of all EDK II Modules needed by this Platform\r
+#\r
+################################################################################\r
+[Components.common]\r
+ #\r
+ # PEI Phase modules\r
+ #\r
+ ArmVirtPkg/PrePi/ArmVirtPrePiUniCoreRelocatable.inf {\r
+ <LibraryClasses>\r
+ ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf\r
+ LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf\r
+ PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf\r
+ HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf\r
+ PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf\r
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibPrePi.inf\r
+ MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf\r
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf\r
+ SerialPortLib|OvmfPkg/Library/XenConsoleSerialPortLib/XenConsoleSerialPortLib.inf\r
+ }\r
+\r
+ #\r
+ # DXE\r
+ #\r
+ MdeModulePkg/Core/Dxe/DxeMain.inf {\r
+ <LibraryClasses>\r
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf\r
+ }\r
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
+\r
+ #\r
+ # Architectural Protocols\r
+ #\r
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+\r
+ MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf\r
+\r
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
+\r
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+ EmbeddedPkg/SerialDxe/SerialDxe.inf\r
+\r
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+\r
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
+\r
+ #\r
+ # Platform Driver\r
+ #\r
+ ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.inf\r
+\r
+ #\r
+ # FAT filesystem + GPT/MBR partitioning\r
+ #\r
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+\r
+ #\r
+ # Bds\r
+ #\r
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf\r
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
+ IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf\r
+\r
+ OvmfPkg/XenBusDxe/XenBusDxe.inf\r
+ OvmfPkg/XenPvBlkDxe/XenPvBlkDxe.inf\r
--- /dev/null
+#\r
+# Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
+# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+\r
+################################################################################\r
+#\r
+# FD Section\r
+# The [FD] Section is made up of the definition statements and a\r
+# description of what goes into the Flash Device Image. Each FD section\r
+# defines one flash "device" image. A flash device image may be one of\r
+# the following: Removable media bootable image (like a boot floppy\r
+# image,) an Option ROM image (that would be "flashed" into an add-in\r
+# card,) a System "Flash" image (that would be burned into a system's\r
+# flash) or an Update ("Capsule") image that will be used to update and\r
+# existing system flash.\r
+#\r
+################################################################################\r
+\r
+[FD.XEN_EFI]\r
+BaseAddress = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress\r
+Size = 0x00200000|gArmTokenSpaceGuid.PcdFdSize\r
+ErasePolarity = 1\r
+\r
+# This one is tricky, it must be: BlockSize * NumBlocks = Size\r
+BlockSize = 0x00001000\r
+NumBlocks = 0x200\r
+\r
+################################################################################\r
+#\r
+# Following are lists of FD Region layout which correspond to the locations of different\r
+# images within the flash device.\r
+#\r
+# Regions must be defined in ascending order and may not overlap.\r
+#\r
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by\r
+# the pipe "|" character, followed by the size of the region, also in hex with the leading\r
+# "0x" characters. Like:\r
+# Offset|Size\r
+# PcdOffsetCName|PcdSizeCName\r
+# RegionType <FV, DATA, or FILE>\r
+#\r
+################################################################################\r
+\r
+#\r
+# Implement the Linux kernel header layout so that the Xen loader will identify\r
+# it as something bootable, and execute it with a FDT pointer in x0. This area\r
+# will be reused to store a copy of the FDT so round it up to 8 KB.\r
+#\r
+0x00000000|0x00002000\r
+DATA = {\r
+ 0x01, 0x00, 0x00, 0x10, # code0: adr x1, .\r
+ 0xff, 0x07, 0x00, 0x14, # code1: b 0x2000\r
+ 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, # text_offset: 512 KB\r
+ 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, # image_size: 2 MB\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # flags\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res2\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res3\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res4\r
+ 0x41, 0x52, 0x4d, 0x64, # magic: "ARM\x64"\r
+ 0x00, 0x00, 0x00, 0x00 # res5\r
+}\r
+\r
+0x00002000|0x001fe000\r
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize\r
+FV = FVMAIN_COMPACT\r
+\r
+\r
+################################################################################\r
+#\r
+# FV Section\r
+#\r
+# [FV] section is used to define what components or modules are placed within a flash\r
+# device file. This section also defines order the components and modules are positioned\r
+# within the image. The [FV] section consists of define statements, set statements and\r
+# module statements.\r
+#\r
+################################################################################\r
+\r
+[FV.FvMain]\r
+BlockSize = 0x40\r
+NumBlocks = 0 # This FV gets compressed so make it just big enough\r
+FvAlignment = 16 # FV alignment and FV attributes setting.\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+ APRIORI DXE {\r
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
+ INF ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.inf\r
+ }\r
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf\r
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
+ INF ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.inf\r
+\r
+ #\r
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)\r
+ #\r
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+\r
+ INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf\r
+\r
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+\r
+ #\r
+ # Multiple Console IO support\r
+ #\r
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+ INF EmbeddedPkg/SerialDxe/SerialDxe.inf\r
+\r
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
+\r
+ #\r
+ # FAT filesystem + GPT/MBR partitioning\r
+ #\r
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+ INF FatBinPkg/EnhancedFatDxe/Fat.inf\r
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+\r
+ #\r
+ # UEFI application (Shell Embedded Boot Loader)\r
+ #\r
+ INF ShellPkg/Application/Shell/Shell.inf\r
+\r
+ #\r
+ # Bds\r
+ #\r
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf\r
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
+ INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf\r
+\r
+ INF OvmfPkg/XenBusDxe/XenBusDxe.inf\r
+ INF OvmfPkg/XenPvBlkDxe/XenPvBlkDxe.inf\r
+\r
+[FV.FVMAIN_COMPACT]\r
+FvAlignment = 16\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+ INF ArmVirtPkg/PrePi/ArmVirtPrePiUniCoreRelocatable.inf\r
+\r
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {\r
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {\r
+ SECTION FV_IMAGE = FVMAIN\r
+ }\r
+ }\r
+\r
+\r
+################################################################################\r
+#\r
+# Rules are use with the [FV] section's module INF type to define\r
+# how an FFS file is created for a given INF file. The following Rule are the default\r
+# rules for the different module type. User can add the customized rules to define the\r
+# content of the FFS file.\r
+#\r
+################################################################################\r
+\r
+\r
+############################################################################\r
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #\r
+############################################################################\r
+#\r
+#[Rule.Common.DXE_DRIVER]\r
+# FILE DRIVER = $(NAMED_GUID) {\r
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+# COMPRESS PI_STD {\r
+# GUIDED {\r
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+# UI STRING="$(MODULE_NAME)" Optional\r
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+# }\r
+# }\r
+# }\r
+#\r
+############################################################################\r
+\r
+[Rule.Common.SEC]\r
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {\r
+ TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ }\r
+\r
+[Rule.Common.PEI_CORE]\r
+ FILE PEI_CORE = $(NAMED_GUID) {\r
+ TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING ="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.PEIM]\r
+ FILE PEIM = $(NAMED_GUID) {\r
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.PEIM.TIANOCOMPRESSED]\r
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {\r
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+ }\r
+\r
+[Rule.Common.DXE_CORE]\r
+ FILE DXE_CORE = $(NAMED_GUID) {\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.UEFI_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.DXE_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.DXE_RUNTIME_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.UEFI_APPLICATION]\r
+ FILE APPLICATION = $(NAMED_GUID) {\r
+ UI STRING ="$(MODULE_NAME)" Optional\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ }\r
+\r
+[Rule.Common.UEFI_DRIVER.BINARY]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional |.depex\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.UEFI_APPLICATION.BINARY]\r
+ FILE APPLICATION = $(NAMED_GUID) {\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.USER_DEFINED.ACPITABLE]\r
+ FILE FREEFORM = $(NAMED_GUID) {\r
+ RAW ACPI |.acpi\r
+ RAW ASL |.aml\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
--- /dev/null
+/** @file\r
+* Header defining platform constants (Base addresses, sizes, flags)\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* Copyright (c) 2014, Linaro Limited\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#ifndef __PLATFORM_H__\r
+#define __PLATFORM_H__\r
+\r
+//\r
+// We don't care about this value, but the PL031 driver depends on the macro\r
+// to exist: it will pass it on to our ArmPlatformSysConfigLib:ConfigGet()\r
+// function, which just returns EFI_UNSUPPORTED.\r
+//\r
+#define SYS_CFG_RTC 0x0\r
+\r
+#define QEMU_NOR_BLOCK_SIZE SIZE_256KB\r
+#define QEMU_NOR0_BASE 0x0\r
+#define QEMU_NOR0_SIZE SIZE_64MB\r
+#define QEMU_NOR1_BASE 0x04000000\r
+#define QEMU_NOR1_SIZE SIZE_64MB\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ GUID for the HOB that caches the base address of the PL011 serial port, for\r
+ when PCD access is not available.\r
+\r
+ Copyright (C) 2014, Red Hat, Inc.\r
+\r
+ This program and the accompanying materials are licensed and made available\r
+ under the terms and conditions of the BSD License that accompanies this\r
+ distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __EARLY_PL011_BASE_ADDRESS_H__\r
+#define __EARLY_PL011_BASE_ADDRESS_H__\r
+\r
+#define EARLY_PL011_BASE_ADDRESS_GUID { \\r
+ 0xB199DEA9, 0xFD5C, 0x4A84, \\r
+ { 0x80, 0x82, 0x2F, 0x41, 0x70, 0x78, 0x03, 0x05 } \\r
+ }\r
+\r
+extern EFI_GUID gEarlyPL011BaseAddressGuid;\r
+\r
+#endif\r
--- /dev/null
+## @file\r
+# Instance of HOB Library using HOB list from EFI Configuration Table, with\r
+# DebugLib dependency removed\r
+#\r
+# HOB Library implementation that retrieves the HOB List\r
+# from the System Configuration Table in the EFI System Table.\r
+#\r
+# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmVirtDxeHobLib\r
+ FILE_GUID = 3CD90EEC-EBF3-425D-AAE8-B16215AC4F50\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = HobLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER SMM_CORE DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
+ CONSTRUCTOR = HobLibConstructor\r
+\r
+[Sources]\r
+ HobLib.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseMemoryLib\r
+\r
+[Guids]\r
+ gEfiHobListGuid ## CONSUMES ## SystemTable\r
--- /dev/null
+/** @file\r
+ HOB Library implemenation for Dxe Phase with DebugLib dependency removed\r
+\r
+Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#define ASSERT(Expression) \\r
+ do { \\r
+ if (!(Expression)) { \\r
+ CpuDeadLoop (); \\r
+ } \\r
+ } while (FALSE)\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Guid/HobList.h>\r
+\r
+#include <Library/HobLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+\r
+VOID *mHobList = NULL;\r
+\r
+/**\r
+ The constructor function caches the pointer to HOB list.\r
+\r
+ The constructor function gets the start address of HOB list from system configuration table.\r
+\r
+ @param ImageHandle The firmware allocated handle for the EFI image.\r
+ @param SystemTable A pointer to the EFI System Table.\r
+\r
+ @retval EFI_SUCCESS The constructor successfully gets HobList.\r
+ @retval Other value The constructor can't get HobList.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+HobLibConstructor (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ UINTN Index;\r
+\r
+ for (Index = 0; Index < SystemTable->NumberOfTableEntries; Index++) {\r
+ if (CompareGuid (&gEfiHobListGuid, &(SystemTable->ConfigurationTable[Index].VendorGuid))) {\r
+ mHobList = SystemTable->ConfigurationTable[Index].VendorTable;\r
+ return EFI_SUCCESS;\r
+ }\r
+ }\r
+\r
+ return EFI_NOT_FOUND;\r
+}\r
+\r
+/**\r
+ Returns the pointer to the HOB list.\r
+\r
+ This function returns the pointer to first HOB in the list.\r
+ For PEI phase, the PEI service GetHobList() can be used to retrieve the pointer\r
+ to the HOB list. For the DXE phase, the HOB list pointer can be retrieved through\r
+ the EFI System Table by looking up theHOB list GUID in the System Configuration Table.\r
+ Since the System Configuration Table does not exist that the time the DXE Core is\r
+ launched, the DXE Core uses a global variable from the DXE Core Entry Point Library\r
+ to manage the pointer to the HOB list.\r
+\r
+ If the pointer to the HOB list is NULL, then ASSERT().\r
+\r
+ @return The pointer to the HOB list.\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+GetHobList (\r
+ VOID\r
+ )\r
+{\r
+ ASSERT (mHobList != NULL);\r
+ return mHobList;\r
+}\r
+\r
+/**\r
+ Returns the next instance of a HOB type from the starting HOB.\r
+\r
+ This function searches the first instance of a HOB type from the starting HOB pointer.\r
+ If there does not exist such HOB type from the starting HOB pointer, it will return NULL.\r
+ In contrast with macro GET_NEXT_HOB(), this function does not skip the starting HOB pointer\r
+ unconditionally: it returns HobStart back if HobStart itself meets the requirement;\r
+ caller is required to use GET_NEXT_HOB() if it wishes to skip current HobStart.\r
+\r
+ If HobStart is NULL, then ASSERT().\r
+\r
+ @param Type The HOB type to return.\r
+ @param HobStart The starting HOB pointer to search from.\r
+\r
+ @return The next instance of a HOB type from the starting HOB.\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+GetNextHob (\r
+ IN UINT16 Type,\r
+ IN CONST VOID *HobStart\r
+ )\r
+{\r
+ EFI_PEI_HOB_POINTERS Hob;\r
+\r
+ ASSERT (HobStart != NULL);\r
+\r
+ Hob.Raw = (UINT8 *) HobStart;\r
+ //\r
+ // Parse the HOB list until end of list or matching type is found.\r
+ //\r
+ while (!END_OF_HOB_LIST (Hob)) {\r
+ if (Hob.Header->HobType == Type) {\r
+ return Hob.Raw;\r
+ }\r
+ Hob.Raw = GET_NEXT_HOB (Hob);\r
+ }\r
+ return NULL;\r
+}\r
+\r
+/**\r
+ Returns the first instance of a HOB type among the whole HOB list.\r
+\r
+ This function searches the first instance of a HOB type among the whole HOB list.\r
+ If there does not exist such HOB type in the HOB list, it will return NULL.\r
+\r
+ If the pointer to the HOB list is NULL, then ASSERT().\r
+\r
+ @param Type The HOB type to return.\r
+\r
+ @return The next instance of a HOB type from the starting HOB.\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+GetFirstHob (\r
+ IN UINT16 Type\r
+ )\r
+{\r
+ VOID *HobList;\r
+\r
+ HobList = GetHobList ();\r
+ return GetNextHob (Type, HobList);\r
+}\r
+\r
+/**\r
+ Returns the next instance of the matched GUID HOB from the starting HOB.\r
+\r
+ This function searches the first instance of a HOB from the starting HOB pointer.\r
+ Such HOB should satisfy two conditions:\r
+ its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to the input Guid.\r
+ If there does not exist such HOB from the starting HOB pointer, it will return NULL.\r
+ Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_SIZE ()\r
+ to extract the data section and its size information, respectively.\r
+ In contrast with macro GET_NEXT_HOB(), this function does not skip the starting HOB pointer\r
+ unconditionally: it returns HobStart back if HobStart itself meets the requirement;\r
+ caller is required to use GET_NEXT_HOB() if it wishes to skip current HobStart.\r
+\r
+ If Guid is NULL, then ASSERT().\r
+ If HobStart is NULL, then ASSERT().\r
+\r
+ @param Guid The GUID to match with in the HOB list.\r
+ @param HobStart A pointer to a Guid.\r
+\r
+ @return The next instance of the matched GUID HOB from the starting HOB.\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+GetNextGuidHob (\r
+ IN CONST EFI_GUID *Guid,\r
+ IN CONST VOID *HobStart\r
+ )\r
+{\r
+ EFI_PEI_HOB_POINTERS GuidHob;\r
+\r
+ GuidHob.Raw = (UINT8 *) HobStart;\r
+ while ((GuidHob.Raw = GetNextHob (EFI_HOB_TYPE_GUID_EXTENSION, GuidHob.Raw)) != NULL) {\r
+ if (CompareGuid (Guid, &GuidHob.Guid->Name)) {\r
+ break;\r
+ }\r
+ GuidHob.Raw = GET_NEXT_HOB (GuidHob);\r
+ }\r
+ return GuidHob.Raw;\r
+}\r
+\r
+/**\r
+ Returns the first instance of the matched GUID HOB among the whole HOB list.\r
+\r
+ This function searches the first instance of a HOB among the whole HOB list.\r
+ Such HOB should satisfy two conditions:\r
+ its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to the input Guid.\r
+ If there does not exist such HOB from the starting HOB pointer, it will return NULL.\r
+ Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_SIZE ()\r
+ to extract the data section and its size information, respectively.\r
+\r
+ If the pointer to the HOB list is NULL, then ASSERT().\r
+ If Guid is NULL, then ASSERT().\r
+\r
+ @param Guid The GUID to match with in the HOB list.\r
+\r
+ @return The first instance of the matched GUID HOB among the whole HOB list.\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+GetFirstGuidHob (\r
+ IN CONST EFI_GUID *Guid\r
+ )\r
+{\r
+ VOID *HobList;\r
+\r
+ HobList = GetHobList ();\r
+ return GetNextGuidHob (Guid, HobList);\r
+}\r
+\r
+/**\r
+ Get the system boot mode from the HOB list.\r
+\r
+ This function returns the system boot mode information from the\r
+ PHIT HOB in HOB list.\r
+\r
+ If the pointer to the HOB list is NULL, then ASSERT().\r
+\r
+ @param VOID\r
+\r
+ @return The Boot Mode.\r
+\r
+**/\r
+EFI_BOOT_MODE\r
+EFIAPI\r
+GetBootModeHob (\r
+ VOID\r
+ )\r
+{\r
+ EFI_HOB_HANDOFF_INFO_TABLE *HandOffHob;\r
+\r
+ HandOffHob = (EFI_HOB_HANDOFF_INFO_TABLE *) GetHobList ();\r
+\r
+ return HandOffHob->BootMode;\r
+}\r
+\r
+/**\r
+ Builds a HOB for a loaded PE32 module.\r
+\r
+ This function builds a HOB for a loaded PE32 module.\r
+ It can only be invoked during PEI phase;\r
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
+\r
+ If ModuleName is NULL, then ASSERT().\r
+ If there is no additional space for HOB creation, then ASSERT().\r
+\r
+ @param ModuleName The GUID File Name of the module.\r
+ @param MemoryAllocationModule The 64 bit physical address of the module.\r
+ @param ModuleLength The length of the module in bytes.\r
+ @param EntryPoint The 64 bit physical address of the module entry point.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+BuildModuleHob (\r
+ IN CONST EFI_GUID *ModuleName,\r
+ IN EFI_PHYSICAL_ADDRESS MemoryAllocationModule,\r
+ IN UINT64 ModuleLength,\r
+ IN EFI_PHYSICAL_ADDRESS EntryPoint\r
+ )\r
+{\r
+ //\r
+ // PEI HOB is read only for DXE phase\r
+ //\r
+ ASSERT (FALSE);\r
+}\r
+\r
+/**\r
+ Builds a HOB that describes a chunk of system memory.\r
+\r
+ This function builds a HOB that describes a chunk of system memory.\r
+ It can only be invoked during PEI phase;\r
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
+\r
+ If there is no additional space for HOB creation, then ASSERT().\r
+\r
+ @param ResourceType The type of resource described by this HOB.\r
+ @param ResourceAttribute The resource attributes of the memory described by this HOB.\r
+ @param PhysicalStart The 64 bit physical address of memory described by this HOB.\r
+ @param NumberOfBytes The length of the memory described by this HOB in bytes.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+BuildResourceDescriptorHob (\r
+ IN EFI_RESOURCE_TYPE ResourceType,\r
+ IN EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute,\r
+ IN EFI_PHYSICAL_ADDRESS PhysicalStart,\r
+ IN UINT64 NumberOfBytes\r
+ )\r
+{\r
+ //\r
+ // PEI HOB is read only for DXE phase\r
+ //\r
+ ASSERT (FALSE);\r
+}\r
+\r
+/**\r
+ Builds a customized HOB tagged with a GUID for identification and returns\r
+ the start address of GUID HOB data.\r
+\r
+ This function builds a customized HOB tagged with a GUID for identification\r
+ and returns the start address of GUID HOB data so that caller can fill the customized data.\r
+ The HOB Header and Name field is already stripped.\r
+ It can only be invoked during PEI phase;\r
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
+\r
+ If Guid is NULL, then ASSERT().\r
+ If there is no additional space for HOB creation, then ASSERT().\r
+ If DataLength > (0xFFF8 - sizeof (EFI_HOB_GUID_TYPE)), then ASSERT().\r
+ HobLength is UINT16 and multiples of 8 bytes, so the max HobLength is 0xFFF8.\r
+\r
+ @param Guid The GUID to tag the customized HOB.\r
+ @param DataLength The size of the data payload for the GUID HOB.\r
+\r
+ @retval NULL The GUID HOB could not be allocated.\r
+ @retval others The start address of GUID HOB data.\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+BuildGuidHob (\r
+ IN CONST EFI_GUID *Guid,\r
+ IN UINTN DataLength\r
+ )\r
+{\r
+ //\r
+ // PEI HOB is read only for DXE phase\r
+ //\r
+ ASSERT (FALSE);\r
+ return NULL;\r
+}\r
+\r
+/**\r
+ Builds a customized HOB tagged with a GUID for identification, copies the input data to the HOB\r
+ data field, and returns the start address of the GUID HOB data.\r
+\r
+ This function builds a customized HOB tagged with a GUID for identification and copies the input\r
+ data to the HOB data field and returns the start address of the GUID HOB data. It can only be\r
+ invoked during PEI phase; for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
+ The HOB Header and Name field is already stripped.\r
+ It can only be invoked during PEI phase;\r
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
+\r
+ If Guid is NULL, then ASSERT().\r
+ If Data is NULL and DataLength > 0, then ASSERT().\r
+ If there is no additional space for HOB creation, then ASSERT().\r
+ If DataLength > (0xFFF8 - sizeof (EFI_HOB_GUID_TYPE)), then ASSERT().\r
+ HobLength is UINT16 and multiples of 8 bytes, so the max HobLength is 0xFFF8.\r
+\r
+ @param Guid The GUID to tag the customized HOB.\r
+ @param Data The data to be copied into the data field of the GUID HOB.\r
+ @param DataLength The size of the data payload for the GUID HOB.\r
+\r
+ @retval NULL The GUID HOB could not be allocated.\r
+ @retval others The start address of GUID HOB data.\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+BuildGuidDataHob (\r
+ IN CONST EFI_GUID *Guid,\r
+ IN VOID *Data,\r
+ IN UINTN DataLength\r
+ )\r
+{\r
+ //\r
+ // PEI HOB is read only for DXE phase\r
+ //\r
+ ASSERT (FALSE);\r
+ return NULL;\r
+}\r
+\r
+/**\r
+ Builds a Firmware Volume HOB.\r
+\r
+ This function builds a Firmware Volume HOB.\r
+ It can only be invoked during PEI phase;\r
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
+\r
+ If there is no additional space for HOB creation, then ASSERT().\r
+\r
+ @param BaseAddress The base address of the Firmware Volume.\r
+ @param Length The size of the Firmware Volume in bytes.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+BuildFvHob (\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
+ )\r
+{\r
+ //\r
+ // PEI HOB is read only for DXE phase\r
+ //\r
+ ASSERT (FALSE);\r
+}\r
+\r
+/**\r
+ Builds a EFI_HOB_TYPE_FV2 HOB.\r
+\r
+ This function builds a EFI_HOB_TYPE_FV2 HOB.\r
+ It can only be invoked during PEI phase;\r
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
+\r
+ If there is no additional space for HOB creation, then ASSERT().\r
+\r
+ @param BaseAddress The base address of the Firmware Volume.\r
+ @param Length The size of the Firmware Volume in bytes.\r
+ @param FvName The name of the Firmware Volume.\r
+ @param FileName The name of the file.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+BuildFv2Hob (\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN CONST EFI_GUID *FvName,\r
+ IN CONST EFI_GUID *FileName\r
+ )\r
+{\r
+ ASSERT (FALSE);\r
+}\r
+\r
+\r
+/**\r
+ Builds a Capsule Volume HOB.\r
+\r
+ This function builds a Capsule Volume HOB.\r
+ It can only be invoked during PEI phase;\r
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
+\r
+ If the platform does not support Capsule Volume HOBs, then ASSERT().\r
+ If there is no additional space for HOB creation, then ASSERT().\r
+\r
+ @param BaseAddress The base address of the Capsule Volume.\r
+ @param Length The size of the Capsule Volume in bytes.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+BuildCvHob (\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
+ )\r
+{\r
+ //\r
+ // PEI HOB is read only for DXE phase\r
+ //\r
+ ASSERT (FALSE);\r
+}\r
+\r
+/**\r
+ Builds a HOB for the CPU.\r
+\r
+ This function builds a HOB for the CPU.\r
+ It can only be invoked during PEI phase;\r
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
+\r
+ If there is no additional space for HOB creation, then ASSERT().\r
+\r
+ @param SizeOfMemorySpace The maximum physical memory addressability of the processor.\r
+ @param SizeOfIoSpace The maximum physical I/O addressability of the processor.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+BuildCpuHob (\r
+ IN UINT8 SizeOfMemorySpace,\r
+ IN UINT8 SizeOfIoSpace\r
+ )\r
+{\r
+ //\r
+ // PEI HOB is read only for DXE phase\r
+ //\r
+ ASSERT (FALSE);\r
+}\r
+\r
+/**\r
+ Builds a HOB for the Stack.\r
+\r
+ This function builds a HOB for the stack.\r
+ It can only be invoked during PEI phase;\r
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
+\r
+ If there is no additional space for HOB creation, then ASSERT().\r
+\r
+ @param BaseAddress The 64 bit physical address of the Stack.\r
+ @param Length The length of the stack in bytes.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+BuildStackHob (\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
+ )\r
+{\r
+ //\r
+ // PEI HOB is read only for DXE phase\r
+ //\r
+ ASSERT (FALSE);\r
+}\r
+\r
+/**\r
+ Builds a HOB for the BSP store.\r
+\r
+ This function builds a HOB for BSP store.\r
+ It can only be invoked during PEI phase;\r
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
+\r
+ If there is no additional space for HOB creation, then ASSERT().\r
+\r
+ @param BaseAddress The 64 bit physical address of the BSP.\r
+ @param Length The length of the BSP store in bytes.\r
+ @param MemoryType Type of memory allocated by this HOB.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+BuildBspStoreHob (\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN EFI_MEMORY_TYPE MemoryType\r
+ )\r
+{\r
+ //\r
+ // PEI HOB is read only for DXE phase\r
+ //\r
+ ASSERT (FALSE);\r
+}\r
+\r
+/**\r
+ Builds a HOB for the memory allocation.\r
+\r
+ This function builds a HOB for the memory allocation.\r
+ It can only be invoked during PEI phase;\r
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.\r
+\r
+ If there is no additional space for HOB creation, then ASSERT().\r
+\r
+ @param BaseAddress The 64 bit physical address of the memory.\r
+ @param Length The length of the memory allocation in bytes.\r
+ @param MemoryType Type of memory allocated by this HOB.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+BuildMemoryAllocationHob (\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN EFI_MEMORY_TYPE MemoryType\r
+ )\r
+{\r
+ //\r
+ // PEI HOB is read only for DXE phase\r
+ //\r
+ ASSERT (FALSE);\r
+}\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
+* Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/CacheMaintenanceLib.h>\r
+\r
+VOID\r
+BuildMemoryTypeInformationHob (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+InitMmu (\r
+ VOID\r
+ )\r
+{\r
+ ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;\r
+ VOID *TranslationTableBase;\r
+ UINTN TranslationTableSize;\r
+ RETURN_STATUS Status;\r
+\r
+ // Get Virtual Memory Map from the Platform Library\r
+ ArmPlatformGetVirtualMemoryMap (&MemoryTable);\r
+\r
+ //Note: Because we called PeiServicesInstallPeiMemory() before to call InitMmu() the MMU Page Table resides in\r
+ // DRAM (even at the top of DRAM as it is the first permanent memory allocation)\r
+ Status = ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_ERROR, "Error: Failed to enable MMU\n"));\r
+ }\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+MemoryPeim (\r
+ IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,\r
+ IN UINT64 UefiMemorySize\r
+ )\r
+{\r
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;\r
+\r
+ // Ensure PcdSystemMemorySize has been set\r
+ ASSERT (PcdGet64 (PcdSystemMemorySize) != 0);\r
+\r
+ //\r
+ // Now, the permanent memory has been installed, we can call AllocatePages()\r
+ //\r
+ ResourceAttributes = (\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED\r
+ );\r
+\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_SYSTEM_MEMORY,\r
+ ResourceAttributes,\r
+ PcdGet64 (PcdSystemMemoryBase),\r
+ PcdGet64 (PcdSystemMemorySize)\r
+ );\r
+\r
+ //\r
+ // When running under virtualization, the PI/UEFI memory region may be\r
+ // clean but not invalidated in system caches or in lower level caches\r
+ // on other CPUs. So invalidate the region by virtual address, to ensure\r
+ // that the contents we put there with the caches and MMU off will still\r
+ // be visible after turning them on.\r
+ //\r
+ InvalidateDataCacheRange ((VOID*)(UINTN)UefiMemoryBase, UefiMemorySize);\r
+\r
+ // Build Memory Allocation Hob\r
+ InitMmu ();\r
+\r
+ if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) {\r
+ // Optional feature that helps prevent EFI memory map fragmentation.\r
+ BuildMemoryTypeInformationHob ();\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+#/** @file\r
+#\r
+# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>\r
+# Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmVirtMemoryInitPeiLib\r
+ FILE_GUID = 021b6156-3cc8-4e99-85ee-13d8a871edf2\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = MemoryInitPeiLib\r
+\r
+[Sources]\r
+ ArmVirtMemoryInitPeiLib.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ DebugLib\r
+ HobLib\r
+ ArmLib\r
+ ArmPlatformLib\r
+ CacheMaintenanceLib\r
+\r
+[Guids]\r
+ gEfiMemoryTypeInformationGuid\r
+\r
+[FeaturePcd]\r
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob\r
+\r
+[FixedPcd]\r
+ gArmTokenSpaceGuid.PcdFdSize\r
+\r
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize\r
+\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData\r
+\r
+[Pcd]\r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize\r
+ gArmTokenSpaceGuid.PcdFdBaseAddress\r
+\r
+[Depex]\r
+ TRUE\r
--- /dev/null
+#\r
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+\r
+#include <AsmMacroIoLibV8.h>\r
+#include <Base.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <AutoGen.h>\r
+\r
+.text\r
+.align 2\r
+\r
+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)\r
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r
+GCC_ASM_EXPORT(ArmGetPhysAddrTop)\r
+\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdCoreCount)\r
+\r
+ASM_PFX(ArmPlatformPeiBootAction):\r
+ ret\r
+\r
+//UINTN\r
+//ArmPlatformGetPrimaryCoreMpId (\r
+// VOID\r
+// );\r
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, x0)\r
+ ldrh w0, [x0]\r
+ ret\r
+\r
+//UINTN\r
+//ArmPlatformIsPrimaryCore (\r
+// IN UINTN MpId\r
+// );\r
+ASM_PFX(ArmPlatformIsPrimaryCore):\r
+ mov x0, #1\r
+ ret\r
+\r
+//UINTN\r
+//ArmPlatformGetCorePosition (\r
+// IN UINTN MpId\r
+// );\r
+// With this function: CorePos = (ClusterId * 4) + CoreId\r
+ASM_PFX(ArmPlatformGetCorePosition):\r
+ and x1, x0, #ARM_CORE_MASK\r
+ and x0, x0, #ARM_CLUSTER_MASK\r
+ add x0, x1, x0, LSR #6\r
+ ret\r
+\r
+//EFI_PHYSICAL_ADDRESS\r
+//GetPhysAddrTop (\r
+// VOID\r
+// );\r
+ASM_PFX(ArmGetPhysAddrTop):\r
+ mrs x0, id_aa64mmfr0_el1\r
+ adr x1, .LPARanges\r
+ and x0, x0, #7\r
+ ldrb w1, [x1, x0]\r
+ mov x0, #1\r
+ lsl x0, x0, x1\r
+ ret\r
+\r
+//\r
+// Bits 0..2 of the AA64MFR0_EL1 system register encode the size of the\r
+// physical address space support on this CPU:\r
+// 0 == 32 bits, 1 == 36 bits, etc etc\r
+// 6 and 7 are reserved\r
+//\r
+.LPARanges:\r
+ .byte 32, 36, 40, 42, 44, 48, -1, -1\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
--- /dev/null
+#\r
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <AutoGen.h>\r
+\r
+.text\r
+.align 2\r
+\r
+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)\r
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r
+GCC_ASM_EXPORT(ArmGetPhysAddrTop)\r
+\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdCoreCount)\r
+\r
+ASM_PFX(ArmPlatformPeiBootAction):\r
+ bx lr\r
+\r
+//UINTN\r
+//ArmPlatformGetPrimaryCoreMpId (\r
+// VOID\r
+// );\r
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)\r
+ ldr r0, [r0]\r
+ bx lr\r
+\r
+//UINTN\r
+//ArmPlatformIsPrimaryCore (\r
+// IN UINTN MpId\r
+// );\r
+ASM_PFX(ArmPlatformIsPrimaryCore):\r
+ mov r0, #1\r
+ bx lr\r
+\r
+//UINTN\r
+//ArmPlatformGetCorePosition (\r
+// IN UINTN MpId\r
+// );\r
+// With this function: CorePos = (ClusterId * 4) + CoreId\r
+ASM_PFX(ArmPlatformGetCorePosition):\r
+ and r1, r0, #ARM_CORE_MASK\r
+ and r0, r0, #ARM_CLUSTER_MASK\r
+ add r0, r1, r0, LSR #6\r
+ bx lr\r
+\r
+//EFI_PHYSICAL_ADDRESS\r
+//GetPhysAddrTop (\r
+// VOID\r
+// );\r
+ASM_PFX(ArmGetPhysAddrTop):\r
+ mov r0, #0x00000000\r
+ mov r1, #0x10000\r
+ bx lr\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
--- /dev/null
+//\r
+// Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
+// Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <AutoGen.h>\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+\r
+ EXPORT ArmPlatformPeiBootAction\r
+ EXPORT ArmPlatformIsPrimaryCore\r
+ EXPORT ArmPlatformGetPrimaryCoreMpId\r
+ EXPORT ArmPlatformGetCorePosition\r
+ EXPORT ArmGetPhysAddrTop\r
+\r
+ IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCore\r
+ IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCoreMask\r
+ IMPORT _gPcd_FixedAtBuild_PcdCoreCount\r
+\r
+ AREA VirtHelper, CODE, READONLY\r
+\r
+ArmPlatformPeiBootAction FUNCTION\r
+ bx lr\r
+ ENDFUNC\r
+\r
+//UINTN\r
+//ArmPlatformGetPrimaryCoreMpId (\r
+// VOID\r
+// );\r
+ArmPlatformGetPrimaryCoreMpId FUNCTION\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)\r
+ ldr r0, [r0]\r
+ bx lr\r
+ ENDFUNC\r
+\r
+//UINTN\r
+//ArmPlatformIsPrimaryCore (\r
+// IN UINTN MpId\r
+// );\r
+ArmPlatformIsPrimaryCore FUNCTION\r
+ mov r0, #1\r
+ bx lr\r
+ ENDFUNC\r
+\r
+//UINTN\r
+//ArmPlatformGetCorePosition (\r
+// IN UINTN MpId\r
+// );\r
+// With this function: CorePos = (ClusterId * 4) + CoreId\r
+ArmPlatformGetCorePosition FUNCTION\r
+ and r1, r0, #ARM_CORE_MASK\r
+ and r0, r0, #ARM_CLUSTER_MASK\r
+ add r0, r1, r0, LSR #6\r
+ bx lr\r
+ ENDFUNC\r
+\r
+//EFI_PHYSICAL_ADDRESS\r
+//GetPhysAddrTop (\r
+// VOID\r
+// );\r
+ArmGetPhysAddrTop FUNCTION\r
+ mov r0, #0x00000000\r
+ mov r1, #0x10000\r
+ bx lr\r
+ ENDFUNC\r
+\r
+ END\r
--- /dev/null
+#/* @file\r
+# Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
+# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#*/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmVirtPlatformLib\r
+ FILE_GUID = 00214cc1-06d1-45fe-9700-dca5726ad7bf\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = ArmPlatformLib|SEC PEIM\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+ ArmVirtPkg/ArmVirtPkg.dec\r
+\r
+[LibraryClasses]\r
+ IoLib\r
+ MemoryAllocationLib\r
+ ArmLib\r
+ PrintLib\r
+ FdtLib\r
+\r
+[Sources.common]\r
+ Virt.c\r
+ VirtMem.c\r
+\r
+[Sources.AARCH64]\r
+ AARCH64/VirtHelper.S\r
+\r
+[Sources.ARM]\r
+ ARM/VirtHelper.S | GCC\r
+ ARM/VirtHelper.asm | RVCT\r
+\r
+[FeaturePcd]\r
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec\r
+\r
+[Pcd]\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize\r
+\r
+[FixedPcd]\r
+ gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress\r
+ gArmPlatformTokenSpaceGuid.PcdCoreCount\r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCore\r
+ gArmTokenSpaceGuid.PcdFdBaseAddress\r
+ gArmTokenSpaceGuid.PcdFdSize\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+* Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+* Copyright (c) 2014, Red Hat, Inc.\r
+*\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Library/IoLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <ArmPlatform.h>\r
+#include <libfdt.h>\r
+#include <Pi/PiBootMode.h>\r
+#include <Uefi/UefiBaseType.h>\r
+#include <Uefi/UefiMultiPhase.h>\r
+\r
+/**\r
+ Return the current Boot Mode\r
+\r
+ This function returns the boot reason on the platform\r
+\r
+ @return Return the current Boot Mode of the platform\r
+\r
+**/\r
+EFI_BOOT_MODE\r
+ArmPlatformGetBootMode (\r
+ VOID\r
+ )\r
+{\r
+ return BOOT_WITH_FULL_CONFIGURATION;\r
+}\r
+\r
+/**\r
+ This function is called by PrePeiCore, in the SEC phase.\r
+**/\r
+RETURN_STATUS\r
+ArmPlatformInitialize (\r
+ IN UINTN MpId\r
+ )\r
+{\r
+ //\r
+ // We are relying on ArmPlatformInitializeSystemMemory () being called from\r
+ // InitializeMemory (), which only occurs if the following feature is disabled\r
+ //\r
+ ASSERT (!FeaturePcdGet (PcdSystemMemoryInitializeInSec));\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+ Initialize the system (or sometimes called permanent) memory\r
+\r
+ This memory is generally represented by the DRAM.\r
+\r
+ This function is called from InitializeMemory() in MemoryInitPeim, in the PEI\r
+ phase.\r
+**/\r
+VOID\r
+ArmPlatformInitializeSystemMemory (\r
+ VOID\r
+ )\r
+{\r
+ VOID *DeviceTreeBase;\r
+ INT32 Node, Prev;\r
+ UINT64 NewBase;\r
+ UINT64 NewSize;\r
+ CONST CHAR8 *Type;\r
+ INT32 Len;\r
+ CONST UINT64 *RegProp;\r
+\r
+ NewBase = 0;\r
+ NewSize = 0;\r
+\r
+ DeviceTreeBase = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeInitialBaseAddress);\r
+ ASSERT (DeviceTreeBase != NULL);\r
+\r
+ //\r
+ // Make sure we have a valid device tree blob\r
+ //\r
+ ASSERT (fdt_check_header (DeviceTreeBase) == 0);\r
+\r
+ //\r
+ // Look for a memory node\r
+ //\r
+ for (Prev = 0;; Prev = Node) {\r
+ Node = fdt_next_node (DeviceTreeBase, Prev, NULL);\r
+ if (Node < 0) {\r
+ break;\r
+ }\r
+\r
+ //\r
+ // Check for memory node\r
+ //\r
+ Type = fdt_getprop (DeviceTreeBase, Node, "device_type", &Len);\r
+ if (Type && AsciiStrnCmp (Type, "memory", Len) == 0) {\r
+ //\r
+ // Get the 'reg' property of this node. For now, we will assume\r
+ // two 8 byte quantities for base and size, respectively.\r
+ //\r
+ RegProp = fdt_getprop (DeviceTreeBase, Node, "reg", &Len);\r
+ if (RegProp != 0 && Len == (2 * sizeof (UINT64))) {\r
+\r
+ NewBase = fdt64_to_cpu (ReadUnaligned64 (RegProp));\r
+ NewSize = fdt64_to_cpu (ReadUnaligned64 (RegProp + 1));\r
+\r
+ //\r
+ // Make sure the start of DRAM matches our expectation\r
+ //\r
+ ASSERT (FixedPcdGet64 (PcdSystemMemoryBase) == NewBase);\r
+ PcdSet64 (PcdSystemMemorySize, NewSize);\r
+\r
+ DEBUG ((EFI_D_INFO, "%a: System RAM @ 0x%lx - 0x%lx\n",\r
+ __FUNCTION__, NewBase, NewBase + NewSize - 1));\r
+ } else {\r
+ DEBUG ((EFI_D_ERROR, "%a: Failed to parse FDT memory node\n",\r
+ __FUNCTION__));\r
+ }\r
+ break;\r
+ }\r
+ }\r
+\r
+ //\r
+ // We need to make sure that the machine we are running on has at least\r
+ // 128 MB of memory configured, and is currently executing this binary from\r
+ // NOR flash. This prevents a device tree image in DRAM from getting\r
+ // clobbered when our caller installs permanent PEI RAM, before we have a\r
+ // chance of marking its location as reserved or copy it to a freshly\r
+ // allocated block in the permanent PEI RAM in the platform PEIM.\r
+ //\r
+ ASSERT (NewSize >= SIZE_128MB);\r
+ ASSERT (\r
+ (((UINT64)PcdGet64 (PcdFdBaseAddress) +\r
+ (UINT64)PcdGet32 (PcdFdSize)) <= NewBase) ||\r
+ ((UINT64)PcdGet64 (PcdFdBaseAddress) >= (NewBase + NewSize)));\r
+}\r
+\r
+VOID\r
+ArmPlatformGetPlatformPpiList (\r
+ OUT UINTN *PpiListSize,\r
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r
+ )\r
+{\r
+ *PpiListSize = 0;\r
+ *PpiList = NULL;\r
+}\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/ArmPlatformGlobalVariableLib.h>\r
+#include <ArmPlatform.h>\r
+\r
+// Number of Virtual Memory Map Descriptors\r
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 4\r
+\r
+// DDR attributes\r
+#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
+\r
+EFI_PHYSICAL_ADDRESS\r
+ArmGetPhysAddrTop (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Return the Virtual Memory Map of your platform\r
+\r
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU\r
+ on your platform.\r
+\r
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR\r
+ describing a Physical-to-Virtual Memory\r
+ mapping. This array must be ended by a\r
+ zero-filled entry\r
+\r
+**/\r
+VOID\r
+ArmPlatformGetVirtualMemoryMap (\r
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap\r
+ )\r
+{\r
+ ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;\r
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r
+\r
+ ASSERT (VirtualMemoryMap != NULL);\r
+\r
+ VirtualMemoryTable = AllocatePages (\r
+ EFI_SIZE_TO_PAGES (\r
+ sizeof (ARM_MEMORY_REGION_DESCRIPTOR)\r
+ * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS\r
+ )\r
+ );\r
+\r
+ if (VirtualMemoryTable == NULL) {\r
+ DEBUG ((EFI_D_ERROR, "%a: Error: Failed AllocatePages()\n", __FUNCTION__));\r
+ return;\r
+ }\r
+\r
+ if (FeaturePcdGet (PcdCacheEnable) == TRUE) {\r
+ CacheAttributes = DDR_ATTRIBUTES_CACHED;\r
+ } else {\r
+ CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r
+ }\r
+\r
+ // System DRAM\r
+ VirtualMemoryTable[0].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);\r
+ VirtualMemoryTable[0].VirtualBase = VirtualMemoryTable[0].PhysicalBase;\r
+ VirtualMemoryTable[0].Length = PcdGet64 (PcdSystemMemorySize);\r
+ VirtualMemoryTable[0].Attributes = CacheAttributes;\r
+\r
+ DEBUG ((EFI_D_INFO, "%a: Dumping System DRAM Memory Map:\n"\r
+ "\tPhysicalBase: 0x%lX\n"\r
+ "\tVirtualBase: 0x%lX\n"\r
+ "\tLength: 0x%lX\n",\r
+ __FUNCTION__,\r
+ VirtualMemoryTable[0].PhysicalBase,\r
+ VirtualMemoryTable[0].VirtualBase,\r
+ VirtualMemoryTable[0].Length));\r
+\r
+ // Peripheral space before DRAM\r
+ VirtualMemoryTable[1].PhysicalBase = 0x0;\r
+ VirtualMemoryTable[1].VirtualBase = 0x0;\r
+ VirtualMemoryTable[1].Length = VirtualMemoryTable[0].PhysicalBase;\r
+ VirtualMemoryTable[1].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+\r
+ // Peripheral space after DRAM\r
+ VirtualMemoryTable[2].PhysicalBase = VirtualMemoryTable[0].Length + VirtualMemoryTable[1].Length;\r
+ VirtualMemoryTable[2].VirtualBase = VirtualMemoryTable[2].PhysicalBase;\r
+ VirtualMemoryTable[2].Length = ArmGetPhysAddrTop () - VirtualMemoryTable[2].PhysicalBase;\r
+ VirtualMemoryTable[2].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+\r
+ // End of Table\r
+ ZeroMem (&VirtualMemoryTable[3], sizeof (ARM_MEMORY_REGION_DESCRIPTOR));\r
+\r
+ *VirtualMemoryMap = VirtualMemoryTable;\r
+}\r
--- /dev/null
+/** @file\r
+ Support ResetSystem Runtime call using PSCI calls\r
+\r
+ Note: A similar library is implemented in\r
+ ArmPkg/Library/ArmPsciResetSystemLib. Similar issues might\r
+ exist in this implementation too.\r
+\r
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+ Copyright (c) 2013, ARM Ltd. All rights reserved.<BR>\r
+ Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/EfiResetSystemLib.h>\r
+#include <Library/ArmSmcLib.h>\r
+#include <Library/ArmHvcLib.h>\r
+\r
+#include <IndustryStandard/ArmStdSmc.h>\r
+\r
+STATIC UINT32 mArmPsciMethod;\r
+\r
+RETURN_STATUS\r
+EFIAPI\r
+ArmPsciResetSystemLibConstructor (\r
+ VOID\r
+ )\r
+{\r
+ mArmPsciMethod = PcdGet32 (PcdArmPsciMethod);\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+ Resets the entire platform.\r
+\r
+ @param ResetType The type of reset to perform.\r
+ @param ResetStatus The status code for the reset.\r
+ @param DataSize The size, in bytes, of WatchdogData.\r
+ @param ResetData For a ResetType of EfiResetCold, EfiResetWarm, or\r
+ EfiResetShutdown the data buffer starts with a Null-terminated\r
+ Unicode string, optionally followed by additional binary data.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibResetSystem (\r
+ IN EFI_RESET_TYPE ResetType,\r
+ IN EFI_STATUS ResetStatus,\r
+ IN UINTN DataSize,\r
+ IN CHAR16 *ResetData OPTIONAL\r
+ )\r
+{\r
+ ARM_SMC_ARGS ArmSmcArgs;\r
+ ARM_HVC_ARGS ArmHvcArgs;\r
+\r
+ switch (ResetType) {\r
+\r
+ case EfiResetPlatformSpecific:\r
+ // Map the platform specific reset as reboot\r
+ case EfiResetWarm:\r
+ // Map a warm reset into a cold reset\r
+ case EfiResetCold:\r
+ // Send a PSCI 0.2 SYSTEM_RESET command\r
+ ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET;\r
+ ArmHvcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET;\r
+ break;\r
+ case EfiResetShutdown:\r
+ // Send a PSCI 0.2 SYSTEM_OFF command\r
+ ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_OFF;\r
+ ArmHvcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_OFF;\r
+ break;\r
+ default:\r
+ ASSERT (FALSE);\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ switch (mArmPsciMethod) {\r
+ case 1:\r
+ ArmCallHvc (&ArmHvcArgs);\r
+ break;\r
+\r
+ case 2:\r
+ ArmCallSmc (&ArmSmcArgs);\r
+ break;\r
+\r
+ default:\r
+ DEBUG ((EFI_D_ERROR, "%a: no PSCI method defined\n", __FUNCTION__));\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ // We should never be here\r
+ DEBUG ((EFI_D_ERROR, "%a: PSCI Reset failed\n", __FUNCTION__));\r
+ CpuDeadLoop ();\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+/**\r
+ Initialize any infrastructure required for LibResetSystem () to function.\r
+\r
+ @param ImageHandle The firmware allocated handle for the EFI image.\r
+ @param SystemTable A pointer to the EFI System Table.\r
+\r
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibInitializeResetSystem (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+#/** @file\r
+# Reset System lib using PSCI hypervisor or secure monitor calls\r
+#\r
+# Copyright (c) 2008, Apple Inc. All rights reserved.<BR>\r
+# Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmVirtPsciResetSystemLib\r
+ FILE_GUID = c81d76ed-66fa-44a3-ac4a-f163120187a9\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = EfiResetSystemLib\r
+ CONSTRUCTOR = ArmPsciResetSystemLibConstructor\r
+\r
+[Sources]\r
+ ArmVirtPsciResetSystemLib.c\r
+\r
+[Packages]\r
+ ArmPkg/ArmPkg.dec\r
+ ArmVirtPkg/ArmVirtPkg.dec\r
+ MdePkg/MdePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+\r
+[LibraryClasses]\r
+ DebugLib\r
+ BaseLib\r
+ ArmSmcLib\r
+ ArmHvcLib\r
+\r
+[Pcd]\r
+ gArmVirtTokenSpaceGuid.PcdArmPsciMethod\r
--- /dev/null
+/*\r
+ * Copyright (c) 2014, Linaro Ltd. All rights reserved.\r
+ *\r
+ * This program and the accompanying materials\r
+ * are licensed and made available under the terms and conditions of the BSD License\r
+ * which accompanies this distribution. The full text of the license may be found at\r
+ * http://opensource.org/licenses/bsd-license.php\r
+ *\r
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ */\r
+\r
+/*\r
+ * Theory of operation\r
+ * -------------------\r
+ *\r
+ * This code parses a Flattened Device Tree binary (DTB) to find the base of\r
+ * system RAM. It is written in assembly so that it can be executed before a\r
+ * stack has been set up.\r
+ *\r
+ * To find the base of system RAM, we have to traverse the FDT to find a memory\r
+ * node. In the context of this implementation, the first node that has a\r
+ * device_type property with the value 'memory' and a 'reg' property is\r
+ * acceptable, and the name of the node (memory[@xxx]) is ignored, as are any\r
+ * other nodes that match the above constraints.\r
+ *\r
+ * In pseudo code, this implementation does the following:\r
+ *\r
+ * for each node {\r
+ * have_device_type = false\r
+ * have_reg = false\r
+ *\r
+ * for each property {\r
+ * if property value == 'memory' {\r
+ * if property name == 'device_type' {\r
+ * have_device_type = true\r
+ * }\r
+ * } else {\r
+ * if property name == 'reg' {\r
+ * have_reg = true\r
+ * membase = property value[0]\r
+ * memsize = property value[1]\r
+ * }\r
+ * }\r
+ * }\r
+ * if have_device_type and have_reg {\r
+ * return membase and memsize\r
+ * }\r
+ * }\r
+ * return NOT_FOUND\r
+ */\r
+\r
+#define FDT_MAGIC 0xedfe0dd0\r
+\r
+#define FDT_BEGIN_NODE 0x1\r
+#define FDT_END_NODE 0x2\r
+#define FDT_PROP 0x3\r
+#define FDT_END 0x9\r
+\r
+ xMEMSIZE .req x0 // recorded system RAM size\r
+ xMEMBASE .req x1 // recorded system RAM base\r
+\r
+ xLR .req x8 // our preserved link register\r
+ xDTP .req x9 // pointer to traverse the DT structure\r
+ xSTRTAB .req x10 // pointer to the DTB string table\r
+ xMEMNODE .req x11 // bit field to record found properties\r
+\r
+#define HAVE_REG 0x1\r
+#define HAVE_DEVICE_TYPE 0x2\r
+\r
+ .text\r
+ .align 3\r
+_memory:\r
+ .asciz "memory"\r
+_reg:\r
+ .asciz "reg"\r
+_device_type:\r
+ .asciz "device_type"\r
+\r
+ /*\r
+ * Compare strings in x4 and x5, return in w7\r
+ */\r
+ .align 3\r
+strcmp:\r
+ ldrb w2, [x4], #1\r
+ ldrb w3, [x5], #1\r
+ subs w7, w2, w3\r
+ cbz w2, 0f\r
+ cbz w3, 0f\r
+ beq strcmp\r
+0: ret\r
+\r
+ .globl find_memnode\r
+find_memnode:\r
+ // preserve link register\r
+ mov xLR, x30\r
+ mov xDTP, x0\r
+\r
+ /*\r
+ * Check the DTB magic at offset 0\r
+ */\r
+ movz w4, #:abs_g0_nc:FDT_MAGIC\r
+ movk w4, #:abs_g1:FDT_MAGIC\r
+ ldr w5, [xDTP]\r
+ cmp w4, w5\r
+ bne err_invalid_magic\r
+\r
+ /*\r
+ * Read the string offset and store it for later use\r
+ */\r
+ ldr w4, [xDTP, #12]\r
+ rev w4, w4\r
+ add xSTRTAB, xDTP, x4\r
+\r
+ /*\r
+ * Read the struct offset and add it to the DT pointer\r
+ */\r
+ ldr w5, [xDTP, #8]\r
+ rev w5, w5\r
+ add xDTP, xDTP, x5\r
+\r
+ /*\r
+ * Check current tag for FDT_BEGIN_NODE\r
+ */\r
+ ldr w5, [xDTP]\r
+ rev w5, w5\r
+ cmp w5, #FDT_BEGIN_NODE\r
+ bne err_unexpected_begin_tag\r
+\r
+begin_node:\r
+ mov xMEMNODE, #0\r
+ add xDTP, xDTP, #4\r
+\r
+ /*\r
+ * Advance xDTP past NULL terminated string\r
+ */\r
+0: ldrb w4, [xDTP], #1\r
+ cbnz w4, 0b\r
+\r
+next_tag:\r
+ /*\r
+ * Align the DT pointer xDTP to the next 32-bit boundary\r
+ */\r
+ add xDTP, xDTP, #3\r
+ and xDTP, xDTP, #~3\r
+\r
+ /*\r
+ * Read the next tag, could be BEGIN_NODE, END_NODE, PROP, END\r
+ */\r
+ ldr w5, [xDTP]\r
+ rev w5, w5\r
+ cmp w5, #FDT_BEGIN_NODE\r
+ beq begin_node\r
+ cmp w5, #FDT_END_NODE\r
+ beq end_node\r
+ cmp w5, #FDT_PROP\r
+ beq prop_node\r
+ cmp w5, #FDT_END\r
+ beq err_end_of_fdt\r
+ b err_unexpected_tag\r
+\r
+prop_node:\r
+ /*\r
+ * If propname == 'reg', record as membase and memsize\r
+ * If propname == 'device_type' and value == 'memory',\r
+ * set the 'is_memnode' flag for this node\r
+ */\r
+ ldr w6, [xDTP, #4]\r
+ add xDTP, xDTP, #12\r
+ rev w6, w6\r
+ mov x5, xDTP\r
+ adr x4, _memory\r
+ bl strcmp\r
+\r
+ /*\r
+ * Get handle to property name\r
+ */\r
+ ldr w5, [xDTP, #-4]\r
+ rev w5, w5\r
+ add x5, xSTRTAB, x5\r
+\r
+ cbz w7, check_device_type\r
+\r
+ /*\r
+ * Check for 'reg' property\r
+ */\r
+ adr x4, _reg\r
+ bl strcmp\r
+ cbnz w7, inc_and_next_tag\r
+\r
+ /*\r
+ * Extract two 64-bit quantities from the 'reg' property. These values\r
+ * will only be used if the node also turns out to have a device_type\r
+ * property with a value of 'memory'.\r
+ *\r
+ * NOTE: xDTP is only guaranteed to be 32 bit aligned, and we are most\r
+ * likely executing with the MMU off, so we cannot use 64 bit\r
+ * wide accesses here.\r
+ */\r
+ ldp w4, w5, [xDTP]\r
+ orr xMEMBASE, x4, x5, lsl #32\r
+ ldp w4, w5, [xDTP, #8]\r
+ orr xMEMSIZE, x4, x5, lsl #32\r
+ rev xMEMBASE, xMEMBASE\r
+ rev xMEMSIZE, xMEMSIZE\r
+ orr xMEMNODE, xMEMNODE, #HAVE_REG\r
+ b inc_and_next_tag\r
+\r
+check_device_type:\r
+ /*\r
+ * Check whether the current property's name is 'device_type'\r
+ */\r
+ adr x4, _device_type\r
+ bl strcmp\r
+ cbnz w7, inc_and_next_tag\r
+ orr xMEMNODE, xMEMNODE, #HAVE_DEVICE_TYPE\r
+\r
+inc_and_next_tag:\r
+ add xDTP, xDTP, x6\r
+ b next_tag\r
+\r
+end_node:\r
+ /*\r
+ * Check for device_type = memory and reg = xxxx\r
+ * If we have both, we are done\r
+ */\r
+ add xDTP, xDTP, #4\r
+ cmp xMEMNODE, #(HAVE_REG | HAVE_DEVICE_TYPE)\r
+ bne next_tag\r
+\r
+ ret xLR\r
+\r
+err_invalid_magic:\r
+err_unexpected_begin_tag:\r
+err_unexpected_tag:\r
+err_end_of_fdt:\r
+ wfi\r
--- /dev/null
+#\r
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+\r
+#include <AsmMacroIoLibV8.h>\r
+#include <Base.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <AutoGen.h>\r
+\r
+.text\r
+.align 2\r
+\r
+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)\r
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r
+GCC_ASM_EXPORT(ArmGetPhysAddrTop)\r
+\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdCoreCount)\r
+\r
+.LFdtMagic:\r
+ .byte 0xd0, 0x0d, 0xfe, 0xed\r
+\r
+.LArm64LinuxMagic:\r
+ .byte 0x41, 0x52, 0x4d, 0x64\r
+\r
+// VOID\r
+// ArmPlatformPeiBootAction (\r
+// VOID *DeviceTreeBaseAddress, // passed by loader in x0\r
+// VOID *ImageBase // passed by FDF trampoline in x1\r
+// );\r
+ASM_PFX(ArmPlatformPeiBootAction):\r
+ mov x29, x30 // preserve LR\r
+\r
+ //\r
+ // If we are booting from RAM using the Linux kernel boot protocol, x0 will\r
+ // point to the DTB image in memory. Otherwise, we are just coming out of\r
+ // reset, and x0 will be 0. Check also the FDT magic.\r
+ //\r
+ cbz x0, .Lout\r
+ ldr w8, .LFdtMagic\r
+ ldr w9, [x0]\r
+ cmp w8, w9\r
+ bne .Lout\r
+\r
+ //\r
+ // The base of the runtime image has been preserved in x1. Check whether\r
+ // the expected magic number can be found in the header.\r
+ //\r
+ ldr w8, .LArm64LinuxMagic\r
+ ldr w9, [x1, #0x38]\r
+ cmp w8, w9\r
+ bne .Lout\r
+\r
+ //\r
+ //\r
+ // OK, so far so good. We have confirmed that we likely have a DTB and are\r
+ // booting via the arm64 Linux boot protocol. Update the base-of-image PCD\r
+ // to the actual relocated value, and add the shift of PcdFdBaseAddress to\r
+ // PcdFvBaseAddress as well\r
+ //\r
+ adr x8, PcdGet64 (PcdFdBaseAddress)\r
+ adr x9, PcdGet64 (PcdFvBaseAddress)\r
+ ldr x6, [x8]\r
+ ldr x7, [x9]\r
+ sub x7, x7, x6\r
+ add x7, x7, x1\r
+ str x1, [x8]\r
+ str x7, [x9]\r
+\r
+ //\r
+ // Copy the DTB to the slack space right after the 64 byte arm64/Linux style\r
+ // image header at the base of this image (defined in the FDF), and record the\r
+ // pointer in PcdDeviceTreeInitialBaseAddress.\r
+ //\r
+ adr x8, PcdGet64 (PcdDeviceTreeInitialBaseAddress)\r
+ add x1, x1, #0x40\r
+ str x1, [x8]\r
+\r
+ ldr w8, [x0, #4] // get DTB size (BE)\r
+ mov x9, x1\r
+ rev w8, w8\r
+ add x8, x8, x0\r
+0:ldp x6, x7, [x0], #16\r
+ stp x6, x7, [x9], #16\r
+ cmp x0, x8\r
+ blt 0b\r
+\r
+ //\r
+ // Discover the memory size and offset from the DTB, and record in the\r
+ // respective PCDs\r
+ //\r
+ mov x0, x1\r
+ bl find_memnode // returns (size, base) size in (x0, x1)\r
+ cbz x0, .Lout\r
+\r
+ adr x8, PcdGet64 (PcdSystemMemorySize)\r
+ adr x9, PcdGet64 (PcdSystemMemoryBase)\r
+ str x0, [x8]\r
+ str x1, [x9]\r
+\r
+.Lout:\r
+ ret x29\r
+\r
+//UINTN\r
+//ArmPlatformGetPrimaryCoreMpId (\r
+// VOID\r
+// );\r
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, x0)\r
+ ldrh w0, [x0]\r
+ ret\r
+\r
+//UINTN\r
+//ArmPlatformIsPrimaryCore (\r
+// IN UINTN MpId\r
+// );\r
+ASM_PFX(ArmPlatformIsPrimaryCore):\r
+ mov x0, #1\r
+ ret\r
+\r
+//UINTN\r
+//ArmPlatformGetCorePosition (\r
+// IN UINTN MpId\r
+// );\r
+// With this function: CorePos = (ClusterId * 4) + CoreId\r
+ASM_PFX(ArmPlatformGetCorePosition):\r
+ and x1, x0, #ARM_CORE_MASK\r
+ and x0, x0, #ARM_CLUSTER_MASK\r
+ add x0, x1, x0, LSR #6\r
+ ret\r
+\r
+//EFI_PHYSICAL_ADDRESS\r
+//GetPhysAddrTop (\r
+// VOID\r
+// );\r
+ASM_PFX(ArmGetPhysAddrTop):\r
+ mrs x0, id_aa64mmfr0_el1\r
+ adr x1, .LPARanges\r
+ and x0, x0, #7\r
+ ldrb w1, [x1, x0]\r
+ mov x0, #1\r
+ lsl x0, x0, x1\r
+ ret\r
+\r
+//\r
+// Bits 0..2 of the AA64MFR0_EL1 system register encode the size of the\r
+// physical address space support on this CPU:\r
+// 0 == 32 bits, 1 == 36 bits, etc etc\r
+// 6 and 7 are reserved\r
+//\r
+.LPARanges:\r
+ .byte 32, 36, 40, 42, 44, 48, -1, -1\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
--- /dev/null
+#/* @file\r
+# Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
+# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#*/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmXenRelocatablePlatformLib\r
+ FILE_GUID = c8602718-4faa-4119-90ca-cae72509ac4c\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = ArmPlatformLib|SEC PEIM\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+ ArmVirtPkg/ArmVirtPkg.dec\r
+\r
+[LibraryClasses]\r
+ IoLib\r
+ ArmLib\r
+ PrintLib\r
+\r
+[Sources.common]\r
+ RelocatableVirt.c\r
+ XenVirtMem.c\r
+\r
+[Sources.AARCH64]\r
+ AARCH64/RelocatableVirtHelper.S\r
+ AARCH64/MemnodeParser.S\r
+\r
+[FeaturePcd]\r
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec\r
+\r
+[PatchPcd]\r
+ gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress\r
+ gArmTokenSpaceGuid.PcdFdBaseAddress\r
+ gArmTokenSpaceGuid.PcdFvBaseAddress\r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize\r
+\r
+[FixedPcd]\r
+ gArmPlatformTokenSpaceGuid.PcdCoreCount\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCore\r
+ gArmTokenSpaceGuid.PcdFdSize\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+* Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+* Copyright (c) 2014, Red Hat, Inc.\r
+*\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Library/IoLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <ArmPlatform.h>\r
+#include <Pi/PiBootMode.h>\r
+\r
+/**\r
+ Return the current Boot Mode\r
+\r
+ This function returns the boot reason on the platform\r
+\r
+ @return Return the current Boot Mode of the platform\r
+\r
+**/\r
+EFI_BOOT_MODE\r
+ArmPlatformGetBootMode (\r
+ VOID\r
+ )\r
+{\r
+ return BOOT_WITH_FULL_CONFIGURATION;\r
+}\r
+\r
+/**\r
+ This function is called by PrePeiCore, in the SEC phase.\r
+**/\r
+RETURN_STATUS\r
+ArmPlatformInitialize (\r
+ IN UINTN MpId\r
+ )\r
+{\r
+ //\r
+ // We are relying on ArmPlatformInitializeSystemMemory () being called from\r
+ // InitializeMemory (), which only occurs if the following feature is disabled\r
+ //\r
+ ASSERT (!FeaturePcdGet (PcdSystemMemoryInitializeInSec));\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+VOID\r
+ArmPlatformInitializeSystemMemory (\r
+ VOID\r
+ )\r
+{\r
+}\r
+\r
+VOID\r
+ArmPlatformGetPlatformPpiList (\r
+ OUT UINTN *PpiListSize,\r
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r
+ )\r
+{\r
+ *PpiListSize = 0;\r
+ *PpiList = NULL;\r
+}\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <ArmPlatform.h>\r
+\r
+// Number of Virtual Memory Map Descriptors\r
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 2\r
+\r
+// DDR attributes\r
+#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
+\r
+EFI_PHYSICAL_ADDRESS\r
+ArmGetPhysAddrTop (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Return the Virtual Memory Map of your platform\r
+\r
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU\r
+ on your platform.\r
+\r
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR\r
+ describing a Physical-to-Virtual Memory\r
+ mapping. This array must be ended by a\r
+ zero-filled entry\r
+\r
+**/\r
+VOID\r
+ArmPlatformGetVirtualMemoryMap (\r
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap\r
+ )\r
+{\r
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r
+\r
+ ASSERT (VirtualMemoryMap != NULL);\r
+\r
+ VirtualMemoryTable = AllocatePages (\r
+ EFI_SIZE_TO_PAGES (\r
+ sizeof (ARM_MEMORY_REGION_DESCRIPTOR)\r
+ * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS\r
+ )\r
+ );\r
+\r
+ if (VirtualMemoryTable == NULL) {\r
+ DEBUG ((EFI_D_ERROR, "%a: Error: Failed AllocatePages()\n", __FUNCTION__));\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Map the entire physical memory space as cached. The only device\r
+ // we care about is the GIC, which will be stage 2 mapped as a device\r
+ // by the hypervisor, which will override the cached mapping we install\r
+ // here.\r
+ //\r
+ VirtualMemoryTable[0].PhysicalBase = 0x0;\r
+ VirtualMemoryTable[0].VirtualBase = 0x0;\r
+ VirtualMemoryTable[0].Length = ArmGetPhysAddrTop ();\r
+ VirtualMemoryTable[0].Attributes = DDR_ATTRIBUTES_CACHED;\r
+\r
+ // End of Table\r
+ ZeroMem (&VirtualMemoryTable[1], sizeof (ARM_MEMORY_REGION_DESCRIPTOR));\r
+\r
+ *VirtualMemoryMap = VirtualMemoryTable;\r
+}\r
--- /dev/null
+## @file\r
+# Instance of PCI Express Library using the 256 MB PCI Express MMIO window.\r
+#\r
+# PCI Express Library that uses the 256 MB PCI Express MMIO window to perform\r
+# PCI Configuration cycles. Layers on top of an I/O Library instance.\r
+#\r
+# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = BaseCachingPciExpressLib\r
+ FILE_GUID = 3f3ffd80-04dc-4a2b-9d25-ecca55c2e520\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = PciExpressLib|DXE_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
+ CONSTRUCTOR = PciExpressLibInitialize\r
+\r
+#\r
+# VALID_ARCHITECTURES = ARM AARCH64\r
+#\r
+\r
+[Sources]\r
+ PciExpressLib.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ PcdLib\r
+ DebugLib\r
+ IoLib\r
+\r
+[Pcd]\r
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES\r
+\r
--- /dev/null
+/** @file\r
+ Functions in this library instance make use of MMIO functions in IoLib to\r
+ access memory mapped PCI configuration space.\r
+\r
+ All assertions for I/O operations are handled in MMIO functions in the IoLib\r
+ Library.\r
+\r
+ Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include <Base.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/PciExpressLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+\r
+/**\r
+ Assert the validity of a PCI address. A valid PCI address should contain 1's\r
+ only in the low 28 bits.\r
+\r
+ @param A The address to validate.\r
+\r
+**/\r
+#define ASSERT_INVALID_PCI_ADDRESS(A) \\r
+ ASSERT (((A) & ~0xfffffff) == 0)\r
+\r
+/**\r
+ Registers a PCI device so PCI configuration registers may be accessed after\r
+ SetVirtualAddressMap().\r
+\r
+ Registers the PCI device specified by Address so all the PCI configuration\r
+ registers associated with that PCI device may be accessed after SetVirtualAddressMap()\r
+ is called.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+\r
+ @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function\r
+ after ExitBootServices().\r
+ @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r
+ at runtime could not be mapped.\r
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r
+ complete the registration.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+PciExpressRegisterForRuntimeAccess (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return RETURN_UNSUPPORTED;\r
+}\r
+\r
+STATIC UINT64 mPciExpressBaseAddress;\r
+\r
+RETURN_STATUS\r
+EFIAPI\r
+PciExpressLibInitialize (\r
+ VOID\r
+ )\r
+{\r
+ mPciExpressBaseAddress = PcdGet64 (PcdPciExpressBaseAddress);\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Gets the base address of PCI Express.\r
+\r
+ @return The base address of PCI Express.\r
+\r
+**/\r
+VOID*\r
+GetPciExpressBaseAddress (\r
+ VOID\r
+ )\r
+{\r
+ return (VOID*)(UINTN) mPciExpressBaseAddress;\r
+}\r
+\r
+/**\r
+ Reads an 8-bit PCI configuration register.\r
+\r
+ Reads and returns the 8-bit PCI configuration register specified by Address.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+\r
+ @return The read value from the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciExpressRead8 (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioRead8 ((UINTN) GetPciExpressBaseAddress () + Address);\r
+}\r
+\r
+/**\r
+ Writes an 8-bit PCI configuration register.\r
+\r
+ Writes the 8-bit PCI configuration register specified by Address with the\r
+ value specified by Value. Value is returned. This function must guarantee\r
+ that all PCI read and write operations are serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param Value The value to write.\r
+\r
+ @return The value written to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciExpressWrite8 (\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r
+}\r
+\r
+/**\r
+ Performs a bitwise OR of an 8-bit PCI configuration register with\r
+ an 8-bit value.\r
+\r
+ Reads the 8-bit PCI configuration register specified by Address, performs a\r
+ bitwise OR between the read result and the value specified by\r
+ OrData, and writes the result to the 8-bit PCI configuration register\r
+ specified by Address. The value written to the PCI configuration register is\r
+ returned. This function must guarantee that all PCI read and write operations\r
+ are serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param OrData The value to OR with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciExpressOr8 (\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioOr8 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r
+}\r
+\r
+/**\r
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
+ value.\r
+\r
+ Reads the 8-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData, and\r
+ writes the result to the 8-bit PCI configuration register specified by\r
+ Address. The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciExpressAnd8 (\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioAnd8 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r
+}\r
+\r
+/**\r
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
+ value, followed a bitwise OR with another 8-bit value.\r
+\r
+ Reads the 8-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData,\r
+ performs a bitwise OR between the result of the AND operation and\r
+ the value specified by OrData, and writes the result to the 8-bit PCI\r
+ configuration register specified by Address. The value written to the PCI\r
+ configuration register is returned. This function must guarantee that all PCI\r
+ read and write operations are serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciExpressAndThenOr8 (\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioAndThenOr8 (\r
+ (UINTN) GetPciExpressBaseAddress () + Address,\r
+ AndData,\r
+ OrData\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field of a PCI configuration register.\r
+\r
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is\r
+ specified by the StartBit and the EndBit. The value of the bit field is\r
+ returned.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to read.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+\r
+ @return The value of the bit field read from the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciExpressBitFieldRead8 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioBitFieldRead8 (\r
+ (UINTN) GetPciExpressBaseAddress () + Address,\r
+ StartBit,\r
+ EndBit\r
+ );\r
+}\r
+\r
+/**\r
+ Writes a bit field to a PCI configuration register.\r
+\r
+ Writes Value to the bit field of the PCI configuration register. The bit\r
+ field is specified by the StartBit and the EndBit. All other bits in the\r
+ destination PCI configuration register are preserved. The new value of the\r
+ 8-bit register is returned.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param Value The new value of the bit field.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciExpressBitFieldWrite8 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioBitFieldWrite8 (\r
+ (UINTN) GetPciExpressBaseAddress () + Address,\r
+ StartBit,\r
+ EndBit,\r
+ Value\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r
+ writes the result back to the bit field in the 8-bit port.\r
+\r
+ Reads the 8-bit PCI configuration register specified by Address, performs a\r
+ bitwise OR between the read result and the value specified by\r
+ OrData, and writes the result to the 8-bit PCI configuration register\r
+ specified by Address. The value written to the PCI configuration register is\r
+ returned. This function must guarantee that all PCI read and write operations\r
+ are serialized. Extra left bits in OrData are stripped.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param OrData The value to OR with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciExpressBitFieldOr8 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioBitFieldOr8 (\r
+ (UINTN) GetPciExpressBaseAddress () + Address,\r
+ StartBit,\r
+ EndBit,\r
+ OrData\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r
+ AND, and writes the result back to the bit field in the 8-bit register.\r
+\r
+ Reads the 8-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData, and\r
+ writes the result to the 8-bit PCI configuration register specified by\r
+ Address. The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized. Extra left bits in AndData are stripped.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciExpressBitFieldAnd8 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioBitFieldAnd8 (\r
+ (UINTN) GetPciExpressBaseAddress () + Address,\r
+ StartBit,\r
+ EndBit,\r
+ AndData\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
+ bitwise OR, and writes the result back to the bit field in the\r
+ 8-bit port.\r
+\r
+ Reads the 8-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND followed by a bitwise OR between the read result and\r
+ the value specified by AndData, and writes the result to the 8-bit PCI\r
+ configuration register specified by Address. The value written to the PCI\r
+ configuration register is returned. This function must guarantee that all PCI\r
+ read and write operations are serialized. Extra left bits in both AndData and\r
+ OrData are stripped.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciExpressBitFieldAndThenOr8 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioBitFieldAndThenOr8 (\r
+ (UINTN) GetPciExpressBaseAddress () + Address,\r
+ StartBit,\r
+ EndBit,\r
+ AndData,\r
+ OrData\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a 16-bit PCI configuration register.\r
+\r
+ Reads and returns the 16-bit PCI configuration register specified by Address.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+\r
+ @return The read value from the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciExpressRead16 (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioRead16 ((UINTN) GetPciExpressBaseAddress () + Address);\r
+}\r
+\r
+/**\r
+ Writes a 16-bit PCI configuration register.\r
+\r
+ Writes the 16-bit PCI configuration register specified by Address with the\r
+ value specified by Value. Value is returned. This function must guarantee\r
+ that all PCI read and write operations are serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param Value The value to write.\r
+\r
+ @return The value written to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciExpressWrite16 (\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioWrite16 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r
+}\r
+\r
+/**\r
+ Performs a bitwise OR of a 16-bit PCI configuration register with\r
+ a 16-bit value.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address, performs a\r
+ bitwise OR between the read result and the value specified by\r
+ OrData, and writes the result to the 16-bit PCI configuration register\r
+ specified by Address. The value written to the PCI configuration register is\r
+ returned. This function must guarantee that all PCI read and write operations\r
+ are serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param OrData The value to OR with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciExpressOr16 (\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r
+}\r
+\r
+/**\r
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
+ value.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData, and\r
+ writes the result to the 16-bit PCI configuration register specified by\r
+ Address. The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciExpressAnd16 (\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioAnd16 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r
+}\r
+\r
+/**\r
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
+ value, followed a bitwise OR with another 16-bit value.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData,\r
+ performs a bitwise OR between the result of the AND operation and\r
+ the value specified by OrData, and writes the result to the 16-bit PCI\r
+ configuration register specified by Address. The value written to the PCI\r
+ configuration register is returned. This function must guarantee that all PCI\r
+ read and write operations are serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciExpressAndThenOr16 (\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioAndThenOr16 (\r
+ (UINTN) GetPciExpressBaseAddress () + Address,\r
+ AndData,\r
+ OrData\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field of a PCI configuration register.\r
+\r
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is\r
+ specified by the StartBit and the EndBit. The value of the bit field is\r
+ returned.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to read.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+\r
+ @return The value of the bit field read from the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciExpressBitFieldRead16 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioBitFieldRead16 (\r
+ (UINTN) GetPciExpressBaseAddress () + Address,\r
+ StartBit,\r
+ EndBit\r
+ );\r
+}\r
+\r
+/**\r
+ Writes a bit field to a PCI configuration register.\r
+\r
+ Writes Value to the bit field of the PCI configuration register. The bit\r
+ field is specified by the StartBit and the EndBit. All other bits in the\r
+ destination PCI configuration register are preserved. The new value of the\r
+ 16-bit register is returned.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param Value The new value of the bit field.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciExpressBitFieldWrite16 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioBitFieldWrite16 (\r
+ (UINTN) GetPciExpressBaseAddress () + Address,\r
+ StartBit,\r
+ EndBit,\r
+ Value\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r
+ writes the result back to the bit field in the 16-bit port.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address, performs a\r
+ bitwise OR between the read result and the value specified by\r
+ OrData, and writes the result to the 16-bit PCI configuration register\r
+ specified by Address. The value written to the PCI configuration register is\r
+ returned. This function must guarantee that all PCI read and write operations\r
+ are serialized. Extra left bits in OrData are stripped.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param OrData The value to OR with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciExpressBitFieldOr16 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioBitFieldOr16 (\r
+ (UINTN) GetPciExpressBaseAddress () + Address,\r
+ StartBit,\r
+ EndBit,\r
+ OrData\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r
+ AND, and writes the result back to the bit field in the 16-bit register.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData, and\r
+ writes the result to the 16-bit PCI configuration register specified by\r
+ Address. The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized. Extra left bits in AndData are stripped.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciExpressBitFieldAnd16 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioBitFieldAnd16 (\r
+ (UINTN) GetPciExpressBaseAddress () + Address,\r
+ StartBit,\r
+ EndBit,\r
+ AndData\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r
+ bitwise OR, and writes the result back to the bit field in the\r
+ 16-bit port.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND followed by a bitwise OR between the read result and\r
+ the value specified by AndData, and writes the result to the 16-bit PCI\r
+ configuration register specified by Address. The value written to the PCI\r
+ configuration register is returned. This function must guarantee that all PCI\r
+ read and write operations are serialized. Extra left bits in both AndData and\r
+ OrData are stripped.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciExpressBitFieldAndThenOr16 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioBitFieldAndThenOr16 (\r
+ (UINTN) GetPciExpressBaseAddress () + Address,\r
+ StartBit,\r
+ EndBit,\r
+ AndData,\r
+ OrData\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a 32-bit PCI configuration register.\r
+\r
+ Reads and returns the 32-bit PCI configuration register specified by Address.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+\r
+ @return The read value from the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciExpressRead32 (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Address);\r
+}\r
+\r
+/**\r
+ Writes a 32-bit PCI configuration register.\r
+\r
+ Writes the 32-bit PCI configuration register specified by Address with the\r
+ value specified by Value. Value is returned. This function must guarantee\r
+ that all PCI read and write operations are serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param Value The value to write.\r
+\r
+ @return The value written to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciExpressWrite32 (\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r
+}\r
+\r
+/**\r
+ Performs a bitwise OR of a 32-bit PCI configuration register with\r
+ a 32-bit value.\r
+\r
+ Reads the 32-bit PCI configuration register specified by Address, performs a\r
+ bitwise OR between the read result and the value specified by\r
+ OrData, and writes the result to the 32-bit PCI configuration register\r
+ specified by Address. The value written to the PCI configuration register is\r
+ returned. This function must guarantee that all PCI read and write operations\r
+ are serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param OrData The value to OR with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciExpressOr32 (\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r
+}\r
+\r
+/**\r
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
+ value.\r
+\r
+ Reads the 32-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData, and\r
+ writes the result to the 32-bit PCI configuration register specified by\r
+ Address. The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciExpressAnd32 (\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r
+}\r
+\r
+/**\r
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
+ value, followed a bitwise OR with another 32-bit value.\r
+\r
+ Reads the 32-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData,\r
+ performs a bitwise OR between the result of the AND operation and\r
+ the value specified by OrData, and writes the result to the 32-bit PCI\r
+ configuration register specified by Address. The value written to the PCI\r
+ configuration register is returned. This function must guarantee that all PCI\r
+ read and write operations are serialized.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciExpressAndThenOr32 (\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioAndThenOr32 (\r
+ (UINTN) GetPciExpressBaseAddress () + Address,\r
+ AndData,\r
+ OrData\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field of a PCI configuration register.\r
+\r
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is\r
+ specified by the StartBit and the EndBit. The value of the bit field is\r
+ returned.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to read.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+\r
+ @return The value of the bit field read from the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciExpressBitFieldRead32 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioBitFieldRead32 (\r
+ (UINTN) GetPciExpressBaseAddress () + Address,\r
+ StartBit,\r
+ EndBit\r
+ );\r
+}\r
+\r
+/**\r
+ Writes a bit field to a PCI configuration register.\r
+\r
+ Writes Value to the bit field of the PCI configuration register. The bit\r
+ field is specified by the StartBit and the EndBit. All other bits in the\r
+ destination PCI configuration register are preserved. The new value of the\r
+ 32-bit register is returned.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param Value The new value of the bit field.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciExpressBitFieldWrite32 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioBitFieldWrite32 (\r
+ (UINTN) GetPciExpressBaseAddress () + Address,\r
+ StartBit,\r
+ EndBit,\r
+ Value\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r
+ writes the result back to the bit field in the 32-bit port.\r
+\r
+ Reads the 32-bit PCI configuration register specified by Address, performs a\r
+ bitwise OR between the read result and the value specified by\r
+ OrData, and writes the result to the 32-bit PCI configuration register\r
+ specified by Address. The value written to the PCI configuration register is\r
+ returned. This function must guarantee that all PCI read and write operations\r
+ are serialized. Extra left bits in OrData are stripped.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param OrData The value to OR with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciExpressBitFieldOr32 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioBitFieldOr32 (\r
+ (UINTN) GetPciExpressBaseAddress () + Address,\r
+ StartBit,\r
+ EndBit,\r
+ OrData\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r
+ AND, and writes the result back to the bit field in the 32-bit register.\r
+\r
+ Reads the 32-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData, and\r
+ writes the result to the 32-bit PCI configuration register specified by\r
+ Address. The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized. Extra left bits in AndData are stripped.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciExpressBitFieldAnd32 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioBitFieldAnd32 (\r
+ (UINTN) GetPciExpressBaseAddress () + Address,\r
+ StartBit,\r
+ EndBit,\r
+ AndData\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r
+ bitwise OR, and writes the result back to the bit field in the\r
+ 32-bit port.\r
+\r
+ Reads the 32-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND followed by a bitwise OR between the read result and\r
+ the value specified by AndData, and writes the result to the 32-bit PCI\r
+ configuration register specified by Address. The value written to the PCI\r
+ configuration register is returned. This function must guarantee that all PCI\r
+ read and write operations are serialized. Extra left bits in both AndData and\r
+ OrData are stripped.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address The PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciExpressBitFieldAndThenOr32 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return MmioBitFieldAndThenOr32 (\r
+ (UINTN) GetPciExpressBaseAddress () + Address,\r
+ StartBit,\r
+ EndBit,\r
+ AndData,\r
+ OrData\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a range of PCI configuration registers into a caller supplied buffer.\r
+\r
+ Reads the range of PCI configuration registers specified by StartAddress and\r
+ Size into the buffer specified by Buffer. This function only allows the PCI\r
+ configuration registers from a single PCI function to be read. Size is\r
+ returned. When possible 32-bit PCI configuration read cycles are used to read\r
+ from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
+ and 16-bit PCI configuration read cycles may be used at the beginning and the\r
+ end of the range.\r
+\r
+ If StartAddress > 0x0FFFFFFF, then ASSERT().\r
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
+ If Size > 0 and Buffer is NULL, then ASSERT().\r
+\r
+ @param StartAddress The starting address that encodes the PCI Bus, Device,\r
+ Function and Register.\r
+ @param Size The size in bytes of the transfer.\r
+ @param Buffer The pointer to a buffer receiving the data read.\r
+\r
+ @return Size read data from StartAddress.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+PciExpressReadBuffer (\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
+ )\r
+{\r
+ UINTN ReturnValue;\r
+\r
+ ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
+\r
+ if (Size == 0) {\r
+ return Size;\r
+ }\r
+\r
+ ASSERT (Buffer != NULL);\r
+\r
+ //\r
+ // Save Size for return\r
+ //\r
+ ReturnValue = Size;\r
+\r
+ if ((StartAddress & 1) != 0) {\r
+ //\r
+ // Read a byte if StartAddress is byte aligned\r
+ //\r
+ *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r
+ StartAddress += sizeof (UINT8);\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8*)Buffer + 1;\r
+ }\r
+\r
+ if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
+ //\r
+ // Read a word if StartAddress is word aligned\r
+ //\r
+ WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r
+\r
+ StartAddress += sizeof (UINT16);\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16*)Buffer + 1;\r
+ }\r
+\r
+ while (Size >= sizeof (UINT32)) {\r
+ //\r
+ // Read as many double words as possible\r
+ //\r
+ WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));\r
+\r
+ StartAddress += sizeof (UINT32);\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32*)Buffer + 1;\r
+ }\r
+\r
+ if (Size >= sizeof (UINT16)) {\r
+ //\r
+ // Read the last remaining word if exist\r
+ //\r
+ WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r
+ StartAddress += sizeof (UINT16);\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16*)Buffer + 1;\r
+ }\r
+\r
+ if (Size >= sizeof (UINT8)) {\r
+ //\r
+ // Read the last remaining byte if exist\r
+ //\r
+ *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r
+ }\r
+\r
+ return ReturnValue;\r
+}\r
+\r
+/**\r
+ Copies the data in a caller supplied buffer to a specified range of PCI\r
+ configuration space.\r
+\r
+ Writes the range of PCI configuration registers specified by StartAddress and\r
+ Size from the buffer specified by Buffer. This function only allows the PCI\r
+ configuration registers from a single PCI function to be written. Size is\r
+ returned. When possible 32-bit PCI configuration write cycles are used to\r
+ write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
+ and the end of the range.\r
+\r
+ If StartAddress > 0x0FFFFFFF, then ASSERT().\r
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
+ If Size > 0 and Buffer is NULL, then ASSERT().\r
+\r
+ @param StartAddress The starting address that encodes the PCI Bus, Device,\r
+ Function and Register.\r
+ @param Size The size in bytes of the transfer.\r
+ @param Buffer The pointer to a buffer containing the data to write.\r
+\r
+ @return Size written to StartAddress.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+PciExpressWriteBuffer (\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ UINTN ReturnValue;\r
+\r
+ ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
+\r
+ if (Size == 0) {\r
+ return 0;\r
+ }\r
+\r
+ ASSERT (Buffer != NULL);\r
+\r
+ //\r
+ // Save Size for return\r
+ //\r
+ ReturnValue = Size;\r
+\r
+ if ((StartAddress & 1) != 0) {\r
+ //\r
+ // Write a byte if StartAddress is byte aligned\r
+ //\r
+ PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ StartAddress += sizeof (UINT8);\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8*)Buffer + 1;\r
+ }\r
+\r
+ if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
+ //\r
+ // Write a word if StartAddress is word aligned\r
+ //\r
+ PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r
+ StartAddress += sizeof (UINT16);\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16*)Buffer + 1;\r
+ }\r
+\r
+ while (Size >= sizeof (UINT32)) {\r
+ //\r
+ // Write as many double words as possible\r
+ //\r
+ PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));\r
+ StartAddress += sizeof (UINT32);\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32*)Buffer + 1;\r
+ }\r
+\r
+ if (Size >= sizeof (UINT16)) {\r
+ //\r
+ // Write the last remaining word if exist\r
+ //\r
+ PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r
+ StartAddress += sizeof (UINT16);\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16*)Buffer + 1;\r
+ }\r
+\r
+ if (Size >= sizeof (UINT8)) {\r
+ //\r
+ // Write the last remaining byte if exist\r
+ //\r
+ PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ }\r
+\r
+ return ReturnValue;\r
+}\r
--- /dev/null
+/** @file\r
+ Serial I/O Port library functions with base address discovered from FDT\r
+\r
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+ Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.<BR>\r
+ Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Base.h>\r
+\r
+#include <Library/PcdLib.h>\r
+#include <Library/SerialPortLib.h>\r
+#include <Library/SerialPortExtLib.h>\r
+#include <libfdt.h>\r
+\r
+#include <Drivers/PL011Uart.h>\r
+\r
+RETURN_STATUS\r
+EFIAPI\r
+SerialPortInitialize (\r
+ VOID\r
+ )\r
+{\r
+ //\r
+ // This SerialPortInitialize() function is completely empty, for a number of\r
+ // reasons:\r
+ // - if we are executing from flash, it is hard to keep state (i.e., store the\r
+ // discovered base address in a global), and the most robust way to deal\r
+ // with this is to discover the base address at every Write ();\r
+ // - calls to the Write() function in this module may be issued before this\r
+ // initialization function is called: this is not a problem when the base\r
+ // address of the UART is hardcoded, and only the baud rate may be wrong,\r
+ // but if we don't know the base address yet, we may be poking into memory\r
+ // that does not tolerate being poked into;\r
+ // - SEC and PEI phases produce debug output only, so with debug disabled, no\r
+ // initialization (or device tree parsing) is performed at all.\r
+ //\r
+ // Note that this means that on *every* Write () call, the device tree will be\r
+ // parsed and the UART re-initialized. However, this is a small price to pay\r
+ // for having serial debug output on a UART with no fixed base address.\r
+ //\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+STATIC\r
+UINT64\r
+SerialPortGetBaseAddress (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 BaudRate;\r
+ UINT32 ReceiveFifoDepth;\r
+ EFI_PARITY_TYPE Parity;\r
+ UINT8 DataBits;\r
+ EFI_STOP_BITS_TYPE StopBits;\r
+ VOID *DeviceTreeBase;\r
+ INT32 Node, Prev;\r
+ INT32 Len;\r
+ CONST CHAR8 *Compatible;\r
+ CONST CHAR8 *CompatibleItem;\r
+ CONST UINT64 *RegProperty;\r
+ UINTN UartBase;\r
+ RETURN_STATUS Status;\r
+\r
+ DeviceTreeBase = (VOID *)(UINTN)FixedPcdGet64 (PcdDeviceTreeInitialBaseAddress);\r
+\r
+ if ((DeviceTreeBase == NULL) || (fdt_check_header (DeviceTreeBase) != 0)) {\r
+ return 0;\r
+ }\r
+\r
+ //\r
+ // Enumerate all FDT nodes looking for a PL011 and capture its base address\r
+ //\r
+ for (Prev = 0;; Prev = Node) {\r
+ Node = fdt_next_node (DeviceTreeBase, Prev, NULL);\r
+ if (Node < 0) {\r
+ break;\r
+ }\r
+\r
+ Compatible = fdt_getprop (DeviceTreeBase, Node, "compatible", &Len);\r
+ if (Compatible == NULL) {\r
+ continue;\r
+ }\r
+\r
+ //\r
+ // Iterate over the NULL-separated items in the compatible string\r
+ //\r
+ for (CompatibleItem = Compatible; CompatibleItem < Compatible + Len;\r
+ CompatibleItem += 1 + AsciiStrLen (CompatibleItem)) {\r
+\r
+ if (AsciiStrCmp (CompatibleItem, "arm,pl011") == 0) {\r
+ RegProperty = fdt_getprop (DeviceTreeBase, Node, "reg", &Len);\r
+ if (Len != 16) {\r
+ return 0;\r
+ }\r
+ UartBase = (UINTN)fdt64_to_cpu (ReadUnaligned64 (RegProperty));\r
+\r
+ BaudRate = (UINTN)FixedPcdGet64 (PcdUartDefaultBaudRate);\r
+ ReceiveFifoDepth = 0; // Use the default value for Fifo depth\r
+ Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);\r
+ DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);\r
+ StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);\r
+\r
+ Status = PL011UartInitializePort (\r
+ UartBase,\r
+ &BaudRate, &ReceiveFifoDepth, &Parity, &DataBits, &StopBits);\r
+ if (!EFI_ERROR (Status)) {\r
+ return UartBase;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ Write data to serial device.\r
+\r
+ @param Buffer Point of data buffer which need to be written.\r
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.\r
+\r
+ @retval 0 Write data failed.\r
+ @retval !0 Actual number of bytes written to serial device.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+SerialPortWrite (\r
+ IN UINT8 *Buffer,\r
+ IN UINTN NumberOfBytes\r
+ )\r
+{\r
+ UINT64 SerialRegisterBase;\r
+\r
+ SerialRegisterBase = SerialPortGetBaseAddress ();\r
+ if (SerialRegisterBase != 0) {\r
+ return PL011UartWrite ((UINTN)SerialRegisterBase, Buffer, NumberOfBytes);\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ Read data from serial device and save the data in buffer.\r
+\r
+ @param Buffer Point of data buffer which need to be written.\r
+ @param NumberOfBytes Size of Buffer[].\r
+\r
+ @retval 0 Read data failed.\r
+ @retval !0 Actual number of bytes read from serial device.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+SerialPortRead (\r
+ OUT UINT8 *Buffer,\r
+ IN UINTN NumberOfBytes\r
+)\r
+{\r
+ return 0;\r
+}\r
+\r
+/**\r
+ Check to see if any data is available to be read from the debug device.\r
+\r
+ @retval TRUE At least one byte of data is available to be read\r
+ @retval FALSE No data is available to be read\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+SerialPortPoll (\r
+ VOID\r
+ )\r
+{\r
+ return FALSE;\r
+}\r
--- /dev/null
+#/** @file\r
+#\r
+# Component description file for EarlyFdtPL011SerialPortLib module\r
+#\r
+# Copyright (c) 2011-2015, ARM Ltd. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = EarlyFdtPL011SerialPortLib\r
+ FILE_GUID = 0983616A-49BC-4732-B531-4AF98D2056F0\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = SerialPortLib|SEC PEI_CORE PEIM\r
+\r
+[Sources.common]\r
+ EarlyFdtPL011SerialPortLib.c\r
+\r
+[LibraryClasses]\r
+ PL011UartLib\r
+ PcdLib\r
+ FdtLib\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+ ArmVirtPkg/ArmVirtPkg.dec\r
+\r
+[FixedPcd]\r
+ gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress\r
+\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits\r
--- /dev/null
+/** @file\r
+ Serial I/O Port library functions with base address discovered from FDT\r
+\r
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+ Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.<BR>\r
+ Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
+ Copyright (c) 2014, Red Hat, Inc.<BR>\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Base.h>\r
+\r
+#include <Library/PcdLib.h>\r
+#include <Library/SerialPortLib.h>\r
+#include <Pi/PiBootMode.h>\r
+#include <Uefi/UefiBaseType.h>\r
+#include <Uefi/UefiMultiPhase.h>\r
+#include <Pi/PiHob.h>\r
+#include <Library/HobLib.h>\r
+#include <Guid/EarlyPL011BaseAddress.h>\r
+\r
+#include <Drivers/PL011Uart.h>\r
+\r
+STATIC UINTN mSerialBaseAddress;\r
+\r
+RETURN_STATUS\r
+EFIAPI\r
+SerialPortInitialize (\r
+ VOID\r
+ )\r
+{\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+\r
+ Program hardware of Serial port\r
+\r
+ @return RETURN_NOT_FOUND if no PL011 base address could be found\r
+ Otherwise, result of PL011UartInitializePort () is returned\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+FdtPL011SerialPortLibInitialize (\r
+ VOID\r
+ )\r
+{\r
+ VOID *Hob;\r
+ CONST UINT64 *UartBase;\r
+ UINT64 BaudRate;\r
+ UINT32 ReceiveFifoDepth;\r
+ EFI_PARITY_TYPE Parity;\r
+ UINT8 DataBits;\r
+ EFI_STOP_BITS_TYPE StopBits;\r
+\r
+ Hob = GetFirstGuidHob (&gEarlyPL011BaseAddressGuid);\r
+ if (Hob == NULL || GET_GUID_HOB_DATA_SIZE (Hob) != sizeof *UartBase) {\r
+ return RETURN_NOT_FOUND;\r
+ }\r
+ UartBase = GET_GUID_HOB_DATA (Hob);\r
+\r
+ mSerialBaseAddress = (UINTN)*UartBase;\r
+ if (mSerialBaseAddress == 0) {\r
+ return RETURN_NOT_FOUND;\r
+ }\r
+\r
+ BaudRate = (UINTN)PcdGet64 (PcdUartDefaultBaudRate);\r
+ ReceiveFifoDepth = 0; // Use the default value for Fifo depth\r
+ Parity = (EFI_PARITY_TYPE)PcdGet8 (PcdUartDefaultParity);\r
+ DataBits = PcdGet8 (PcdUartDefaultDataBits);\r
+ StopBits = (EFI_STOP_BITS_TYPE) PcdGet8 (PcdUartDefaultStopBits);\r
+\r
+ return PL011UartInitializePort (\r
+ mSerialBaseAddress, &BaudRate, &ReceiveFifoDepth,\r
+ &Parity, &DataBits, &StopBits);\r
+}\r
+\r
+/**\r
+ Write data to serial device.\r
+\r
+ @param Buffer Point of data buffer which need to be written.\r
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.\r
+\r
+ @retval 0 Write data failed.\r
+ @retval !0 Actual number of bytes written to serial device.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+SerialPortWrite (\r
+ IN UINT8 *Buffer,\r
+ IN UINTN NumberOfBytes\r
+ )\r
+{\r
+ if (mSerialBaseAddress != 0) {\r
+ return PL011UartWrite (mSerialBaseAddress, Buffer, NumberOfBytes);\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ Read data from serial device and save the data in buffer.\r
+\r
+ @param Buffer Point of data buffer which need to be written.\r
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.\r
+\r
+ @retval 0 Read data failed.\r
+ @retval !0 Actual number of bytes read from serial device.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+SerialPortRead (\r
+ OUT UINT8 *Buffer,\r
+ IN UINTN NumberOfBytes\r
+)\r
+{\r
+ if (mSerialBaseAddress != 0) {\r
+ return PL011UartRead (mSerialBaseAddress, Buffer, NumberOfBytes);\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ Check to see if any data is available to be read from the debug device.\r
+\r
+ @retval TRUE At least one byte of data is available to be read\r
+ @retval FALSE No data is available to be read\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+SerialPortPoll (\r
+ VOID\r
+ )\r
+{\r
+ if (mSerialBaseAddress != 0) {\r
+ return PL011UartPoll (mSerialBaseAddress);\r
+ }\r
+ return FALSE;\r
+}\r
--- /dev/null
+#/** @file\r
+#\r
+# Component description file for PL011SerialPortLib module\r
+#\r
+# Copyright (c) 2011-2015, ARM Ltd. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = FdtPL011SerialPortLib\r
+ FILE_GUID = CB768406-7DE6-49B6-BC2C-F324E110DE5A\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = SerialPortLib|DXE_CORE DXE_DRIVER UEFI_DRIVER DXE_RUNTIME_DRIVER UEFI_APPLICATION\r
+ CONSTRUCTOR = FdtPL011SerialPortLibInitialize\r
+\r
+[Sources.common]\r
+ FdtPL011SerialPortLib.c\r
+\r
+[LibraryClasses]\r
+ PL011UartLib\r
+ HobLib\r
+\r
+[Packages]\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+ ArmVirtPkg/ArmVirtPkg.dec\r
+ ArmPkg/ArmPkg.dec\r
+\r
+[FixedPcd]\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits\r
+\r
+[Guids]\r
+ gEarlyPL011BaseAddressGuid\r
--- /dev/null
+/** @file\r
+\r
+ Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ **/\r
+\r
+#include <ArmPlatform.h>\r
+#include <Library/NorFlashPlatformLib.h>\r
+\r
+EFI_STATUS\r
+NorFlashPlatformInitialization (\r
+ VOID\r
+ )\r
+{\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+NOR_FLASH_DESCRIPTION mNorFlashDevices[] = {\r
+ {\r
+ QEMU_NOR0_BASE,\r
+ QEMU_NOR0_BASE,\r
+ QEMU_NOR0_SIZE,\r
+ QEMU_NOR_BLOCK_SIZE,\r
+ {0xF9B94AE2, 0x8BA6, 0x409B, {0x9D, 0x56, 0xB9, 0xB4, 0x17, 0xF5, 0x3C, 0xB3}}\r
+ }, {\r
+ QEMU_NOR1_BASE,\r
+ QEMU_NOR1_BASE,\r
+ QEMU_NOR1_SIZE,\r
+ QEMU_NOR_BLOCK_SIZE,\r
+ {0x8047DB4B, 0x7E9C, 0x4C0C, {0x8E, 0xBC, 0xDF, 0xBB, 0xAA, 0xCA, 0xCE, 0x8F}}\r
+ }\r
+};\r
+\r
+EFI_STATUS\r
+NorFlashPlatformGetDevices (\r
+ OUT NOR_FLASH_DESCRIPTION **NorFlashDescriptions,\r
+ OUT UINT32 *Count\r
+ )\r
+{\r
+ *NorFlashDescriptions = mNorFlashDevices;\r
+ *Count = sizeof (mNorFlashDevices) / sizeof (mNorFlashDevices[0]);\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+#/** @file\r
+#\r
+# Component description file for NorFlashQemuLib module\r
+#\r
+# Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = NorFlashQemuLib\r
+ FILE_GUID = 339B7829-4C5F-4EFC-B2DD-5050E530DECE\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = NorFlashPlatformLib\r
+\r
+[Sources.common]\r
+ NorFlashQemuLib.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
--- /dev/null
+/** @file\r
+ Implementation for PlatformBdsLib library class interfaces.\r
+\r
+ Copyright (C) 2015, Red Hat, Inc.\r
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>\r
+ Copyright (c) 2004 - 2008, Intel Corporation. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials are licensed and made available\r
+ under the terms and conditions of the BSD License which accompanies this\r
+ distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <IndustryStandard/Pci22.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/PlatformBdsLib.h>\r
+#include <Library/QemuBootOrderLib.h>\r
+#include <Protocol/DevicePath.h>\r
+#include <Protocol/GraphicsOutput.h>\r
+#include <Protocol/PciIo.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+\r
+#include "IntelBdsPlatform.h"\r
+\r
+#define DP_NODE_LEN(Type) { (UINT8)sizeof (Type), (UINT8)(sizeof (Type) >> 8) }\r
+\r
+\r
+#pragma pack (1)\r
+typedef struct {\r
+ VENDOR_DEVICE_PATH SerialDxe;\r
+ UART_DEVICE_PATH Uart;\r
+ VENDOR_DEFINED_DEVICE_PATH Vt100;\r
+ EFI_DEVICE_PATH_PROTOCOL End;\r
+} PLATFORM_SERIAL_CONSOLE;\r
+#pragma pack ()\r
+\r
+#define SERIAL_DXE_FILE_GUID { \\r
+ 0xD3987D4B, 0x971A, 0x435F, \\r
+ { 0x8C, 0xAF, 0x49, 0x67, 0xEB, 0x62, 0x72, 0x41 } \\r
+ }\r
+\r
+STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = {\r
+ //\r
+ // VENDOR_DEVICE_PATH SerialDxe\r
+ //\r
+ {\r
+ { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH) },\r
+ SERIAL_DXE_FILE_GUID\r
+ },\r
+\r
+ //\r
+ // UART_DEVICE_PATH Uart\r
+ //\r
+ {\r
+ { MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) },\r
+ 0, // Reserved\r
+ FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate\r
+ FixedPcdGet8 (PcdUartDefaultDataBits), // DataBits\r
+ FixedPcdGet8 (PcdUartDefaultParity), // Parity\r
+ FixedPcdGet8 (PcdUartDefaultStopBits) // StopBits\r
+ },\r
+\r
+ //\r
+ // VENDOR_DEFINED_DEVICE_PATH Vt100\r
+ //\r
+ {\r
+ {\r
+ MESSAGING_DEVICE_PATH, MSG_VENDOR_DP,\r
+ DP_NODE_LEN (VENDOR_DEFINED_DEVICE_PATH)\r
+ },\r
+ EFI_VT_100_GUID\r
+ },\r
+\r
+ //\r
+ // EFI_DEVICE_PATH_PROTOCOL End\r
+ //\r
+ {\r
+ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
+ DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL)\r
+ }\r
+};\r
+\r
+\r
+#pragma pack (1)\r
+typedef struct {\r
+ USB_CLASS_DEVICE_PATH Keyboard;\r
+ EFI_DEVICE_PATH_PROTOCOL End;\r
+} PLATFORM_USB_KEYBOARD;\r
+#pragma pack ()\r
+\r
+STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard = {\r
+ //\r
+ // USB_CLASS_DEVICE_PATH Keyboard\r
+ //\r
+ {\r
+ {\r
+ MESSAGING_DEVICE_PATH, MSG_USB_CLASS_DP,\r
+ DP_NODE_LEN (USB_CLASS_DEVICE_PATH)\r
+ },\r
+ 0xFFFF, // VendorId: any\r
+ 0xFFFF, // ProductId: any\r
+ 3, // DeviceClass: HID\r
+ 1, // DeviceSubClass: boot\r
+ 1 // DeviceProtocol: keyboard\r
+ },\r
+\r
+ //\r
+ // EFI_DEVICE_PATH_PROTOCOL End\r
+ //\r
+ {\r
+ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
+ DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL)\r
+ }\r
+};\r
+\r
+\r
+//\r
+// BDS Platform Functions\r
+//\r
+/**\r
+ Platform Bds init. Include the platform firmware vendor, revision\r
+ and so crc check.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformBdsInit (\r
+ VOID\r
+ )\r
+{\r
+}\r
+\r
+\r
+/**\r
+ Check if the handle satisfies a particular condition.\r
+\r
+ @param[in] Handle The handle to check.\r
+ @param[in] ReportText A caller-allocated string passed in for reporting\r
+ purposes. It must never be NULL.\r
+\r
+ @retval TRUE The condition is satisfied.\r
+ @retval FALSE Otherwise. This includes the case when the condition could not\r
+ be fully evaluated due to an error.\r
+**/\r
+typedef\r
+BOOLEAN\r
+(EFIAPI *FILTER_FUNCTION) (\r
+ IN EFI_HANDLE Handle,\r
+ IN CONST CHAR16 *ReportText\r
+ );\r
+\r
+\r
+/**\r
+ Process a handle.\r
+\r
+ @param[in] Handle The handle to process.\r
+ @param[in] ReportText A caller-allocated string passed in for reporting\r
+ purposes. It must never be NULL.\r
+**/\r
+typedef\r
+VOID\r
+(EFIAPI *CALLBACK_FUNCTION) (\r
+ IN EFI_HANDLE Handle,\r
+ IN CONST CHAR16 *ReportText\r
+ );\r
+\r
+/**\r
+ Locate all handles that carry the specified protocol, filter them with a\r
+ callback function, and pass each handle that passes the filter to another\r
+ callback.\r
+\r
+ @param[in] ProtocolGuid The protocol to look for.\r
+\r
+ @param[in] Filter The filter function to pass each handle to. If this\r
+ parameter is NULL, then all handles are processed.\r
+\r
+ @param[in] Process The callback function to pass each handle to that\r
+ clears the filter.\r
+**/\r
+STATIC\r
+VOID\r
+FilterAndProcess (\r
+ IN EFI_GUID *ProtocolGuid,\r
+ IN FILTER_FUNCTION Filter OPTIONAL,\r
+ IN CALLBACK_FUNCTION Process\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_HANDLE *Handles;\r
+ UINTN NoHandles;\r
+ UINTN Idx;\r
+\r
+ Status = gBS->LocateHandleBuffer (ByProtocol, ProtocolGuid,\r
+ NULL /* SearchKey */, &NoHandles, &Handles);\r
+ if (EFI_ERROR (Status)) {\r
+ //\r
+ // This is not an error, just an informative condition.\r
+ //\r
+ DEBUG ((EFI_D_VERBOSE, "%a: %g: %r\n", __FUNCTION__, ProtocolGuid,\r
+ Status));\r
+ return;\r
+ }\r
+\r
+ ASSERT (NoHandles > 0);\r
+ for (Idx = 0; Idx < NoHandles; ++Idx) {\r
+ CHAR16 *DevicePathText;\r
+ STATIC CHAR16 Fallback[] = L"<device path unavailable>";\r
+\r
+ //\r
+ // The ConvertDevicePathToText() function handles NULL input transparently.\r
+ //\r
+ DevicePathText = ConvertDevicePathToText (\r
+ DevicePathFromHandle (Handles[Idx]),\r
+ FALSE, // DisplayOnly\r
+ FALSE // AllowShortcuts\r
+ );\r
+ if (DevicePathText == NULL) {\r
+ DevicePathText = Fallback;\r
+ }\r
+\r
+ if (Filter == NULL || Filter (Handles[Idx], DevicePathText)) {\r
+ Process (Handles[Idx], DevicePathText);\r
+ }\r
+\r
+ if (DevicePathText != Fallback) {\r
+ FreePool (DevicePathText);\r
+ }\r
+ }\r
+ gBS->FreePool (Handles);\r
+}\r
+\r
+\r
+/**\r
+ This FILTER_FUNCTION checks if a handle corresponds to a PCI display device.\r
+**/\r
+STATIC\r
+BOOLEAN\r
+EFIAPI\r
+IsPciDisplay (\r
+ IN EFI_HANDLE Handle,\r
+ IN CONST CHAR16 *ReportText\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ PCI_TYPE00 Pci;\r
+\r
+ Status = gBS->HandleProtocol (Handle, &gEfiPciIoProtocolGuid,\r
+ (VOID**)&PciIo);\r
+ if (EFI_ERROR (Status)) {\r
+ //\r
+ // This is not an error worth reporting.\r
+ //\r
+ return FALSE;\r
+ }\r
+\r
+ Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, 0 /* Offset */,\r
+ sizeof Pci / sizeof (UINT32), &Pci);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_ERROR, "%a: %s: %r\n", __FUNCTION__, ReportText, Status));\r
+ return FALSE;\r
+ }\r
+\r
+ return IS_PCI_DISPLAY (&Pci);\r
+}\r
+\r
+\r
+/**\r
+ This CALLBACK_FUNCTION attempts to connect a handle non-recursively, asking\r
+ the matching driver to produce all first-level child handles.\r
+**/\r
+STATIC\r
+VOID\r
+EFIAPI\r
+Connect (\r
+ IN EFI_HANDLE Handle,\r
+ IN CONST CHAR16 *ReportText\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ Status = gBS->ConnectController (\r
+ Handle, // ControllerHandle\r
+ NULL, // DriverImageHandle\r
+ NULL, // RemainingDevicePath -- produce all children\r
+ FALSE // Recursive\r
+ );\r
+ DEBUG ((EFI_ERROR (Status) ? EFI_D_ERROR : EFI_D_VERBOSE, "%a: %s: %r\n",\r
+ __FUNCTION__, ReportText, Status));\r
+}\r
+\r
+\r
+/**\r
+ This CALLBACK_FUNCTION retrieves the EFI_DEVICE_PATH_PROTOCOL from the\r
+ handle, and adds it to ConOut and ErrOut.\r
+**/\r
+STATIC\r
+VOID\r
+EFIAPI\r
+AddOutput (\r
+ IN EFI_HANDLE Handle,\r
+ IN CONST CHAR16 *ReportText\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+\r
+ DevicePath = DevicePathFromHandle (Handle);\r
+ if (DevicePath == NULL) {\r
+ DEBUG ((EFI_D_ERROR, "%a: %s: handle %p: device path not found\n",\r
+ __FUNCTION__, ReportText, Handle));\r
+ return;\r
+ }\r
+\r
+ Status = BdsLibUpdateConsoleVariable (L"ConOut", DevicePath, NULL);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_ERROR, "%a: %s: adding to ConOut: %r\n", __FUNCTION__,\r
+ ReportText, Status));\r
+ return;\r
+ }\r
+\r
+ Status = BdsLibUpdateConsoleVariable (L"ErrOut", DevicePath, NULL);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_ERROR, "%a: %s: adding to ErrOut: %r\n", __FUNCTION__,\r
+ ReportText, Status));\r
+ return;\r
+ }\r
+\r
+ DEBUG ((EFI_D_VERBOSE, "%a: %s: added to ConOut and ErrOut\n", __FUNCTION__,\r
+ ReportText));\r
+}\r
+\r
+\r
+/**\r
+ The function will execute with as the platform policy, current policy\r
+ is driven by boot mode. IBV/OEM can customize this code for their specific\r
+ policy action.\r
+\r
+ @param DriverOptionList The header of the driver option link list\r
+ @param BootOptionList The header of the boot option link list\r
+ @param ProcessCapsules A pointer to ProcessCapsules()\r
+ @param BaseMemoryTest A pointer to BaseMemoryTest()\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformBdsPolicyBehavior (\r
+ IN LIST_ENTRY *DriverOptionList,\r
+ IN LIST_ENTRY *BootOptionList,\r
+ IN PROCESS_CAPSULES ProcessCapsules,\r
+ IN BASEM_MEMORY_TEST BaseMemoryTest\r
+ )\r
+{\r
+ //\r
+ // Locate the PCI root bridges and make the PCI bus driver connect each,\r
+ // non-recursively. This will produce a number of child handles with PciIo on\r
+ // them.\r
+ //\r
+ FilterAndProcess (&gEfiPciRootBridgeIoProtocolGuid, NULL, Connect);\r
+\r
+ //\r
+ // Find all display class PCI devices (using the handles from the previous\r
+ // step), and connect them non-recursively. This should produce a number of\r
+ // child handles with GOPs on them.\r
+ //\r
+ FilterAndProcess (&gEfiPciIoProtocolGuid, IsPciDisplay, Connect);\r
+\r
+ //\r
+ // Now add the device path of all handles with GOP on them to ConOut and\r
+ // ErrOut.\r
+ //\r
+ FilterAndProcess (&gEfiGraphicsOutputProtocolGuid, NULL, AddOutput);\r
+\r
+ //\r
+ // Add the hardcoded short-form USB keyboard device path to ConIn.\r
+ //\r
+ BdsLibUpdateConsoleVariable (L"ConIn",\r
+ (EFI_DEVICE_PATH_PROTOCOL *)&mUsbKeyboard, NULL);\r
+\r
+ //\r
+ // Add the hardcoded serial console device path to ConIn, ConOut, ErrOut.\r
+ //\r
+ BdsLibUpdateConsoleVariable (L"ConIn",\r
+ (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);\r
+ BdsLibUpdateConsoleVariable (L"ConOut",\r
+ (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);\r
+ BdsLibUpdateConsoleVariable (L"ErrOut",\r
+ (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);\r
+\r
+ //\r
+ // Connect the consoles based on the above variables.\r
+ //\r
+ BdsLibConnectAllDefaultConsoles ();\r
+\r
+ //\r
+ // Show the splash screen.\r
+ //\r
+ EnableQuietBoot (PcdGetPtr (PcdLogoFile));\r
+\r
+ //\r
+ // Connect the rest of the devices.\r
+ //\r
+ BdsLibConnectAll ();\r
+\r
+ //\r
+ // Process QEMU's -kernel command line option. Note that the kernel booted\r
+ // this way should receive ACPI tables, which is why we connect all devices\r
+ // first (see above) -- PCI enumeration blocks ACPI table installation, if\r
+ // there is a PCI host.\r
+ //\r
+ TryRunningQemuKernel ();\r
+\r
+ BdsLibEnumerateAllBootOption (BootOptionList);\r
+ SetBootOrderFromQemu (BootOptionList);\r
+ //\r
+ // The BootOrder variable may have changed, reload the in-memory list with\r
+ // it.\r
+ //\r
+ BdsLibBuildOptionFromVar (BootOptionList, L"BootOrder");\r
+\r
+ PlatformBdsEnterFrontPage (GetFrontPageTimeoutFromQemu(), TRUE);\r
+}\r
+\r
+/**\r
+ Hook point after a boot attempt succeeds. We don't expect a boot option to\r
+ return, so the UEFI 2.0 specification defines that you will default to an\r
+ interactive mode and stop processing the BootOrder list in this case. This\r
+ is also a platform implementation and can be customized by IBV/OEM.\r
+\r
+ @param Option Pointer to Boot Option that succeeded to boot.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformBdsBootSuccess (\r
+ IN BDS_COMMON_OPTION *Option\r
+ )\r
+{\r
+}\r
+\r
+/**\r
+ Hook point after a boot attempt fails.\r
+\r
+ @param Option Pointer to Boot Option that failed to boot.\r
+ @param Status Status returned from failed boot.\r
+ @param ExitData Exit data returned from failed boot.\r
+ @param ExitDataSize Exit data size returned from failed boot.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformBdsBootFail (\r
+ IN BDS_COMMON_OPTION *Option,\r
+ IN EFI_STATUS Status,\r
+ IN CHAR16 *ExitData,\r
+ IN UINTN ExitDataSize\r
+ )\r
+{\r
+}\r
+\r
+/**\r
+ This function locks platform flash that is not allowed to be updated during normal boot path.\r
+ The flash layout is platform specific.\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformBdsLockNonUpdatableFlash (\r
+ VOID\r
+ )\r
+{\r
+ return;\r
+}\r
--- /dev/null
+/** @file\r
+ Head file for BDS Platform specific code\r
+\r
+ Copyright (c) 2004 - 2008, Intel Corporation. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials are licensed and made available\r
+ under the terms and conditions of the BSD License which accompanies this\r
+ distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _INTEL_BDS_PLATFORM_H_\r
+#define _INTEL_BDS_PLATFORM_H_\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+\r
+VOID\r
+PlatformBdsEnterFrontPage (\r
+ IN UINT16 TimeoutDefault,\r
+ IN BOOLEAN ConnectAllHappened\r
+ );\r
+\r
+/**\r
+ Download the kernel, the initial ramdisk, and the kernel command line from\r
+ QEMU's fw_cfg. Construct a minimal SimpleFileSystem that contains the two\r
+ image files, and load and start the kernel from it.\r
+\r
+ The kernel will be instructed via its command line to load the initrd from\r
+ the same Simple FileSystem.\r
+\r
+ @retval EFI_NOT_FOUND Kernel image was not found.\r
+ @retval EFI_OUT_OF_RESOURCES Memory allocation failed.\r
+ @retval EFI_PROTOCOL_ERROR Unterminated kernel command line.\r
+\r
+ @return Error codes from any of the underlying\r
+ functions. On success, the function doesn't\r
+ return.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+TryRunningQemuKernel (\r
+ VOID\r
+ );\r
+\r
+#endif // _INTEL_BDS_PLATFORM_H\r
--- /dev/null
+## @file\r
+# Implementation for PlatformBdsLib library class interfaces.\r
+#\r
+# Copyright (C) 2015, Red Hat, Inc.\r
+# Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials are licensed and made available\r
+# under the terms and conditions of the BSD License which accompanies this\r
+# distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR\r
+# IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PlatformIntelBdsLib\r
+ FILE_GUID = 46DF84EB-F603-4D39-99D8-E1E86B50BCC2\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = PlatformBdsLib|DXE_DRIVER\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = ARM AARCH64\r
+#\r
+\r
+[Sources]\r
+ IntelBdsPlatform.c\r
+ QemuKernel.c\r
+\r
+[Packages]\r
+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ MdePkg/MdePkg.dec\r
+ OvmfPkg/OvmfPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ BaseMemoryLib\r
+ DebugLib\r
+ DevicePathLib\r
+ GenericBdsLib\r
+ MemoryAllocationLib\r
+ PcdLib\r
+ PrintLib\r
+ QemuBootOrderLib\r
+ QemuFwCfgLib\r
+ UefiBootServicesTableLib\r
+ UefiRuntimeServicesTableLib\r
+\r
+[FixedPcd]\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits\r
+\r
+[Guids]\r
+ gEfiFileInfoGuid\r
+ gEfiFileSystemInfoGuid\r
+ gEfiFileSystemVolumeLabelInfoIdGuid\r
+\r
+[Protocols]\r
+ gEfiDevicePathProtocolGuid\r
+ gEfiGraphicsOutputProtocolGuid\r
+ gEfiLoadedImageProtocolGuid\r
+ gEfiPciRootBridgeIoProtocolGuid\r
+ gEfiSimpleFileSystemProtocolGuid\r
--- /dev/null
+/** @file\r
+ Try to load an EFI-stubbed ARM Linux kernel from QEMU's fw_cfg.\r
+\r
+ This implementation differs from OvmfPkg/Library/LoadLinuxLib. An EFI\r
+ stub in the subject kernel is a hard requirement here.\r
+\r
+ Copyright (C) 2014, Red Hat, Inc.\r
+\r
+ This program and the accompanying materials are licensed and made available\r
+ under the terms and conditions of the BSD License which accompanies this\r
+ distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+**/\r
+\r
+#include <Guid/FileInfo.h>\r
+#include <Guid/FileSystemInfo.h>\r
+#include <Guid/FileSystemVolumeLabelInfo.h>\r
+#include <Library/PrintLib.h>\r
+#include <Library/QemuFwCfgLib.h>\r
+#include <Protocol/DevicePath.h>\r
+#include <Protocol/LoadedImage.h>\r
+#include <Protocol/SimpleFileSystem.h>\r
+\r
+#include "IntelBdsPlatform.h"\r
+\r
+//\r
+// Static data that hosts the fw_cfg blobs and serves file requests.\r
+//\r
+typedef enum {\r
+ KernelBlobTypeKernel,\r
+ KernelBlobTypeInitrd,\r
+ KernelBlobTypeCommandLine,\r
+ KernelBlobTypeMax\r
+} KERNEL_BLOB_TYPE;\r
+\r
+typedef struct {\r
+ FIRMWARE_CONFIG_ITEM CONST SizeKey;\r
+ FIRMWARE_CONFIG_ITEM CONST DataKey;\r
+ CONST CHAR16 * CONST Name;\r
+ UINT32 Size;\r
+ UINT8 *Data;\r
+} KERNEL_BLOB;\r
+\r
+STATIC KERNEL_BLOB mKernelBlob[KernelBlobTypeMax] = {\r
+ { QemuFwCfgItemKernelSize, QemuFwCfgItemKernelData, L"kernel" },\r
+ { QemuFwCfgItemInitrdSize, QemuFwCfgItemInitrdData, L"initrd" },\r
+ { QemuFwCfgItemCommandLineSize, QemuFwCfgItemCommandLineData, L"cmdline" }\r
+};\r
+\r
+STATIC UINT64 mTotalBlobBytes;\r
+\r
+//\r
+// Device path for the handle that incorporates our "EFI stub filesystem". The\r
+// GUID is arbitrary and need not be standardized or advertized.\r
+//\r
+#pragma pack(1)\r
+typedef struct {\r
+ VENDOR_DEVICE_PATH VenHwNode;\r
+ EFI_DEVICE_PATH_PROTOCOL EndNode;\r
+} SINGLE_VENHW_NODE_DEVPATH;\r
+#pragma pack()\r
+\r
+STATIC CONST SINGLE_VENHW_NODE_DEVPATH mFileSystemDevicePath = {\r
+ {\r
+ { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH) } },\r
+ {\r
+ 0xb0fae7e7, 0x6b07, 0x49d0,\r
+ { 0x9e, 0x5b, 0x3b, 0xde, 0xc8, 0x3b, 0x03, 0x9d }\r
+ }\r
+ },\r
+\r
+ {\r
+ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
+ { sizeof (EFI_DEVICE_PATH_PROTOCOL) }\r
+ }\r
+};\r
+\r
+//\r
+// The "file in the EFI stub filesystem" abstraction.\r
+//\r
+STATIC EFI_TIME mInitTime;\r
+\r
+#define STUB_FILE_SIG SIGNATURE_64 ('S', 'T', 'U', 'B', 'F', 'I', 'L', 'E')\r
+\r
+typedef struct {\r
+ UINT64 Signature; // Carries STUB_FILE_SIG.\r
+\r
+ KERNEL_BLOB_TYPE BlobType; // Index into mKernelBlob. KernelBlobTypeMax\r
+ // denotes the root directory of the filesystem.\r
+\r
+ UINT64 Position; // Byte position for regular files;\r
+ // next directory entry to return for the root\r
+ // directory.\r
+\r
+ EFI_FILE_PROTOCOL File; // Standard protocol interface.\r
+} STUB_FILE;\r
+\r
+#define STUB_FILE_FROM_FILE(FilePointer) \\r
+ CR (FilePointer, STUB_FILE, File, STUB_FILE_SIG)\r
+\r
+//\r
+// Tentative definition of the file protocol template. The initializer\r
+// (external definition) will be provided later.\r
+//\r
+STATIC CONST EFI_FILE_PROTOCOL mEfiFileProtocolTemplate;\r
+\r
+\r
+//\r
+// Protocol member functions for File.\r
+//\r
+\r
+/**\r
+ Opens a new file relative to the source file's location.\r
+\r
+ @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that is\r
+ the file handle to the source location. This would\r
+ typically be an open handle to a directory.\r
+\r
+ @param[out] NewHandle A pointer to the location to return the opened handle\r
+ for the new file.\r
+\r
+ @param[in] FileName The Null-terminated string of the name of the file to\r
+ be opened. The file name may contain the following\r
+ path modifiers: "\", ".", and "..".\r
+\r
+ @param[in] OpenMode The mode to open the file. The only valid\r
+ combinations that the file may be opened with are:\r
+ Read, Read/Write, or Create/Read/Write.\r
+\r
+ @param[in] Attributes Only valid for EFI_FILE_MODE_CREATE, in which case\r
+ these are the attribute bits for the newly created\r
+ file.\r
+\r
+ @retval EFI_SUCCESS The file was opened.\r
+ @retval EFI_NOT_FOUND The specified file could not be found on the\r
+ device.\r
+ @retval EFI_NO_MEDIA The device has no medium.\r
+ @retval EFI_MEDIA_CHANGED The device has a different medium in it or the\r
+ medium is no longer supported.\r
+ @retval EFI_DEVICE_ERROR The device reported an error.\r
+ @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted.\r
+ @retval EFI_WRITE_PROTECTED An attempt was made to create a file, or open a\r
+ file for write when the media is\r
+ write-protected.\r
+ @retval EFI_ACCESS_DENIED The service denied access to the file.\r
+ @retval EFI_OUT_OF_RESOURCES Not enough resources were available to open the\r
+ file.\r
+ @retval EFI_VOLUME_FULL The volume is full.\r
+**/\r
+STATIC\r
+EFI_STATUS\r
+EFIAPI\r
+StubFileOpen (\r
+ IN EFI_FILE_PROTOCOL *This,\r
+ OUT EFI_FILE_PROTOCOL **NewHandle,\r
+ IN CHAR16 *FileName,\r
+ IN UINT64 OpenMode,\r
+ IN UINT64 Attributes\r
+ )\r
+{\r
+ CONST STUB_FILE *StubFile;\r
+ UINTN BlobType;\r
+ STUB_FILE *NewStubFile;\r
+\r
+ //\r
+ // We're read-only.\r
+ //\r
+ switch (OpenMode) {\r
+ case EFI_FILE_MODE_READ:\r
+ break;\r
+\r
+ case EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE:\r
+ case EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE | EFI_FILE_MODE_CREATE:\r
+ return EFI_WRITE_PROTECTED;\r
+\r
+ default:\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Only the root directory supports opening files in it.\r
+ //\r
+ StubFile = STUB_FILE_FROM_FILE (This);\r
+ if (StubFile->BlobType != KernelBlobTypeMax) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ //\r
+ // Locate the file.\r
+ //\r
+ for (BlobType = 0; BlobType < KernelBlobTypeMax; ++BlobType) {\r
+ if (StrCmp (FileName, mKernelBlob[BlobType].Name) == 0) {\r
+ break;\r
+ }\r
+ }\r
+ if (BlobType == KernelBlobTypeMax) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ //\r
+ // Found it.\r
+ //\r
+ NewStubFile = AllocatePool (sizeof *NewStubFile);\r
+ if (NewStubFile == NULL) {\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+\r
+ NewStubFile->Signature = STUB_FILE_SIG;\r
+ NewStubFile->BlobType = (KERNEL_BLOB_TYPE)BlobType;\r
+ NewStubFile->Position = 0;\r
+ CopyMem (&NewStubFile->File, &mEfiFileProtocolTemplate,\r
+ sizeof mEfiFileProtocolTemplate);\r
+ *NewHandle = &NewStubFile->File;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Closes a specified file handle.\r
+\r
+ @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that is the file\r
+ handle to close.\r
+\r
+ @retval EFI_SUCCESS The file was closed.\r
+**/\r
+STATIC\r
+EFI_STATUS\r
+EFIAPI\r
+StubFileClose (\r
+ IN EFI_FILE_PROTOCOL *This\r
+ )\r
+{\r
+ FreePool (STUB_FILE_FROM_FILE (This));\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Close and delete the file handle.\r
+\r
+ @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that is the\r
+ handle to the file to delete.\r
+\r
+ @retval EFI_SUCCESS The file was closed and deleted, and the\r
+ handle was closed.\r
+ @retval EFI_WARN_DELETE_FAILURE The handle was closed, but the file was not\r
+ deleted.\r
+\r
+**/\r
+STATIC\r
+EFI_STATUS\r
+EFIAPI\r
+StubFileDelete (\r
+ IN EFI_FILE_PROTOCOL *This\r
+ )\r
+{\r
+ FreePool (STUB_FILE_FROM_FILE (This));\r
+ return EFI_WARN_DELETE_FAILURE;\r
+}\r
+\r
+\r
+/**\r
+ Helper function that formats an EFI_FILE_INFO structure into the\r
+ user-allocated buffer, for any valid KERNEL_BLOB_TYPE value (including\r
+ KernelBlobTypeMax, which stands for the root directory).\r
+\r
+ The interface follows the EFI_FILE_GET_INFO -- and for directories, the\r
+ EFI_FILE_READ -- interfaces.\r
+\r
+ @param[in] BlobType The KERNEL_BLOB_TYPE value identifying the fw_cfg\r
+ blob backing the STUB_FILE that information is\r
+ being requested about. If BlobType equals\r
+ KernelBlobTypeMax, then information will be\r
+ provided about the root directory of the\r
+ filesystem.\r
+\r
+ @param[in,out] BufferSize On input, the size of Buffer. On output, the\r
+ amount of data returned in Buffer. In both cases,\r
+ the size is measured in bytes.\r
+\r
+ @param[out] Buffer A pointer to the data buffer to return. The\r
+ buffer's type is EFI_FILE_INFO.\r
+\r
+ @retval EFI_SUCCESS The information was returned.\r
+ @retval EFI_BUFFER_TOO_SMALL BufferSize is too small to store the\r
+ EFI_FILE_INFO structure. BufferSize has been\r
+ updated with the size needed to complete the\r
+ request.\r
+**/\r
+STATIC\r
+EFI_STATUS\r
+ConvertKernelBlobTypeToFileInfo (\r
+ IN KERNEL_BLOB_TYPE BlobType,\r
+ IN OUT UINTN *BufferSize,\r
+ OUT VOID *Buffer\r
+ )\r
+{\r
+ CONST CHAR16 *Name;\r
+ UINT64 FileSize;\r
+ UINT64 Attribute;\r
+\r
+ UINTN NameSize;\r
+ UINTN FileInfoSize;\r
+ EFI_FILE_INFO *FileInfo;\r
+ UINTN OriginalBufferSize;\r
+\r
+ if (BlobType == KernelBlobTypeMax) {\r
+ //\r
+ // getting file info about the root directory\r
+ //\r
+ Name = L"\\";\r
+ FileSize = KernelBlobTypeMax;\r
+ Attribute = EFI_FILE_READ_ONLY | EFI_FILE_DIRECTORY;\r
+ } else {\r
+ CONST KERNEL_BLOB *Blob;\r
+\r
+ Blob = &mKernelBlob[BlobType];\r
+ Name = Blob->Name;\r
+ FileSize = Blob->Size;\r
+ Attribute = EFI_FILE_READ_ONLY;\r
+ }\r
+\r
+ NameSize = (StrLen(Name) + 1) * 2;\r
+ FileInfoSize = OFFSET_OF (EFI_FILE_INFO, FileName) + NameSize;\r
+ ASSERT (FileInfoSize >= sizeof *FileInfo);\r
+\r
+ OriginalBufferSize = *BufferSize;\r
+ *BufferSize = FileInfoSize;\r
+ if (OriginalBufferSize < *BufferSize) {\r
+ return EFI_BUFFER_TOO_SMALL;\r
+ }\r
+\r
+ FileInfo = (EFI_FILE_INFO *)Buffer;\r
+ FileInfo->Size = FileInfoSize;\r
+ FileInfo->FileSize = FileSize;\r
+ FileInfo->PhysicalSize = FileSize;\r
+ FileInfo->Attribute = Attribute;\r
+\r
+ CopyMem (&FileInfo->CreateTime, &mInitTime, sizeof mInitTime);\r
+ CopyMem (&FileInfo->LastAccessTime, &mInitTime, sizeof mInitTime);\r
+ CopyMem (&FileInfo->ModificationTime, &mInitTime, sizeof mInitTime);\r
+ CopyMem (FileInfo->FileName, Name, NameSize);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Reads data from a file, or continues scanning a directory.\r
+\r
+ @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that\r
+ is the file handle to read data from.\r
+\r
+ @param[in,out] BufferSize On input, the size of the Buffer. On output, the\r
+ amount of data returned in Buffer. In both cases,\r
+ the size is measured in bytes. If the read goes\r
+ beyond the end of the file, the read length is\r
+ truncated to the end of the file.\r
+\r
+ If This is a directory, the function reads the\r
+ directory entry at the current position and\r
+ returns the entry (as EFI_FILE_INFO) in Buffer. If\r
+ there are no more directory entries, the\r
+ BufferSize is set to zero on output.\r
+\r
+ @param[out] Buffer The buffer into which the data is read.\r
+\r
+ @retval EFI_SUCCESS Data was read.\r
+ @retval EFI_NO_MEDIA The device has no medium.\r
+ @retval EFI_DEVICE_ERROR The device reported an error.\r
+ @retval EFI_DEVICE_ERROR An attempt was made to read from a deleted\r
+ file.\r
+ @retval EFI_DEVICE_ERROR On entry, the current file position is beyond\r
+ the end of the file.\r
+ @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted.\r
+ @retval EFI_BUFFER_TOO_SMALL The BufferSize is too small to store the\r
+ current directory entry as a EFI_FILE_INFO\r
+ structure. BufferSize has been updated with the\r
+ size needed to complete the request, and the\r
+ directory position has not been advanced.\r
+**/\r
+STATIC\r
+EFI_STATUS\r
+EFIAPI\r
+StubFileRead (\r
+ IN EFI_FILE_PROTOCOL *This,\r
+ IN OUT UINTN *BufferSize,\r
+ OUT VOID *Buffer\r
+ )\r
+{\r
+ STUB_FILE *StubFile;\r
+ CONST KERNEL_BLOB *Blob;\r
+ UINT64 Left;\r
+\r
+ StubFile = STUB_FILE_FROM_FILE (This);\r
+\r
+ //\r
+ // Scanning the root directory?\r
+ //\r
+ if (StubFile->BlobType == KernelBlobTypeMax) {\r
+ EFI_STATUS Status;\r
+\r
+ if (StubFile->Position == KernelBlobTypeMax) {\r
+ //\r
+ // Scanning complete.\r
+ //\r
+ *BufferSize = 0;\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ Status = ConvertKernelBlobTypeToFileInfo (StubFile->Position, BufferSize,\r
+ Buffer);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ ++StubFile->Position;\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ //\r
+ // Reading a file.\r
+ //\r
+ Blob = &mKernelBlob[StubFile->BlobType];\r
+ if (StubFile->Position > Blob->Size) {\r
+ return EFI_DEVICE_ERROR;\r
+ }\r
+\r
+ Left = Blob->Size - StubFile->Position;\r
+ if (*BufferSize > Left) {\r
+ *BufferSize = (UINTN)Left;\r
+ }\r
+ if (Blob->Data != NULL) {\r
+ CopyMem (Buffer, Blob->Data + StubFile->Position, *BufferSize);\r
+ }\r
+ StubFile->Position += *BufferSize;\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Writes data to a file.\r
+\r
+ @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that\r
+ is the file handle to write data to.\r
+\r
+ @param[in,out] BufferSize On input, the size of the Buffer. On output, the\r
+ amount of data actually written. In both cases,\r
+ the size is measured in bytes.\r
+\r
+ @param[in] Buffer The buffer of data to write.\r
+\r
+ @retval EFI_SUCCESS Data was written.\r
+ @retval EFI_UNSUPPORTED Writes to open directory files are not\r
+ supported.\r
+ @retval EFI_NO_MEDIA The device has no medium.\r
+ @retval EFI_DEVICE_ERROR The device reported an error.\r
+ @retval EFI_DEVICE_ERROR An attempt was made to write to a deleted file.\r
+ @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted.\r
+ @retval EFI_WRITE_PROTECTED The file or medium is write-protected.\r
+ @retval EFI_ACCESS_DENIED The file was opened read only.\r
+ @retval EFI_VOLUME_FULL The volume is full.\r
+**/\r
+STATIC\r
+EFI_STATUS\r
+EFIAPI\r
+StubFileWrite (\r
+ IN EFI_FILE_PROTOCOL *This,\r
+ IN OUT UINTN *BufferSize,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ STUB_FILE *StubFile;\r
+\r
+ StubFile = STUB_FILE_FROM_FILE (This);\r
+ return (StubFile->BlobType == KernelBlobTypeMax) ?\r
+ EFI_UNSUPPORTED :\r
+ EFI_WRITE_PROTECTED;\r
+}\r
+\r
+\r
+/**\r
+ Returns a file's current position.\r
+\r
+ @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that is the\r
+ file handle to get the current position on.\r
+\r
+ @param[out] Position The address to return the file's current position\r
+ value.\r
+\r
+ @retval EFI_SUCCESS The position was returned.\r
+ @retval EFI_UNSUPPORTED The request is not valid on open directories.\r
+ @retval EFI_DEVICE_ERROR An attempt was made to get the position from a\r
+ deleted file.\r
+**/\r
+STATIC\r
+EFI_STATUS\r
+EFIAPI\r
+StubFileGetPosition (\r
+ IN EFI_FILE_PROTOCOL *This,\r
+ OUT UINT64 *Position\r
+ )\r
+{\r
+ STUB_FILE *StubFile;\r
+\r
+ StubFile = STUB_FILE_FROM_FILE (This);\r
+ if (StubFile->BlobType == KernelBlobTypeMax) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ *Position = StubFile->Position;\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Sets a file's current position.\r
+\r
+ @param[in] This A pointer to the EFI_FILE_PROTOCOL instance that is the\r
+ file handle to set the requested position on.\r
+\r
+ @param[in] Position The byte position from the start of the file to set. For\r
+ regular files, MAX_UINT64 means "seek to end". For\r
+ directories, zero means "rewind directory scan".\r
+\r
+ @retval EFI_SUCCESS The position was set.\r
+ @retval EFI_UNSUPPORTED The seek request for nonzero is not valid on open\r
+ directories.\r
+ @retval EFI_DEVICE_ERROR An attempt was made to set the position of a\r
+ deleted file.\r
+**/\r
+STATIC\r
+EFI_STATUS\r
+EFIAPI\r
+StubFileSetPosition (\r
+ IN EFI_FILE_PROTOCOL *This,\r
+ IN UINT64 Position\r
+ )\r
+{\r
+ STUB_FILE *StubFile;\r
+ KERNEL_BLOB *Blob;\r
+\r
+ StubFile = STUB_FILE_FROM_FILE (This);\r
+\r
+ if (StubFile->BlobType == KernelBlobTypeMax) {\r
+ if (Position == 0) {\r
+ //\r
+ // rewinding a directory scan is allowed\r
+ //\r
+ StubFile->Position = 0;\r
+ return EFI_SUCCESS;\r
+ }\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ //\r
+ // regular file seek\r
+ //\r
+ Blob = &mKernelBlob[StubFile->BlobType];\r
+ if (Position == MAX_UINT64) {\r
+ //\r
+ // seek to end\r
+ //\r
+ StubFile->Position = Blob->Size;\r
+ } else {\r
+ //\r
+ // absolute seek from beginning -- seeking past the end is allowed\r
+ //\r
+ StubFile->Position = Position;\r
+ }\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Returns information about a file.\r
+\r
+ @param[in] This A pointer to the EFI_FILE_PROTOCOL instance\r
+ that is the file handle the requested\r
+ information is for.\r
+\r
+ @param[in] InformationType The type identifier GUID for the information\r
+ being requested. The following information\r
+ types are supported, storing the\r
+ corresponding structures in Buffer:\r
+\r
+ - gEfiFileInfoGuid: EFI_FILE_INFO\r
+\r
+ - gEfiFileSystemInfoGuid:\r
+ EFI_FILE_SYSTEM_INFO\r
+\r
+ - gEfiFileSystemVolumeLabelInfoIdGuid:\r
+ EFI_FILE_SYSTEM_VOLUME_LABEL\r
+\r
+ @param[in,out] BufferSize On input, the size of Buffer. On output, the\r
+ amount of data returned in Buffer. In both\r
+ cases, the size is measured in bytes.\r
+\r
+ @param[out] Buffer A pointer to the data buffer to return. The\r
+ buffer's type is indicated by\r
+ InformationType.\r
+\r
+ @retval EFI_SUCCESS The information was returned.\r
+ @retval EFI_UNSUPPORTED The InformationType is not known.\r
+ @retval EFI_NO_MEDIA The device has no medium.\r
+ @retval EFI_DEVICE_ERROR The device reported an error.\r
+ @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted.\r
+ @retval EFI_BUFFER_TOO_SMALL The BufferSize is too small to store the\r
+ information structure requested by\r
+ InformationType. BufferSize has been updated\r
+ with the size needed to complete the request.\r
+**/\r
+STATIC\r
+EFI_STATUS\r
+EFIAPI\r
+StubFileGetInfo (\r
+ IN EFI_FILE_PROTOCOL *This,\r
+ IN EFI_GUID *InformationType,\r
+ IN OUT UINTN *BufferSize,\r
+ OUT VOID *Buffer\r
+ )\r
+{\r
+ CONST STUB_FILE *StubFile;\r
+ UINTN OriginalBufferSize;\r
+\r
+ StubFile = STUB_FILE_FROM_FILE (This);\r
+\r
+ if (CompareGuid (InformationType, &gEfiFileInfoGuid)) {\r
+ return ConvertKernelBlobTypeToFileInfo (StubFile->BlobType, BufferSize,\r
+ Buffer);\r
+ }\r
+\r
+ OriginalBufferSize = *BufferSize;\r
+\r
+ if (CompareGuid (InformationType, &gEfiFileSystemInfoGuid)) {\r
+ EFI_FILE_SYSTEM_INFO *FileSystemInfo;\r
+\r
+ *BufferSize = sizeof *FileSystemInfo;\r
+ if (OriginalBufferSize < *BufferSize) {\r
+ return EFI_BUFFER_TOO_SMALL;\r
+ }\r
+\r
+ FileSystemInfo = (EFI_FILE_SYSTEM_INFO *)Buffer;\r
+ FileSystemInfo->Size = sizeof *FileSystemInfo;\r
+ FileSystemInfo->ReadOnly = TRUE;\r
+ FileSystemInfo->VolumeSize = mTotalBlobBytes;\r
+ FileSystemInfo->FreeSpace = 0;\r
+ FileSystemInfo->BlockSize = 1;\r
+ FileSystemInfo->VolumeLabel[0] = L'\0';\r
+\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ if (CompareGuid (InformationType, &gEfiFileSystemVolumeLabelInfoIdGuid)) {\r
+ EFI_FILE_SYSTEM_VOLUME_LABEL *FileSystemVolumeLabel;\r
+\r
+ *BufferSize = sizeof *FileSystemVolumeLabel;\r
+ if (OriginalBufferSize < *BufferSize) {\r
+ return EFI_BUFFER_TOO_SMALL;\r
+ }\r
+\r
+ FileSystemVolumeLabel = (EFI_FILE_SYSTEM_VOLUME_LABEL *)Buffer;\r
+ FileSystemVolumeLabel->VolumeLabel[0] = L'\0';\r
+\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+/**\r
+ Sets information about a file.\r
+\r
+ @param[in] File A pointer to the EFI_FILE_PROTOCOL instance that\r
+ is the file handle the information is for.\r
+\r
+ @param[in] InformationType The type identifier for the information being\r
+ set.\r
+\r
+ @param[in] BufferSize The size, in bytes, of Buffer.\r
+\r
+ @param[in] Buffer A pointer to the data buffer to write. The\r
+ buffer's type is indicated by InformationType.\r
+\r
+ @retval EFI_SUCCESS The information was set.\r
+ @retval EFI_UNSUPPORTED The InformationType is not known.\r
+ @retval EFI_NO_MEDIA The device has no medium.\r
+ @retval EFI_DEVICE_ERROR The device reported an error.\r
+ @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted.\r
+ @retval EFI_WRITE_PROTECTED InformationType is EFI_FILE_INFO_ID and the\r
+ media is read-only.\r
+ @retval EFI_WRITE_PROTECTED InformationType is\r
+ EFI_FILE_PROTOCOL_SYSTEM_INFO_ID and the media\r
+ is read only.\r
+ @retval EFI_WRITE_PROTECTED InformationType is\r
+ EFI_FILE_SYSTEM_VOLUME_LABEL_ID and the media\r
+ is read-only.\r
+ @retval EFI_ACCESS_DENIED An attempt is made to change the name of a file\r
+ to a file that is already present.\r
+ @retval EFI_ACCESS_DENIED An attempt is being made to change the\r
+ EFI_FILE_DIRECTORY Attribute.\r
+ @retval EFI_ACCESS_DENIED An attempt is being made to change the size of\r
+ a directory.\r
+ @retval EFI_ACCESS_DENIED InformationType is EFI_FILE_INFO_ID and the\r
+ file was opened read-only and an attempt is\r
+ being made to modify a field other than\r
+ Attribute.\r
+ @retval EFI_VOLUME_FULL The volume is full.\r
+ @retval EFI_BAD_BUFFER_SIZE BufferSize is smaller than the size of the type\r
+ indicated by InformationType.\r
+**/\r
+STATIC\r
+EFI_STATUS\r
+EFIAPI\r
+StubFileSetInfo (\r
+ IN EFI_FILE_PROTOCOL *This,\r
+ IN EFI_GUID *InformationType,\r
+ IN UINTN BufferSize,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ return EFI_WRITE_PROTECTED;\r
+}\r
+\r
+\r
+/**\r
+ Flushes all modified data associated with a file to a device.\r
+\r
+ @param [in] This A pointer to the EFI_FILE_PROTOCOL instance that is the\r
+ file handle to flush.\r
+\r
+ @retval EFI_SUCCESS The data was flushed.\r
+ @retval EFI_NO_MEDIA The device has no medium.\r
+ @retval EFI_DEVICE_ERROR The device reported an error.\r
+ @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted.\r
+ @retval EFI_WRITE_PROTECTED The file or medium is write-protected.\r
+ @retval EFI_ACCESS_DENIED The file was opened read-only.\r
+ @retval EFI_VOLUME_FULL The volume is full.\r
+**/\r
+STATIC\r
+EFI_STATUS\r
+EFIAPI\r
+StubFileFlush (\r
+ IN EFI_FILE_PROTOCOL *This\r
+ )\r
+{\r
+ return EFI_WRITE_PROTECTED;\r
+}\r
+\r
+//\r
+// External definition of the file protocol template.\r
+//\r
+STATIC CONST EFI_FILE_PROTOCOL mEfiFileProtocolTemplate = {\r
+ EFI_FILE_PROTOCOL_REVISION, // revision 1\r
+ StubFileOpen,\r
+ StubFileClose,\r
+ StubFileDelete,\r
+ StubFileRead,\r
+ StubFileWrite,\r
+ StubFileGetPosition,\r
+ StubFileSetPosition,\r
+ StubFileGetInfo,\r
+ StubFileSetInfo,\r
+ StubFileFlush,\r
+ NULL, // OpenEx, revision 2\r
+ NULL, // ReadEx, revision 2\r
+ NULL, // WriteEx, revision 2\r
+ NULL // FlushEx, revision 2\r
+};\r
+\r
+\r
+//\r
+// Protocol member functions for SimpleFileSystem.\r
+//\r
+\r
+/**\r
+ Open the root directory on a volume.\r
+\r
+ @param[in] This A pointer to the volume to open the root directory on.\r
+\r
+ @param[out] Root A pointer to the location to return the opened file handle\r
+ for the root directory in.\r
+\r
+ @retval EFI_SUCCESS The device was opened.\r
+ @retval EFI_UNSUPPORTED This volume does not support the requested file\r
+ system type.\r
+ @retval EFI_NO_MEDIA The device has no medium.\r
+ @retval EFI_DEVICE_ERROR The device reported an error.\r
+ @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted.\r
+ @retval EFI_ACCESS_DENIED The service denied access to the file.\r
+ @retval EFI_OUT_OF_RESOURCES The volume was not opened due to lack of\r
+ resources.\r
+ @retval EFI_MEDIA_CHANGED The device has a different medium in it or the\r
+ medium is no longer supported. Any existing\r
+ file handles for this volume are no longer\r
+ valid. To access the files on the new medium,\r
+ the volume must be reopened with OpenVolume().\r
+**/\r
+STATIC\r
+EFI_STATUS\r
+EFIAPI\r
+StubFileSystemOpenVolume (\r
+ IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This,\r
+ OUT EFI_FILE_PROTOCOL **Root\r
+ )\r
+{\r
+ STUB_FILE *StubFile;\r
+\r
+ StubFile = AllocatePool (sizeof *StubFile);\r
+ if (StubFile == NULL) {\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+\r
+ StubFile->Signature = STUB_FILE_SIG;\r
+ StubFile->BlobType = KernelBlobTypeMax;\r
+ StubFile->Position = 0;\r
+ CopyMem (&StubFile->File, &mEfiFileProtocolTemplate,\r
+ sizeof mEfiFileProtocolTemplate);\r
+ *Root = &StubFile->File;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+STATIC CONST EFI_SIMPLE_FILE_SYSTEM_PROTOCOL mFileSystem = {\r
+ EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION,\r
+ StubFileSystemOpenVolume\r
+};\r
+\r
+\r
+//\r
+// Utility functions.\r
+//\r
+\r
+/**\r
+ Populate a blob in mKernelBlob.\r
+\r
+ param[in,out] Blob Pointer to the KERNEL_BLOB element in mKernelBlob that is\r
+ to be filled from fw_cfg.\r
+\r
+ @retval EFI_SUCCESS Blob has been populated. If fw_cfg reported a\r
+ size of zero for the blob, then Blob->Data has\r
+ been left unchanged.\r
+\r
+ @retval EFI_OUT_OF_RESOURCES Failed to allocate memory for Blob->Data.\r
+**/\r
+STATIC\r
+EFI_STATUS\r
+FetchBlob (\r
+ IN OUT KERNEL_BLOB *Blob\r
+ )\r
+{\r
+ UINT32 Left;\r
+\r
+ //\r
+ // Read blob size.\r
+ //\r
+ QemuFwCfgSelectItem (Blob->SizeKey);\r
+ Blob->Size = QemuFwCfgRead32 ();\r
+ if (Blob->Size == 0) {\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ //\r
+ // Read blob.\r
+ //\r
+ Blob->Data = AllocatePool (Blob->Size);\r
+ if (Blob->Data == NULL) {\r
+ DEBUG ((EFI_D_ERROR, "%a: failed to allocate %Ld bytes for \"%s\"\n",\r
+ __FUNCTION__, (INT64)Blob->Size, Blob->Name));\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+\r
+ DEBUG ((EFI_D_INFO, "%a: loading %Ld bytes for \"%s\"\n", __FUNCTION__,\r
+ (INT64)Blob->Size, Blob->Name));\r
+ QemuFwCfgSelectItem (Blob->DataKey);\r
+\r
+ Left = Blob->Size;\r
+ do {\r
+ UINT32 Chunk;\r
+\r
+ Chunk = (Left < SIZE_1MB) ? Left : SIZE_1MB;\r
+ QemuFwCfgReadBytes (Chunk, Blob->Data + (Blob->Size - Left));\r
+ Left -= Chunk;\r
+ DEBUG ((EFI_D_VERBOSE, "%a: %Ld bytes remaining for \"%s\"\n",\r
+ __FUNCTION__, (INT64)Left, Blob->Name));\r
+ } while (Left > 0);\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+//\r
+// The entry point of the feature.\r
+//\r
+\r
+/**\r
+ Download the kernel, the initial ramdisk, and the kernel command line from\r
+ QEMU's fw_cfg. Construct a minimal SimpleFileSystem that contains the two\r
+ image files, and load and start the kernel from it.\r
+\r
+ The kernel will be instructed via its command line to load the initrd from\r
+ the same Simple FileSystem.\r
+\r
+ @retval EFI_NOT_FOUND Kernel image was not found.\r
+ @retval EFI_OUT_OF_RESOURCES Memory allocation failed.\r
+ @retval EFI_PROTOCOL_ERROR Unterminated kernel command line.\r
+\r
+ @return Error codes from any of the underlying\r
+ functions. On success, the function doesn't\r
+ return.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+TryRunningQemuKernel (\r
+ VOID\r
+ )\r
+{\r
+ UINTN BlobType;\r
+ KERNEL_BLOB *CurrentBlob;\r
+ KERNEL_BLOB *KernelBlob, *InitrdBlob, *CommandLineBlob;\r
+ EFI_STATUS Status;\r
+ EFI_HANDLE FileSystemHandle;\r
+ EFI_DEVICE_PATH_PROTOCOL *KernelDevicePath;\r
+ EFI_HANDLE KernelImageHandle;\r
+ EFI_LOADED_IMAGE_PROTOCOL *KernelLoadedImage;\r
+\r
+ Status = gRT->GetTime (&mInitTime, NULL /* Capabilities */);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_ERROR, "%a: GetTime(): %r\n", __FUNCTION__, Status));\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // Fetch all blobs.\r
+ //\r
+ for (BlobType = 0; BlobType < KernelBlobTypeMax; ++BlobType) {\r
+ CurrentBlob = &mKernelBlob[BlobType];\r
+ Status = FetchBlob (CurrentBlob);\r
+ if (EFI_ERROR (Status)) {\r
+ goto FreeBlobs;\r
+ }\r
+ mTotalBlobBytes += CurrentBlob->Size;\r
+ }\r
+ KernelBlob = &mKernelBlob[KernelBlobTypeKernel];\r
+ InitrdBlob = &mKernelBlob[KernelBlobTypeInitrd];\r
+ CommandLineBlob = &mKernelBlob[KernelBlobTypeCommandLine];\r
+\r
+ if (KernelBlob->Data == NULL) {\r
+ Status = EFI_NOT_FOUND;\r
+ goto FreeBlobs;\r
+ }\r
+\r
+ //\r
+ // Create a new handle with a single VenHw() node device path protocol on it,\r
+ // plus a custom SimpleFileSystem protocol on it.\r
+ //\r
+ FileSystemHandle = NULL;\r
+ Status = gBS->InstallMultipleProtocolInterfaces (&FileSystemHandle,\r
+ &gEfiDevicePathProtocolGuid, &mFileSystemDevicePath,\r
+ &gEfiSimpleFileSystemProtocolGuid, &mFileSystem,\r
+ NULL);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_ERROR, "%a: InstallMultipleProtocolInterfaces(): %r\n",\r
+ __FUNCTION__, Status));\r
+ goto FreeBlobs;\r
+ }\r
+\r
+ //\r
+ // Create a device path for the kernel image to be loaded from that will call\r
+ // back into our file system.\r
+ //\r
+ KernelDevicePath = FileDevicePath (FileSystemHandle, KernelBlob->Name);\r
+ if (KernelDevicePath == NULL) {\r
+ DEBUG ((EFI_D_ERROR, "%a: failed to allocate kernel device path\n",\r
+ __FUNCTION__));\r
+ Status = EFI_OUT_OF_RESOURCES;\r
+ goto UninstallProtocols;\r
+ }\r
+\r
+ //\r
+ // Load the image. This should call back into our file system.\r
+ //\r
+ Status = gBS->LoadImage (\r
+ FALSE, // BootPolicy: exact match required\r
+ gImageHandle, // ParentImageHandle\r
+ KernelDevicePath,\r
+ NULL, // SourceBuffer\r
+ 0, // SourceSize\r
+ &KernelImageHandle\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_ERROR, "%a: LoadImage(): %r\n", __FUNCTION__, Status));\r
+ goto FreeKernelDevicePath;\r
+ }\r
+\r
+ //\r
+ // Construct the kernel command line.\r
+ //\r
+ Status = gBS->OpenProtocol (\r
+ KernelImageHandle,\r
+ &gEfiLoadedImageProtocolGuid,\r
+ (VOID **)&KernelLoadedImage,\r
+ gImageHandle, // AgentHandle\r
+ NULL, // ControllerHandle\r
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ if (CommandLineBlob->Data == NULL) {\r
+ KernelLoadedImage->LoadOptionsSize = 0;\r
+ } else {\r
+ //\r
+ // Verify NUL-termination of the command line.\r
+ //\r
+ if (CommandLineBlob->Data[CommandLineBlob->Size - 1] != '\0') {\r
+ DEBUG ((EFI_D_ERROR, "%a: kernel command line is not NUL-terminated\n",\r
+ __FUNCTION__));\r
+ Status = EFI_PROTOCOL_ERROR;\r
+ goto UnloadKernelImage;\r
+ }\r
+\r
+ //\r
+ // Drop the terminating NUL, convert to UTF-16.\r
+ //\r
+ KernelLoadedImage->LoadOptionsSize = (CommandLineBlob->Size - 1) * 2;\r
+ }\r
+\r
+ if (InitrdBlob->Data != NULL) {\r
+ //\r
+ // Append ' initrd=<name>' in UTF-16.\r
+ //\r
+ KernelLoadedImage->LoadOptionsSize +=\r
+ (8 + StrLen(InitrdBlob->Name)) * 2;\r
+ }\r
+\r
+ if (KernelLoadedImage->LoadOptionsSize == 0) {\r
+ KernelLoadedImage->LoadOptions = NULL;\r
+ } else {\r
+ //\r
+ // NUL-terminate in UTF-16.\r
+ //\r
+ KernelLoadedImage->LoadOptionsSize += 2;\r
+\r
+ KernelLoadedImage->LoadOptions = AllocatePool (\r
+ KernelLoadedImage->LoadOptionsSize);\r
+ if (KernelLoadedImage->LoadOptions == NULL) {\r
+ KernelLoadedImage->LoadOptionsSize = 0;\r
+ Status = EFI_OUT_OF_RESOURCES;\r
+ goto UnloadKernelImage;\r
+ }\r
+\r
+ UnicodeSPrintAsciiFormat (\r
+ KernelLoadedImage->LoadOptions,\r
+ KernelLoadedImage->LoadOptionsSize,\r
+ "%a%a%s",\r
+ (CommandLineBlob->Data == NULL) ? "" : (CHAR8 *)CommandLineBlob->Data,\r
+ (InitrdBlob->Data == NULL) ? "" : " initrd=",\r
+ (InitrdBlob->Data == NULL) ? L"" : InitrdBlob->Name\r
+ );\r
+ DEBUG ((EFI_D_INFO, "%a: command line: \"%s\"\n", __FUNCTION__,\r
+ (CHAR16 *)KernelLoadedImage->LoadOptions));\r
+ }\r
+\r
+ //\r
+ // Start the image.\r
+ //\r
+ Status = gBS->StartImage (\r
+ KernelImageHandle,\r
+ NULL, // ExitDataSize\r
+ NULL // ExitData\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_ERROR, "%a: StartImage(): %r\n", __FUNCTION__, Status));\r
+ }\r
+\r
+ if (KernelLoadedImage->LoadOptions != NULL) {\r
+ FreePool (KernelLoadedImage->LoadOptions);\r
+ }\r
+ KernelLoadedImage->LoadOptionsSize = 0;\r
+\r
+UnloadKernelImage:\r
+ gBS->UnloadImage (KernelImageHandle);\r
+\r
+FreeKernelDevicePath:\r
+ FreePool (KernelDevicePath);\r
+\r
+UninstallProtocols:\r
+ gBS->UninstallMultipleProtocolInterfaces (FileSystemHandle,\r
+ &gEfiSimpleFileSystemProtocolGuid, &mFileSystem,\r
+ &gEfiDevicePathProtocolGuid, &mFileSystemDevicePath,\r
+ NULL);\r
+\r
+FreeBlobs:\r
+ while (BlobType > 0) {\r
+ CurrentBlob = &mKernelBlob[--BlobType];\r
+ if (CurrentBlob->Data != NULL) {\r
+ FreePool (CurrentBlob->Data);\r
+ CurrentBlob->Size = 0;\r
+ CurrentBlob->Data = NULL;\r
+ }\r
+ }\r
+\r
+ return Status;\r
+}\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
+* Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <libfdt.h>\r
+\r
+#include <Guid/EarlyPL011BaseAddress.h>\r
+#include <Guid/FdtHob.h>\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformPeim (\r
+ VOID\r
+ )\r
+{\r
+ VOID *Base;\r
+ VOID *NewBase;\r
+ UINTN FdtSize;\r
+ UINTN FdtPages;\r
+ UINT64 *FdtHobData;\r
+ UINT64 *UartHobData;\r
+ INT32 Node, Prev;\r
+ CONST CHAR8 *Compatible;\r
+ CONST CHAR8 *CompItem;\r
+ INT32 Len;\r
+ CONST UINT64 *RegProp;\r
+ UINT64 UartBase;\r
+\r
+\r
+ Base = (VOID*)(UINTN)PcdGet64 (PcdDeviceTreeInitialBaseAddress);\r
+ ASSERT (Base != NULL);\r
+ ASSERT (fdt_check_header (Base) == 0);\r
+\r
+ FdtSize = fdt_totalsize (Base) + PcdGet32 (PcdDeviceTreeAllocationPadding);\r
+ FdtPages = EFI_SIZE_TO_PAGES (FdtSize);\r
+ NewBase = AllocatePages (FdtPages);\r
+ ASSERT (NewBase != NULL);\r
+ fdt_open_into (Base, NewBase, EFI_PAGES_TO_SIZE (FdtPages));\r
+\r
+ FdtHobData = BuildGuidHob (&gFdtHobGuid, sizeof *FdtHobData);\r
+ ASSERT (FdtHobData != NULL);\r
+ *FdtHobData = (UINTN)NewBase;\r
+\r
+ UartHobData = BuildGuidHob (&gEarlyPL011BaseAddressGuid, sizeof *UartHobData);\r
+ ASSERT (UartHobData != NULL);\r
+ *UartHobData = 0;\r
+\r
+ //\r
+ // Look for a UART node\r
+ //\r
+ for (Prev = 0;; Prev = Node) {\r
+ Node = fdt_next_node (Base, Prev, NULL);\r
+ if (Node < 0) {\r
+ break;\r
+ }\r
+\r
+ //\r
+ // Check for UART node\r
+ //\r
+ Compatible = fdt_getprop (Base, Node, "compatible", &Len);\r
+\r
+ //\r
+ // Iterate over the NULL-separated items in the compatible string\r
+ //\r
+ for (CompItem = Compatible; CompItem != NULL && CompItem < Compatible + Len;\r
+ CompItem += 1 + AsciiStrLen (CompItem)) {\r
+\r
+ if (AsciiStrCmp (CompItem, "arm,pl011") == 0) {\r
+ RegProp = fdt_getprop (Base, Node, "reg", &Len);\r
+ ASSERT (Len == 16);\r
+\r
+ UartBase = fdt64_to_cpu (ReadUnaligned64 (RegProp));\r
+\r
+ DEBUG ((EFI_D_INFO, "%a: PL011 UART @ 0x%lx\n", __FUNCTION__, UartBase));\r
+\r
+ *UartHobData = UartBase;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ BuildFvHob (PcdGet64 (PcdFvBaseAddress), PcdGet32 (PcdFvSize));\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+#/** @file\r
+#\r
+# Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
+# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PlatformPeiLib\r
+ FILE_GUID = 59C11815-F8DA-4F49-B4FB-EC1E41ED1F06\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = PlatformPeiLib\r
+\r
+[Sources]\r
+ PlatformPeiLib.c\r
+\r
+[Packages]\r
+ ArmPkg/ArmPkg.dec\r
+ ArmVirtPkg/ArmVirtPkg.dec\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+\r
+[LibraryClasses]\r
+ DebugLib\r
+ HobLib\r
+ FdtLib\r
+\r
+[FixedPcd]\r
+ gArmTokenSpaceGuid.PcdFvSize\r
+ gArmVirtTokenSpaceGuid.PcdDeviceTreeAllocationPadding\r
+\r
+[Pcd]\r
+ gArmTokenSpaceGuid.PcdFvBaseAddress\r
+ gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress\r
+\r
+[Guids]\r
+ gEarlyPL011BaseAddressGuid\r
+ gFdtHobGuid\r
+\r
+[Depex]\r
+ gEfiPeiMemoryDiscoveredPpiGuid\r
--- /dev/null
+/** @file\r
+\r
+ Stateful and implicitly initialized fw_cfg library implementation.\r
+\r
+ Copyright (C) 2013 - 2014, Red Hat, Inc.\r
+ Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials are licensed and made available\r
+ under the terms and conditions of the BSD License which accompanies this\r
+ distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+**/\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/QemuFwCfgLib.h>\r
+\r
+STATIC UINTN mFwCfgSelectorAddress;\r
+STATIC UINTN mFwCfgDataAddress;\r
+\r
+\r
+/**\r
+ Returns a boolean indicating if the firmware configuration interface is\r
+ available for library-internal purposes.\r
+\r
+ This function never changes fw_cfg state.\r
+\r
+ @retval TRUE The interface is available internally.\r
+ @retval FALSE The interface is not available internally.\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+InternalQemuFwCfgIsAvailable (\r
+ VOID\r
+ )\r
+{\r
+ return (BOOLEAN)(mFwCfgSelectorAddress != 0 && mFwCfgDataAddress != 0);\r
+}\r
+\r
+\r
+/**\r
+ Returns a boolean indicating if the firmware configuration interface\r
+ is available or not.\r
+\r
+ This function may change fw_cfg state.\r
+\r
+ @retval TRUE The interface is available\r
+ @retval FALSE The interface is not available\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+QemuFwCfgIsAvailable (\r
+ VOID\r
+ )\r
+{\r
+ return InternalQemuFwCfgIsAvailable ();\r
+}\r
+\r
+\r
+RETURN_STATUS\r
+EFIAPI\r
+QemuFwCfgInitialize (\r
+ VOID\r
+ )\r
+{\r
+ mFwCfgSelectorAddress = (UINTN)PcdGet64 (PcdFwCfgSelectorAddress);\r
+ mFwCfgDataAddress = (UINTN)PcdGet64 (PcdFwCfgDataAddress);\r
+\r
+ if (InternalQemuFwCfgIsAvailable ()) {\r
+ UINT32 Signature;\r
+\r
+ QemuFwCfgSelectItem (QemuFwCfgItemSignature);\r
+ Signature = QemuFwCfgRead32 ();\r
+ if (Signature != SIGNATURE_32 ('Q', 'E', 'M', 'U')) {\r
+ mFwCfgSelectorAddress = 0;\r
+ mFwCfgDataAddress = 0;\r
+ }\r
+ }\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Selects a firmware configuration item for reading.\r
+\r
+ Following this call, any data read from this item will start from the\r
+ beginning of the configuration item's data.\r
+\r
+ @param[in] QemuFwCfgItem Firmware Configuration item to read\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+QemuFwCfgSelectItem (\r
+ IN FIRMWARE_CONFIG_ITEM QemuFwCfgItem\r
+ )\r
+{\r
+ if (InternalQemuFwCfgIsAvailable ()) {\r
+ MmioWrite16 (mFwCfgSelectorAddress, SwapBytes16 ((UINT16)QemuFwCfgItem));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ Reads firmware configuration bytes into a buffer\r
+\r
+ @param[in] Size Size in bytes to read\r
+ @param[in] Buffer Buffer to store data into (OPTIONAL if Size is 0)\r
+\r
+**/\r
+STATIC\r
+VOID\r
+EFIAPI\r
+InternalQemuFwCfgReadBytes (\r
+ IN UINTN Size,\r
+ IN VOID *Buffer OPTIONAL\r
+ )\r
+{\r
+ UINTN Left;\r
+ UINT8 *Ptr;\r
+ UINT8 *End;\r
+\r
+#ifdef MDE_CPU_AARCH64\r
+ Left = Size & 7;\r
+#else\r
+ Left = Size & 3;\r
+#endif\r
+\r
+ Size -= Left;\r
+ Ptr = Buffer;\r
+ End = Ptr + Size;\r
+\r
+#ifdef MDE_CPU_AARCH64\r
+ while (Ptr < End) {\r
+ *(UINT64 *)Ptr = MmioRead64 (mFwCfgDataAddress);\r
+ Ptr += 8;\r
+ }\r
+ if (Left & 4) {\r
+ *(UINT32 *)Ptr = MmioRead32 (mFwCfgDataAddress);\r
+ Ptr += 4;\r
+ }\r
+#else\r
+ while (Ptr < End) {\r
+ *(UINT32 *)Ptr = MmioRead32 (mFwCfgDataAddress);\r
+ Ptr += 4;\r
+ }\r
+#endif\r
+\r
+ if (Left & 2) {\r
+ *(UINT16 *)Ptr = MmioRead16 (mFwCfgDataAddress);\r
+ Ptr += 2;\r
+ }\r
+ if (Left & 1) {\r
+ *Ptr = MmioRead8 (mFwCfgDataAddress);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ Reads firmware configuration bytes into a buffer\r
+\r
+ If called multiple times, then the data read will continue at the offset of\r
+ the firmware configuration item where the previous read ended.\r
+\r
+ @param[in] Size Size in bytes to read\r
+ @param[in] Buffer Buffer to store data into\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+QemuFwCfgReadBytes (\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ if (InternalQemuFwCfgIsAvailable ()) {\r
+ InternalQemuFwCfgReadBytes (Size, Buffer);\r
+ } else {\r
+ ZeroMem (Buffer, Size);\r
+ }\r
+}\r
+\r
+/**\r
+ Write firmware configuration bytes from a buffer\r
+\r
+ If called multiple times, then the data written will continue at the offset\r
+ of the firmware configuration item where the previous write ended.\r
+\r
+ @param[in] Size Size in bytes to write\r
+ @param[in] Buffer Buffer to read data from\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+QemuFwCfgWriteBytes (\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ if (InternalQemuFwCfgIsAvailable ()) {\r
+ UINTN Idx;\r
+\r
+ for (Idx = 0; Idx < Size; ++Idx) {\r
+ MmioWrite8 (mFwCfgDataAddress, ((UINT8 *)Buffer)[Idx]);\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ Reads a UINT8 firmware configuration value\r
+\r
+ @return Value of Firmware Configuration item read\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+QemuFwCfgRead8 (\r
+ VOID\r
+ )\r
+{\r
+ UINT8 Result;\r
+\r
+ QemuFwCfgReadBytes (sizeof Result, &Result);\r
+ return Result;\r
+}\r
+\r
+\r
+/**\r
+ Reads a UINT16 firmware configuration value\r
+\r
+ @return Value of Firmware Configuration item read\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+QemuFwCfgRead16 (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Result;\r
+\r
+ QemuFwCfgReadBytes (sizeof Result, &Result);\r
+ return Result;\r
+}\r
+\r
+\r
+/**\r
+ Reads a UINT32 firmware configuration value\r
+\r
+ @return Value of Firmware Configuration item read\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+QemuFwCfgRead32 (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 Result;\r
+\r
+ QemuFwCfgReadBytes (sizeof Result, &Result);\r
+ return Result;\r
+}\r
+\r
+\r
+/**\r
+ Reads a UINT64 firmware configuration value\r
+\r
+ @return Value of Firmware Configuration item read\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+QemuFwCfgRead64 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Result;\r
+\r
+ QemuFwCfgReadBytes (sizeof Result, &Result);\r
+ return Result;\r
+}\r
+\r
+\r
+/**\r
+ Find the configuration item corresponding to the firmware configuration file.\r
+\r
+ @param[in] Name Name of file to look up.\r
+ @param[out] Item Configuration item corresponding to the file, to be passed\r
+ to QemuFwCfgSelectItem ().\r
+ @param[out] Size Number of bytes in the file.\r
+\r
+ @retval RETURN_SUCCESS If file is found.\r
+ @retval RETURN_NOT_FOUND If file is not found.\r
+ @retval RETURN_UNSUPPORTED If firmware configuration is unavailable.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+QemuFwCfgFindFile (\r
+ IN CONST CHAR8 *Name,\r
+ OUT FIRMWARE_CONFIG_ITEM *Item,\r
+ OUT UINTN *Size\r
+ )\r
+{\r
+ UINT32 Count;\r
+ UINT32 Idx;\r
+\r
+ if (!InternalQemuFwCfgIsAvailable ()) {\r
+ return RETURN_UNSUPPORTED;\r
+ }\r
+\r
+ QemuFwCfgSelectItem (QemuFwCfgItemFileDir);\r
+ Count = SwapBytes32 (QemuFwCfgRead32 ());\r
+\r
+ for (Idx = 0; Idx < Count; ++Idx) {\r
+ UINT32 FileSize;\r
+ UINT16 FileSelect;\r
+ CHAR8 FName[QEMU_FW_CFG_FNAME_SIZE];\r
+\r
+ FileSize = QemuFwCfgRead32 ();\r
+ FileSelect = QemuFwCfgRead16 ();\r
+ QemuFwCfgRead16 (); // skip the field called "reserved"\r
+ InternalQemuFwCfgReadBytes (sizeof (FName), FName);\r
+\r
+ if (AsciiStrCmp (Name, FName) == 0) {\r
+ *Item = (FIRMWARE_CONFIG_ITEM) SwapBytes16 (FileSelect);\r
+ *Size = SwapBytes32 (FileSize);\r
+ return RETURN_SUCCESS;\r
+ }\r
+ }\r
+\r
+ return RETURN_NOT_FOUND;\r
+}\r
+\r
+\r
+/**\r
+ Determine if S3 support is explicitly enabled.\r
+\r
+ @retval TRUE if S3 support is explicitly enabled.\r
+ FALSE otherwise. This includes unavailability of the firmware\r
+ configuration interface.\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+QemuFwCfgS3Enabled (\r
+ VOID\r
+ )\r
+{\r
+ return FALSE;\r
+}\r
--- /dev/null
+## @file\r
+#\r
+# Stateful, implicitly initialized fw_cfg library.\r
+#\r
+# Copyright (C) 2013 - 2014, Red Hat, Inc.\r
+# Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials are licensed and made available\r
+# under the terms and conditions of the BSD License which accompanies this\r
+# distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR\r
+# IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = QemuFwCfgLib\r
+ FILE_GUID = B271F41F-B841-48A9-BA8D-545B4BC2E2BF\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = QemuFwCfgLib|DXE_DRIVER\r
+\r
+ CONSTRUCTOR = QemuFwCfgInitialize\r
+\r
+#\r
+# The following information is for reference only and not required by the build\r
+# tools.\r
+#\r
+# VALID_ARCHITECTURES = ARM AARCH64\r
+#\r
+\r
+[Sources]\r
+ QemuFwCfgLib.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ OvmfPkg/OvmfPkg.dec\r
+ ArmVirtPkg/ArmVirtPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ BaseMemoryLib\r
+ IoLib\r
+ PcdLib\r
+\r
+[Pcd]\r
+ gArmVirtTokenSpaceGuid.PcdFwCfgSelectorAddress\r
+ gArmVirtTokenSpaceGuid.PcdFwCfgDataAddress\r
--- /dev/null
+/** @file\r
+ Implement EFI RealTimeClock runtime services via Xen shared info page\r
+\r
+ Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Uefi.h>\r
+#include <PiDxe.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+/**\r
+ Converts Epoch seconds (elapsed since 1970 JANUARY 01, 00:00:00 UTC) to EFI_TIME\r
+ **/\r
+STATIC\r
+VOID\r
+EpochToEfiTime (\r
+ IN UINTN EpochSeconds,\r
+ OUT EFI_TIME *Time\r
+ )\r
+{\r
+ UINTN a;\r
+ UINTN b;\r
+ UINTN c;\r
+ UINTN d;\r
+ UINTN g;\r
+ UINTN j;\r
+ UINTN m;\r
+ UINTN y;\r
+ UINTN da;\r
+ UINTN db;\r
+ UINTN dc;\r
+ UINTN dg;\r
+ UINTN hh;\r
+ UINTN mm;\r
+ UINTN ss;\r
+ UINTN J;\r
+\r
+ J = (EpochSeconds / 86400) + 2440588;\r
+ j = J + 32044;\r
+ g = j / 146097;\r
+ dg = j % 146097;\r
+ c = (((dg / 36524) + 1) * 3) / 4;\r
+ dc = dg - (c * 36524);\r
+ b = dc / 1461;\r
+ db = dc % 1461;\r
+ a = (((db / 365) + 1) * 3) / 4;\r
+ da = db - (a * 365);\r
+ y = (g * 400) + (c * 100) + (b * 4) + a;\r
+ m = (((da * 5) + 308) / 153) - 2;\r
+ d = da - (((m + 4) * 153) / 5) + 122;\r
+\r
+ Time->Year = y - 4800 + ((m + 2) / 12);\r
+ Time->Month = ((m + 2) % 12) + 1;\r
+ Time->Day = d + 1;\r
+\r
+ ss = EpochSeconds % 60;\r
+ a = (EpochSeconds - ss) / 60;\r
+ mm = a % 60;\r
+ b = (a - mm) / 60;\r
+ hh = b % 24;\r
+\r
+ Time->Hour = hh;\r
+ Time->Minute = mm;\r
+ Time->Second = ss;\r
+ Time->Nanosecond = 0;\r
+\r
+}\r
+\r
+/**\r
+ Returns the current time and date information, and the time-keeping capabilities\r
+ of the hardware platform.\r
+\r
+ @param Time A pointer to storage to receive a snapshot of the current time.\r
+ @param Capabilities An optional pointer to a buffer to receive the real time clock\r
+ device's capabilities.\r
+\r
+ @retval EFI_SUCCESS The operation completed successfully.\r
+ @retval EFI_INVALID_PARAMETER Time is NULL.\r
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibGetTime (\r
+ OUT EFI_TIME *Time,\r
+ OUT EFI_TIME_CAPABILITIES *Capabilities\r
+ )\r
+{\r
+ ASSERT (Time != NULL);\r
+\r
+ //\r
+ // For now, there is nothing that we can do besides returning a bogus time,\r
+ // as Xen's timekeeping uses a shared info page which cannot be shared\r
+ // between UEFI and the OS\r
+ //\r
+ EpochToEfiTime(1421770011, Time);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Sets the current local time and date information.\r
+\r
+ @param Time A pointer to the current time.\r
+\r
+ @retval EFI_SUCCESS The operation completed successfully.\r
+ @retval EFI_INVALID_PARAMETER A time field is out of range.\r
+ @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibSetTime (\r
+ IN EFI_TIME *Time\r
+ )\r
+{\r
+ return EFI_DEVICE_ERROR;\r
+}\r
+\r
+\r
+/**\r
+ Returns the current wakeup alarm clock setting.\r
+\r
+ @param Enabled Indicates if the alarm is currently enabled or disabled.\r
+ @param Pending Indicates if the alarm signal is pending and requires acknowledgement.\r
+ @param Time The current alarm setting.\r
+\r
+ @retval EFI_SUCCESS The alarm settings were returned.\r
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.\r
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.\r
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibGetWakeupTime (\r
+ OUT BOOLEAN *Enabled,\r
+ OUT BOOLEAN *Pending,\r
+ OUT EFI_TIME *Time\r
+ )\r
+{\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+/**\r
+ Sets the system wakeup alarm clock time.\r
+\r
+ @param Enabled Enable or disable the wakeup alarm.\r
+ @param Time If Enable is TRUE, the time to set the wakeup alarm for.\r
+\r
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If\r
+ Enable is FALSE, then the wakeup alarm was disabled.\r
+ @retval EFI_INVALID_PARAMETER A time field is out of range.\r
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.\r
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibSetWakeupTime (\r
+ IN BOOLEAN Enabled,\r
+ OUT EFI_TIME *Time\r
+ )\r
+{\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+/**\r
+ This is the declaration of an EFI image entry point. This can be the entry point to an application\r
+ written to this specification, an EFI boot service driver, or an EFI runtime driver.\r
+\r
+ @param ImageHandle Handle that identifies the loaded image.\r
+ @param SystemTable System Table for this image.\r
+\r
+ @retval EFI_SUCCESS The operation completed successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibRtcInitialize (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+#/** @file\r
+#\r
+# Copyright (c) 2015, L Ltd. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = XenRealTimeClockLib\r
+ FILE_GUID = EC2557E8-7005-430B-9F6F-9BA109698248\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = RealTimeClockLib|DXE_CORE DXE_DRIVER UEFI_DRIVER DXE_RUNTIME_DRIVER UEFI_APPLICATION\r
+\r
+[Sources.common]\r
+ XenRealTimeClockLib.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ OvmfPkg/OvmfPkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+\r
+[LibraryClasses]\r
+ UefiLib\r
+ DebugLib\r
+ DxeServicesTableLib\r
+ UefiRuntimeLib\r
+\r
+[Guids]\r
+ gEfiEventVirtualAddressChangeGuid\r
--- /dev/null
+/** @file\r
+ Provides the basic interfaces to abstract a PCI Host Bridge Resource Allocation\r
+\r
+Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials are\r
+licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "PciHostBridge.h"\r
+\r
+//\r
+// Hard code: Root Bridge Number within the host bridge\r
+// Root Bridge's attribute\r
+// Root Bridge's device path\r
+// Root Bridge's resource aperture\r
+//\r
+UINTN RootBridgeNumber[1] = { 1 };\r
+\r
+UINT64 RootBridgeAttribute[1][1] = { { EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM } };\r
+\r
+EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[1][1] = {\r
+ {\r
+ {\r
+ {\r
+ {\r
+ ACPI_DEVICE_PATH,\r
+ ACPI_DP,\r
+ {\r
+ (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),\r
+ (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)\r
+ }\r
+ },\r
+ EISA_PNP_ID(0x0A03),\r
+ 0\r
+ },\r
+\r
+ {\r
+ END_DEVICE_PATH_TYPE,\r
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
+ {\r
+ END_DEVICE_PATH_LENGTH,\r
+ 0\r
+ }\r
+ }\r
+ }\r
+ }\r
+};\r
+\r
+STATIC PCI_ROOT_BRIDGE_RESOURCE_APERTURE mResAperture[1][1];\r
+\r
+EFI_HANDLE mDriverImageHandle;\r
+\r
+PCI_HOST_BRIDGE_INSTANCE mPciHostBridgeInstanceTemplate = {\r
+ PCI_HOST_BRIDGE_SIGNATURE, // Signature\r
+ NULL, // HostBridgeHandle\r
+ 0, // RootBridgeNumber\r
+ {NULL, NULL}, // Head\r
+ FALSE, // ResourceSubiteed\r
+ TRUE, // CanRestarted\r
+ {\r
+ NotifyPhase,\r
+ GetNextRootBridge,\r
+ GetAttributes,\r
+ StartBusEnumeration,\r
+ SetBusNumbers,\r
+ SubmitResources,\r
+ GetProposedResources,\r
+ PreprocessController\r
+ }\r
+};\r
+\r
+//\r
+// Implementation\r
+//\r
+\r
+/**\r
+ Entry point of this driver\r
+\r
+ @param ImageHandle Handle of driver image\r
+ @param SystemTable Point to EFI_SYSTEM_TABLE\r
+\r
+ @retval EFI_ABORTED PCI host bridge not present\r
+ @retval EFI_OUT_OF_RESOURCES Can not allocate memory resource\r
+ @retval EFI_DEVICE_ERROR Can not install the protocol instance\r
+ @retval EFI_SUCCESS Success to initialize the Pci host bridge.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+InitializePciHostBridge (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ UINT64 MmioAttributes;\r
+ EFI_STATUS Status;\r
+ UINTN Loop1;\r
+ UINTN Loop2;\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridge;\r
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
+\r
+ if (PcdGet64 (PcdPciExpressBaseAddress) == 0) {\r
+ DEBUG ((EFI_D_INFO, "%a: PCI host bridge not present\n", __FUNCTION__));\r
+ return EFI_ABORTED;\r
+ }\r
+\r
+ mDriverImageHandle = ImageHandle;\r
+\r
+ mResAperture[0][0].BusBase = PcdGet32 (PcdPciBusMin);\r
+ mResAperture[0][0].BusLimit = PcdGet32 (PcdPciBusMax);\r
+\r
+ mResAperture[0][0].MemBase = PcdGet32 (PcdPciMmio32Base);\r
+ mResAperture[0][0].MemLimit = (UINT64)PcdGet32 (PcdPciMmio32Base) +\r
+ PcdGet32 (PcdPciMmio32Size) - 1;\r
+\r
+ mResAperture[0][0].IoBase = PcdGet64 (PcdPciIoBase);\r
+ mResAperture[0][0].IoLimit = PcdGet64 (PcdPciIoBase) +\r
+ PcdGet64 (PcdPciIoSize) - 1;\r
+ mResAperture[0][0].IoTranslation = PcdGet64 (PcdPciIoTranslation);\r
+\r
+ //\r
+ // Add IO and MMIO memory space, so that resources can be allocated in the\r
+ // EfiPciHostBridgeAllocateResources phase.\r
+ //\r
+ Status = gDS->AddIoSpace (\r
+ EfiGcdIoTypeIo,\r
+ PcdGet64 (PcdPciIoBase),\r
+ PcdGet64 (PcdPciIoSize)\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ MmioAttributes = FeaturePcdGet (PcdKludgeMapPciMmioAsCached) ?\r
+ EFI_MEMORY_WB : EFI_MEMORY_UC;\r
+\r
+ Status = gDS->AddMemorySpace (\r
+ EfiGcdMemoryTypeMemoryMappedIo,\r
+ PcdGet32 (PcdPciMmio32Base),\r
+ PcdGet32 (PcdPciMmio32Size),\r
+ MmioAttributes\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_ERROR, "%a: AddMemorySpace: %r\n", __FUNCTION__, Status));\r
+ return Status;\r
+ }\r
+\r
+ Status = gDS->SetMemorySpaceAttributes (\r
+ PcdGet32 (PcdPciMmio32Base),\r
+ PcdGet32 (PcdPciMmio32Size),\r
+ MmioAttributes\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_ERROR, "%a: SetMemorySpaceAttributes: %r\n", __FUNCTION__,\r
+ Status));\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // Create Host Bridge Device Handle\r
+ //\r
+ for (Loop1 = 0; Loop1 < HOST_BRIDGE_NUMBER; Loop1++) {\r
+ HostBridge = AllocateCopyPool (sizeof(PCI_HOST_BRIDGE_INSTANCE), &mPciHostBridgeInstanceTemplate);\r
+ if (HostBridge == NULL) {\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+\r
+ HostBridge->RootBridgeNumber = RootBridgeNumber[Loop1];\r
+ InitializeListHead (&HostBridge->Head);\r
+\r
+ Status = gBS->InstallMultipleProtocolInterfaces (\r
+ &HostBridge->HostBridgeHandle,\r
+ &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc,\r
+ NULL\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ FreePool (HostBridge);\r
+ return EFI_DEVICE_ERROR;\r
+ }\r
+\r
+ //\r
+ // Create Root Bridge Device Handle in this Host Bridge\r
+ //\r
+\r
+ for (Loop2 = 0; Loop2 < HostBridge->RootBridgeNumber; Loop2++) {\r
+ PrivateData = AllocateZeroPool (sizeof(PCI_ROOT_BRIDGE_INSTANCE));\r
+ if (PrivateData == NULL) {\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+\r
+ PrivateData->Signature = PCI_ROOT_BRIDGE_SIGNATURE;\r
+ PrivateData->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[Loop1][Loop2];\r
+\r
+ RootBridgeConstructor (\r
+ &PrivateData->Io,\r
+ HostBridge->HostBridgeHandle,\r
+ RootBridgeAttribute[Loop1][Loop2],\r
+ &mResAperture[Loop1][Loop2]\r
+ );\r
+\r
+ Status = gBS->InstallMultipleProtocolInterfaces(\r
+ &PrivateData->Handle,\r
+ &gEfiDevicePathProtocolGuid, PrivateData->DevicePath,\r
+ &gEfiPciRootBridgeIoProtocolGuid, &PrivateData->Io,\r
+ NULL\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ FreePool(PrivateData);\r
+ return EFI_DEVICE_ERROR;\r
+ }\r
+\r
+ InsertTailList (&HostBridge->Head, &PrivateData->Link);\r
+ }\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ These are the notifications from the PCI bus driver that it is about to enter a certain\r
+ phase of the PCI enumeration process.\r
+\r
+ This member function can be used to notify the host bridge driver to perform specific actions,\r
+ including any chipset-specific initialization, so that the chipset is ready to enter the next phase.\r
+ Eight notification points are defined at this time. See belows:\r
+ EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data\r
+ structures. The PCI enumerator should issue this notification\r
+ before starting a fresh enumeration process. Enumeration cannot\r
+ be restarted after sending any other notification such as\r
+ EfiPciHostBridgeBeginBusAllocation.\r
+ EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is\r
+ required here. This notification can be used to perform any\r
+ chipset-specific programming.\r
+ EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No\r
+ specific action is required here. This notification can be used to\r
+ perform any chipset-specific programming.\r
+ EfiPciHostBridgeBeginResourceAllocation\r
+ The resource allocation phase is about to begin. No specific\r
+ action is required here. This notification can be used to perform\r
+ any chipset-specific programming.\r
+ EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI\r
+ root bridges. These resource settings are returned on the next call to\r
+ GetProposedResources(). Before calling NotifyPhase() with a Phase of\r
+ EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible\r
+ for gathering I/O and memory requests for\r
+ all the PCI root bridges and submitting these requests using\r
+ SubmitResources(). This function pads the resource amount\r
+ to suit the root bridge hardware, takes care of dependencies between\r
+ the PCI root bridges, and calls the Global Coherency Domain (GCD)\r
+ with the allocation request. In the case of padding, the allocated range\r
+ could be bigger than what was requested.\r
+ EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated\r
+ resources (proposed resources) for all the PCI root bridges. After the\r
+ hardware is programmed, reassigning resources will not be supported.\r
+ The bus settings are not affected.\r
+ EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI\r
+ root bridges and resets the I/O and memory apertures to their initial\r
+ state. The bus settings are not affected. If the request to allocate\r
+ resources fails, the PCI enumerator can use this notification to\r
+ deallocate previous resources, adjust the requests, and retry\r
+ allocation.\r
+ EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is\r
+ required here. This notification can be used to perform any chipsetspecific\r
+ programming.\r
+\r
+ @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ @param[in] Phase The phase during enumeration\r
+\r
+ @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error\r
+ is valid for a Phase of EfiPciHostBridgeAllocateResources if\r
+ SubmitResources() has not been called for one or more\r
+ PCI root bridges before this call\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid\r
+ for a Phase of EfiPciHostBridgeSetResources.\r
+ @retval EFI_INVALID_PARAMETER Invalid phase parameter\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the\r
+ previously submitted resource requests cannot be fulfilled or\r
+ were only partially fulfilled.\r
+ @retval EFI_SUCCESS The notification was accepted without any errors.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+NotifyPhase(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r
+ )\r
+{\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
+ PCI_RESOURCE_TYPE Index;\r
+ LIST_ENTRY *List;\r
+ EFI_PHYSICAL_ADDRESS BaseAddress;\r
+ UINT64 AddrLen;\r
+ UINTN BitsOfAlignment;\r
+ EFI_STATUS Status;\r
+ EFI_STATUS ReturnStatus;\r
+\r
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
+\r
+ switch (Phase) {\r
+\r
+ case EfiPciHostBridgeBeginEnumeration:\r
+ if (HostBridgeInstance->CanRestarted) {\r
+ //\r
+ // Reset the Each Root Bridge\r
+ //\r
+ List = HostBridgeInstance->Head.ForwardLink;\r
+\r
+ while (List != &HostBridgeInstance->Head) {\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+ for (Index = TypeIo; Index < TypeMax; Index++) {\r
+ RootBridgeInstance->ResAllocNode[Index].Type = Index;\r
+ RootBridgeInstance->ResAllocNode[Index].Base = 0;\r
+ RootBridgeInstance->ResAllocNode[Index].Length = 0;\r
+ RootBridgeInstance->ResAllocNode[Index].Status = ResNone;\r
+ }\r
+\r
+ List = List->ForwardLink;\r
+ }\r
+\r
+ HostBridgeInstance->ResourceSubmited = FALSE;\r
+ HostBridgeInstance->CanRestarted = TRUE;\r
+ } else {\r
+ //\r
+ // Can not restart\r
+ //\r
+ return EFI_NOT_READY;\r
+ }\r
+ break;\r
+\r
+ case EfiPciHostBridgeEndEnumeration:\r
+ break;\r
+\r
+ case EfiPciHostBridgeBeginBusAllocation:\r
+ //\r
+ // No specific action is required here, can perform any chipset specific programing\r
+ //\r
+ HostBridgeInstance->CanRestarted = FALSE;\r
+ break;\r
+\r
+ case EfiPciHostBridgeEndBusAllocation:\r
+ //\r
+ // No specific action is required here, can perform any chipset specific programing\r
+ //\r
+ //HostBridgeInstance->CanRestarted = FALSE;\r
+ break;\r
+\r
+ case EfiPciHostBridgeBeginResourceAllocation:\r
+ //\r
+ // No specific action is required here, can perform any chipset specific programing\r
+ //\r
+ //HostBridgeInstance->CanRestarted = FALSE;\r
+ break;\r
+\r
+ case EfiPciHostBridgeAllocateResources:\r
+ ReturnStatus = EFI_SUCCESS;\r
+ if (HostBridgeInstance->ResourceSubmited) {\r
+ //\r
+ // Take care of the resource dependencies between the root bridges\r
+ //\r
+ List = HostBridgeInstance->Head.ForwardLink;\r
+\r
+ while (List != &HostBridgeInstance->Head) {\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+ for (Index = TypeIo; Index < TypeBus; Index++) {\r
+ if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {\r
+\r
+ AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
+\r
+ //\r
+ // Get the number of '1' in Alignment.\r
+ //\r
+ BitsOfAlignment = (UINTN) (HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1);\r
+\r
+ switch (Index) {\r
+\r
+ case TypeIo:\r
+ //\r
+ // It is impossible for this chipset to align 0xFFFF for IO16\r
+ // So clear it\r
+ //\r
+ if (BitsOfAlignment >= 16) {\r
+ BitsOfAlignment = 0;\r
+ }\r
+\r
+ BaseAddress = mResAperture[0][0].IoLimit;\r
+ Status = gDS->AllocateIoSpace (\r
+ EfiGcdAllocateMaxAddressSearchTopDown,\r
+ EfiGcdIoTypeIo,\r
+ BitsOfAlignment,\r
+ AddrLen,\r
+ &BaseAddress,\r
+ mDriverImageHandle,\r
+ NULL\r
+ );\r
+\r
+ if (!EFI_ERROR (Status)) {\r
+ RootBridgeInstance->ResAllocNode[Index].Base = (UINTN)BaseAddress;\r
+ RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;\r
+ } else {\r
+ ReturnStatus = Status;\r
+ if (Status != EFI_OUT_OF_RESOURCES) {\r
+ RootBridgeInstance->ResAllocNode[Index].Length = 0;\r
+ }\r
+ }\r
+\r
+ break;\r
+\r
+\r
+ case TypeMem32:\r
+ //\r
+ // It is impossible for this chipset to align 0xFFFFFFFF for Mem32\r
+ // So clear it\r
+ //\r
+\r
+ if (BitsOfAlignment >= 32) {\r
+ BitsOfAlignment = 0;\r
+ }\r
+\r
+ BaseAddress = mResAperture[0][0].MemLimit;\r
+ Status = gDS->AllocateMemorySpace (\r
+ EfiGcdAllocateMaxAddressSearchTopDown,\r
+ EfiGcdMemoryTypeMemoryMappedIo,\r
+ BitsOfAlignment,\r
+ AddrLen,\r
+ &BaseAddress,\r
+ mDriverImageHandle,\r
+ NULL\r
+ );\r
+\r
+ if (!EFI_ERROR (Status)) {\r
+ // We were able to allocate the PCI memory\r
+ RootBridgeInstance->ResAllocNode[Index].Base = (UINTN)BaseAddress;\r
+ RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;\r
+\r
+ } else {\r
+ // Not able to allocate enough PCI memory\r
+ ReturnStatus = Status;\r
+\r
+ if (Status != EFI_OUT_OF_RESOURCES) {\r
+ RootBridgeInstance->ResAllocNode[Index].Length = 0;\r
+ }\r
+ ASSERT (FALSE);\r
+ }\r
+ break;\r
+\r
+ case TypePMem32:\r
+ case TypeMem64:\r
+ case TypePMem64:\r
+ ReturnStatus = EFI_ABORTED;\r
+ break;\r
+ default:\r
+ ASSERT (FALSE);\r
+ break;\r
+ }; //end switch\r
+ }\r
+ }\r
+\r
+ List = List->ForwardLink;\r
+ }\r
+\r
+ return ReturnStatus;\r
+ } else {\r
+ return EFI_NOT_READY;\r
+ }\r
+\r
+ case EfiPciHostBridgeSetResources:\r
+ break;\r
+\r
+ case EfiPciHostBridgeFreeResources:\r
+ ReturnStatus = EFI_SUCCESS;\r
+ List = HostBridgeInstance->Head.ForwardLink;\r
+ while (List != &HostBridgeInstance->Head) {\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+ for (Index = TypeIo; Index < TypeBus; Index++) {\r
+ if (RootBridgeInstance->ResAllocNode[Index].Status == ResAllocated) {\r
+ AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
+ BaseAddress = RootBridgeInstance->ResAllocNode[Index].Base;\r
+ switch (Index) {\r
+\r
+ case TypeIo:\r
+ Status = gDS->FreeIoSpace (BaseAddress, AddrLen);\r
+ if (EFI_ERROR (Status)) {\r
+ ReturnStatus = Status;\r
+ }\r
+ break;\r
+\r
+ case TypeMem32:\r
+ Status = gDS->FreeMemorySpace (BaseAddress, AddrLen);\r
+ if (EFI_ERROR (Status)) {\r
+ ReturnStatus = Status;\r
+ }\r
+ break;\r
+\r
+ case TypePMem32:\r
+ break;\r
+\r
+ case TypeMem64:\r
+ break;\r
+\r
+ case TypePMem64:\r
+ break;\r
+\r
+ default:\r
+ ASSERT (FALSE);\r
+ break;\r
+\r
+ }; //end switch\r
+ RootBridgeInstance->ResAllocNode[Index].Type = Index;\r
+ RootBridgeInstance->ResAllocNode[Index].Base = 0;\r
+ RootBridgeInstance->ResAllocNode[Index].Length = 0;\r
+ RootBridgeInstance->ResAllocNode[Index].Status = ResNone;\r
+ }\r
+ }\r
+\r
+ List = List->ForwardLink;\r
+ }\r
+\r
+ HostBridgeInstance->ResourceSubmited = FALSE;\r
+ HostBridgeInstance->CanRestarted = TRUE;\r
+ return ReturnStatus;\r
+\r
+ case EfiPciHostBridgeEndResourceAllocation:\r
+ HostBridgeInstance->CanRestarted = FALSE;\r
+ break;\r
+\r
+ default:\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Return the device handle of the next PCI root bridge that is associated with this Host Bridge.\r
+\r
+ This function is called multiple times to retrieve the device handles of all the PCI root bridges that\r
+ are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI\r
+ root bridges. On each call, the handle that was returned by the previous call is passed into the\r
+ interface, and on output the interface returns the device handle of the next PCI root bridge. The\r
+ caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
+ for that root bridge. When there are no more PCI root bridges to report, the interface returns\r
+ EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they\r
+ are returned by this function.\r
+ For D945 implementation, there is only one root bridge in PCI host bridge.\r
+\r
+ @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge.\r
+\r
+ @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the\r
+ specific Host bridge and return EFI_SUCCESS.\r
+ @retval EFI_NOT_FOUND Can not find the any more root bridge in specific host bridge.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was\r
+ returned on a previous call to GetNextRootBridge().\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GetNextRootBridge(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN OUT EFI_HANDLE *RootBridgeHandle\r
+ )\r
+{\r
+ BOOLEAN NoRootBridge;\r
+ LIST_ENTRY *List;\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
+\r
+ NoRootBridge = TRUE;\r
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
+ List = HostBridgeInstance->Head.ForwardLink;\r
+\r
+\r
+ while (List != &HostBridgeInstance->Head) {\r
+ NoRootBridge = FALSE;\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+ if (*RootBridgeHandle == NULL) {\r
+ //\r
+ // Return the first Root Bridge Handle of the Host Bridge\r
+ //\r
+ *RootBridgeHandle = RootBridgeInstance->Handle;\r
+ return EFI_SUCCESS;\r
+ } else {\r
+ if (*RootBridgeHandle == RootBridgeInstance->Handle) {\r
+ //\r
+ // Get next if have\r
+ //\r
+ List = List->ForwardLink;\r
+ if (List!=&HostBridgeInstance->Head) {\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+ *RootBridgeHandle = RootBridgeInstance->Handle;\r
+ return EFI_SUCCESS;\r
+ } else {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+ }\r
+ }\r
+\r
+ List = List->ForwardLink;\r
+ } //end while\r
+\r
+ if (NoRootBridge) {\r
+ return EFI_NOT_FOUND;\r
+ } else {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+}\r
+\r
+/**\r
+ Returns the allocation attributes of a PCI root bridge.\r
+\r
+ The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary\r
+ from one PCI root bridge to another. These attributes are different from the decode-related\r
+ attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The\r
+ RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device\r
+ handles of all the root bridges that are associated with this host bridge must be obtained by calling\r
+ GetNextRootBridge(). The attributes are static in the sense that they do not change during or\r
+ after the enumeration process. The hardware may provide mechanisms to change the attributes on\r
+ the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is\r
+ installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in\r
+ "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.\r
+ For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to\r
+ include requests for the prefetchable memory in the nonprefetchable memory pool and not request any\r
+ prefetchable memory.\r
+ Attribute Description\r
+ ------------------------------------ ----------------------------------------------------------------------\r
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root bridge does not support separate\r
+ windows for nonprefetchable and prefetchable memory. A PCI bus\r
+ driver needs to include requests for prefetchable memory in the\r
+ nonprefetchable memory pool.\r
+\r
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root bridge supports 64-bit memory\r
+ windows. If this bit is not set, the PCI bus driver needs to include\r
+ requests for a 64-bit memory address in the corresponding 32-bit\r
+ memory pool.\r
+\r
+ @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested. Type\r
+ EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.\r
+ @param[out] Attributes The pointer to attribte of root bridge, it is output parameter\r
+\r
+ @retval EFI_INVALID_PARAMETER Attribute pointer is NULL\r
+ @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.\r
+ @retval EFI_SUCCESS Success to get attribute of interested root bridge.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GetAttributes(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ OUT UINT64 *Attributes\r
+ )\r
+{\r
+ LIST_ENTRY *List;\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
+\r
+ if (Attributes == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
+ List = HostBridgeInstance->Head.ForwardLink;\r
+\r
+ while (List != &HostBridgeInstance->Head) {\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+ if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
+ *Attributes = RootBridgeInstance->RootBridgeAttrib;\r
+ return EFI_SUCCESS;\r
+ }\r
+ List = List->ForwardLink;\r
+ }\r
+\r
+ //\r
+ // RootBridgeHandle is not an EFI_HANDLE\r
+ // that was returned on a previous call to GetNextRootBridge()\r
+ //\r
+ return EFI_INVALID_PARAMETER;\r
+}\r
+\r
+/**\r
+ Sets up the specified PCI root bridge for the bus enumeration process.\r
+\r
+ This member function sets up the root bridge for bus enumeration and returns the PCI bus range\r
+ over which the search should be performed in ACPI 2.0 resource descriptor format.\r
+\r
+ @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.\r
+ @param[in] RootBridgeHandle The PCI Root Bridge to be set up.\r
+ @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor.\r
+\r
+ @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle\r
+ @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.\r
+ @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+StartBusEnumeration(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ OUT VOID **Configuration\r
+ )\r
+{\r
+ LIST_ENTRY *List;\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
+ VOID *Buffer;\r
+ UINT8 *Temp;\r
+ UINT64 BusStart;\r
+ UINT64 BusEnd;\r
+\r
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
+ List = HostBridgeInstance->Head.ForwardLink;\r
+\r
+ while (List != &HostBridgeInstance->Head) {\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+ if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
+ //\r
+ // Set up the Root Bridge for Bus Enumeration\r
+ //\r
+ BusStart = RootBridgeInstance->BusBase;\r
+ BusEnd = RootBridgeInstance->BusLimit;\r
+ //\r
+ // Program the Hardware(if needed) if error return EFI_DEVICE_ERROR\r
+ //\r
+\r
+ Buffer = AllocatePool (sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));\r
+ if (Buffer == NULL) {\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+\r
+ Temp = (UINT8 *)Buffer;\r
+\r
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Desc = 0x8A;\r
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Len = 0x2B;\r
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->ResType = 2;\r
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->GenFlag = 0;\r
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->SpecificFlag = 0;\r
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrSpaceGranularity = 0;\r
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMin = BusStart;\r
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMax = 0;\r
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrTranslationOffset = 0;\r
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrLen = BusEnd - BusStart + 1;\r
+\r
+ Temp = Temp + sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
+ ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;\r
+ ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;\r
+\r
+ *Configuration = Buffer;\r
+ return EFI_SUCCESS;\r
+ }\r
+ List = List->ForwardLink;\r
+ }\r
+\r
+ return EFI_INVALID_PARAMETER;\r
+}\r
+\r
+/**\r
+ Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.\r
+\r
+ This member function programs the specified PCI root bridge to decode the bus range that is\r
+ specified by the input parameter Configuration.\r
+ The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.\r
+\r
+ @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance\r
+ @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be programmed\r
+ @param[in] Configuration The pointer to the PCI bus resource descriptor\r
+\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.\r
+ @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.\r
+ @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource descriptor.\r
+ @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than\r
+ bus descriptors.\r
+ @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource descriptors.\r
+ @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.\r
+ @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
+ @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SetBusNumbers(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN VOID *Configuration\r
+ )\r
+{\r
+ LIST_ENTRY *List;\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
+ UINT8 *Ptr;\r
+ UINTN BusStart;\r
+ UINTN BusEnd;\r
+ UINTN BusLen;\r
+\r
+ if (Configuration == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ Ptr = Configuration;\r
+\r
+ //\r
+ // Check the Configuration is valid\r
+ //\r
+ if(*Ptr != ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->ResType != 2) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ Ptr += sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
+ if (*Ptr != ACPI_END_TAG_DESCRIPTOR) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
+ List = HostBridgeInstance->Head.ForwardLink;\r
+\r
+ Ptr = Configuration;\r
+\r
+ while (List != &HostBridgeInstance->Head) {\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+ if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
+ BusStart = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrRangeMin;\r
+ BusLen = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrLen;\r
+ BusEnd = BusStart + BusLen - 1;\r
+\r
+ if (BusStart > BusEnd) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if ((BusStart < RootBridgeInstance->BusBase) || (BusEnd > RootBridgeInstance->BusLimit)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Update the Bus Range\r
+ //\r
+ RootBridgeInstance->ResAllocNode[TypeBus].Base = BusStart;\r
+ RootBridgeInstance->ResAllocNode[TypeBus].Length = BusLen;\r
+ RootBridgeInstance->ResAllocNode[TypeBus].Status = ResAllocated;\r
+\r
+ //\r
+ // Program the Root Bridge Hardware\r
+ //\r
+\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ List = List->ForwardLink;\r
+ }\r
+\r
+ return EFI_INVALID_PARAMETER;\r
+}\r
+\r
+\r
+/**\r
+ Submits the I/O and memory resource requirements for the specified PCI root bridge.\r
+\r
+ This function is used to submit all the I/O and memory resources that are required by the specified\r
+ PCI root bridge. The input parameter Configuration is used to specify the following:\r
+ - The various types of resources that are required\r
+ - The associated lengths in terms of ACPI 2.0 resource descriptor format\r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
+ @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being submitted.\r
+ @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor.\r
+\r
+ @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were accepted.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.\r
+ @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.\r
+ @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are\r
+ not supported by this PCI root bridge. This error will happen if the caller\r
+ did not combine resources according to Attributes that were returned by\r
+ GetAllocAttributes().\r
+ @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.\r
+ @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SubmitResources(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN VOID *Configuration\r
+ )\r
+{\r
+ LIST_ENTRY *List;\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
+ UINT8 *Temp;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
+ UINT64 AddrLen;\r
+ UINT64 Alignment;\r
+\r
+ //\r
+ // Check the input parameter: Configuration\r
+ //\r
+ if (Configuration == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
+ List = HostBridgeInstance->Head.ForwardLink;\r
+\r
+ Temp = (UINT8 *)Configuration;\r
+ while ( *Temp == 0x8A) {\r
+ Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ;\r
+ }\r
+ if (*Temp != 0x79) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ Temp = (UINT8 *)Configuration;\r
+ while (List != &HostBridgeInstance->Head) {\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+ if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
+ for (;\r
+ *Temp == 0x8A;\r
+ Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR)\r
+ ) {\r
+ Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;\r
+\r
+ //\r
+ // Check Address Length\r
+ //\r
+ if (Ptr->AddrLen == 0) {\r
+ HostBridgeInstance->ResourceSubmited = TRUE;\r
+ continue;\r
+ }\r
+ if (Ptr->AddrLen > 0xffffffff) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Check address range alignment\r
+ //\r
+ if (Ptr->AddrRangeMax >= 0xffffffff || Ptr->AddrRangeMax != (GetPowerOfTwo64 (Ptr->AddrRangeMax + 1) - 1)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ switch (Ptr->ResType) {\r
+\r
+ case 0:\r
+\r
+ //\r
+ // Check invalid Address Sapce Granularity\r
+ //\r
+ if (Ptr->AddrSpaceGranularity != 32) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // check the memory resource request is supported by PCI root bridge\r
+ //\r
+ if (RootBridgeInstance->RootBridgeAttrib == EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM &&\r
+ Ptr->SpecificFlag == 0x06) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ AddrLen = Ptr->AddrLen;\r
+ Alignment = Ptr->AddrRangeMax;\r
+ if (Ptr->AddrSpaceGranularity == 32) {\r
+ if (Ptr->SpecificFlag == 0x06) {\r
+ //\r
+ // Apply from GCD\r
+ //\r
+ RootBridgeInstance->ResAllocNode[TypePMem32].Status = ResSubmitted;\r
+ } else {\r
+ RootBridgeInstance->ResAllocNode[TypeMem32].Length = AddrLen;\r
+ RootBridgeInstance->ResAllocNode[TypeMem32].Alignment = Alignment;\r
+ RootBridgeInstance->ResAllocNode[TypeMem32].Status = ResRequested;\r
+ HostBridgeInstance->ResourceSubmited = TRUE;\r
+ }\r
+ }\r
+\r
+ if (Ptr->AddrSpaceGranularity == 64) {\r
+ if (Ptr->SpecificFlag == 0x06) {\r
+ RootBridgeInstance->ResAllocNode[TypePMem64].Status = ResSubmitted;\r
+ } else {\r
+ RootBridgeInstance->ResAllocNode[TypeMem64].Status = ResSubmitted;\r
+ }\r
+ }\r
+ break;\r
+\r
+ case 1:\r
+ AddrLen = (UINTN) Ptr->AddrLen;\r
+ Alignment = (UINTN) Ptr->AddrRangeMax;\r
+ RootBridgeInstance->ResAllocNode[TypeIo].Length = AddrLen;\r
+ RootBridgeInstance->ResAllocNode[TypeIo].Alignment = Alignment;\r
+ RootBridgeInstance->ResAllocNode[TypeIo].Status = ResRequested;\r
+ HostBridgeInstance->ResourceSubmited = TRUE;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ };\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ List = List->ForwardLink;\r
+ }\r
+\r
+ return EFI_INVALID_PARAMETER;\r
+}\r
+\r
+/**\r
+ Returns the proposed resource settings for the specified PCI root bridge.\r
+\r
+ This member function returns the proposed resource settings for the specified PCI root bridge. The\r
+ proposed resource settings are prepared when NotifyPhase() is called with a Phase of\r
+ EfiPciHostBridgeAllocateResources. The output parameter Configuration\r
+ specifies the following:\r
+ - The various types of resources, excluding bus resources, that are allocated\r
+ - The associated lengths in terms of ACPI 2.0 resource descriptor format\r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
+ @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.\r
+ @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.\r
+\r
+ @retval EFI_SUCCESS The requested parameters were returned.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GetProposedResources(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ OUT VOID **Configuration\r
+ )\r
+{\r
+ LIST_ENTRY *List;\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
+ UINTN Index;\r
+ UINTN Number;\r
+ VOID *Buffer;\r
+ UINT8 *Temp;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
+ UINT64 ResStatus;\r
+\r
+ Buffer = NULL;\r
+ Number = 0;\r
+ //\r
+ // Get the Host Bridge Instance from the resource allocation protocol\r
+ //\r
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
+ List = HostBridgeInstance->Head.ForwardLink;\r
+\r
+ //\r
+ // Enumerate the root bridges in this host bridge\r
+ //\r
+ while (List != &HostBridgeInstance->Head) {\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+ if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
+ for (Index = 0; Index < TypeBus; Index ++) {\r
+ if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {\r
+ Number ++;\r
+ }\r
+ }\r
+\r
+ if (Number == 0) {\r
+ EFI_ACPI_END_TAG_DESCRIPTOR *End;\r
+\r
+ End = AllocateZeroPool (sizeof *End);\r
+ if (End == NULL) {\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+ End->Desc = ACPI_END_TAG_DESCRIPTOR;\r
+ *Configuration = End;\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ Buffer = AllocateZeroPool (Number * sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));\r
+ if (Buffer == NULL) {\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+\r
+ Temp = Buffer;\r
+ for (Index = 0; Index < TypeBus; Index ++) {\r
+ if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {\r
+ Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;\r
+ ResStatus = RootBridgeInstance->ResAllocNode[Index].Status;\r
+\r
+ switch (Index) {\r
+\r
+ case TypeIo:\r
+ //\r
+ // Io\r
+ //\r
+ Ptr->Desc = 0x8A;\r
+ Ptr->Len = 0x2B;\r
+ Ptr->ResType = 1;\r
+ Ptr->GenFlag = 0;\r
+ Ptr->SpecificFlag = 0;\r
+ Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
+ Ptr->AddrRangeMax = 0;\r
+ Ptr->AddrTranslationOffset = \\r
+ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;\r
+ Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
+ break;\r
+\r
+ case TypeMem32:\r
+ //\r
+ // Memory 32\r
+ //\r
+ Ptr->Desc = 0x8A;\r
+ Ptr->Len = 0x2B;\r
+ Ptr->ResType = 0;\r
+ Ptr->GenFlag = 0;\r
+ Ptr->SpecificFlag = 0;\r
+ Ptr->AddrSpaceGranularity = 32;\r
+ Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
+ Ptr->AddrRangeMax = 0;\r
+ Ptr->AddrTranslationOffset = \\r
+ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;\r
+ Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
+ break;\r
+\r
+ case TypePMem32:\r
+ //\r
+ // Prefetch memory 32\r
+ //\r
+ Ptr->Desc = 0x8A;\r
+ Ptr->Len = 0x2B;\r
+ Ptr->ResType = 0;\r
+ Ptr->GenFlag = 0;\r
+ Ptr->SpecificFlag = 6;\r
+ Ptr->AddrSpaceGranularity = 32;\r
+ Ptr->AddrRangeMin = 0;\r
+ Ptr->AddrRangeMax = 0;\r
+ Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;\r
+ Ptr->AddrLen = 0;\r
+ break;\r
+\r
+ case TypeMem64:\r
+ //\r
+ // Memory 64\r
+ //\r
+ Ptr->Desc = 0x8A;\r
+ Ptr->Len = 0x2B;\r
+ Ptr->ResType = 0;\r
+ Ptr->GenFlag = 0;\r
+ Ptr->SpecificFlag = 0;\r
+ Ptr->AddrSpaceGranularity = 64;\r
+ Ptr->AddrRangeMin = 0;\r
+ Ptr->AddrRangeMax = 0;\r
+ Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;\r
+ Ptr->AddrLen = 0;\r
+ break;\r
+\r
+ case TypePMem64:\r
+ //\r
+ // Prefetch memory 64\r
+ //\r
+ Ptr->Desc = 0x8A;\r
+ Ptr->Len = 0x2B;\r
+ Ptr->ResType = 0;\r
+ Ptr->GenFlag = 0;\r
+ Ptr->SpecificFlag = 6;\r
+ Ptr->AddrSpaceGranularity = 64;\r
+ Ptr->AddrRangeMin = 0;\r
+ Ptr->AddrRangeMax = 0;\r
+ Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;\r
+ Ptr->AddrLen = 0;\r
+ break;\r
+ };\r
+\r
+ Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
+ }\r
+ }\r
+\r
+ ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;\r
+ ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;\r
+\r
+ *Configuration = Buffer;\r
+\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ List = List->ForwardLink;\r
+ }\r
+\r
+ return EFI_INVALID_PARAMETER;\r
+}\r
+\r
+/**\r
+ Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r
+ stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r
+ PCI controllers before enumeration.\r
+\r
+ This function is called during the PCI enumeration process. No specific action is expected from this\r
+ member function. It allows the host bridge driver to preinitialize individual PCI controllers before\r
+ enumeration.\r
+\r
+ @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
+ @param RootBridgeHandle The associated PCI root bridge handle. Type EFI_HANDLE is defined in\r
+ InstallProtocolInterface() in the UEFI 2.0 Specification.\r
+ @param PciAddress The address of the PCI device on the PCI bus. This address can be passed to the\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI\r
+ configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for\r
+ the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.\r
+ @param Phase The phase of the PCI device enumeration.\r
+\r
+ @retval EFI_SUCCESS The requested parameters were returned.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in\r
+ EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should\r
+ not enumerate this device, including its child devices if it is a PCI-to-PCI\r
+ bridge.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PreprocessController (\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
+ )\r
+{\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
+ LIST_ENTRY *List;\r
+\r
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
+ List = HostBridgeInstance->Head.ForwardLink;\r
+\r
+ //\r
+ // Enumerate the root bridges in this host bridge\r
+ //\r
+ while (List != &HostBridgeInstance->Head) {\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+ if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
+ break;\r
+ }\r
+ List = List->ForwardLink;\r
+ }\r
+ if (List == &HostBridgeInstance->Head) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if ((UINT32)Phase > EfiPciBeforeResourceCollection) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+/** @file\r
+ The Header file of the Pci Host Bridge Driver\r
+\r
+ Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials are\r
+ licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _PCI_HOST_BRIDGE_H_\r
+#define _PCI_HOST_BRIDGE_H_\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <IndustryStandard/Pci.h>\r
+#include <IndustryStandard/Acpi.h>\r
+\r
+#include <Protocol/PciHostBridgeResourceAllocation.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+#include <Protocol/Metronome.h>\r
+#include <Protocol/DevicePath.h>\r
+\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/DxeServicesTableLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PciLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+//\r
+// Hard code the host bridge number in the platform.\r
+// In this chipset, there is only one host bridge.\r
+//\r
+#define HOST_BRIDGE_NUMBER 1\r
+\r
+#define MAX_PCI_DEVICE_NUMBER 31\r
+#define MAX_PCI_FUNCTION_NUMBER 7\r
+#define MAX_PCI_REG_ADDRESS (SIZE_4KB - 1)\r
+\r
+typedef enum {\r
+ IoOperation,\r
+ MemOperation,\r
+ PciOperation\r
+} OPERATION_TYPE;\r
+\r
+#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32('e', 'h', 's', 't')\r
+typedef struct {\r
+ UINTN Signature;\r
+ EFI_HANDLE HostBridgeHandle;\r
+ UINTN RootBridgeNumber;\r
+ LIST_ENTRY Head;\r
+ BOOLEAN ResourceSubmited;\r
+ BOOLEAN CanRestarted;\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc;\r
+} PCI_HOST_BRIDGE_INSTANCE;\r
+\r
+#define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) \\r
+ CR(a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)\r
+\r
+//\r
+// HostBridge Resource Allocation interface\r
+//\r
+\r
+/**\r
+ These are the notifications from the PCI bus driver that it is about to enter a certain\r
+ phase of the PCI enumeration process.\r
+\r
+ This member function can be used to notify the host bridge driver to perform specific actions,\r
+ including any chipset-specific initialization, so that the chipset is ready to enter the next phase.\r
+ Eight notification points are defined at this time. See belows:\r
+ EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data\r
+ structures. The PCI enumerator should issue this notification\r
+ before starting a fresh enumeration process. Enumeration cannot\r
+ be restarted after sending any other notification such as\r
+ EfiPciHostBridgeBeginBusAllocation.\r
+ EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is\r
+ required here. This notification can be used to perform any\r
+ chipset-specific programming.\r
+ EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No\r
+ specific action is required here. This notification can be used to\r
+ perform any chipset-specific programming.\r
+ EfiPciHostBridgeBeginResourceAllocation\r
+ The resource allocation phase is about to begin. No specific\r
+ action is required here. This notification can be used to perform\r
+ any chipset-specific programming.\r
+ EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI\r
+ root bridges. These resource settings are returned on the next call to\r
+ GetProposedResources(). Before calling NotifyPhase() with a Phase of\r
+ EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible\r
+ for gathering I/O and memory requests for\r
+ all the PCI root bridges and submitting these requests using\r
+ SubmitResources(). This function pads the resource amount\r
+ to suit the root bridge hardware, takes care of dependencies between\r
+ the PCI root bridges, and calls the Global Coherency Domain (GCD)\r
+ with the allocation request. In the case of padding, the allocated range\r
+ could be bigger than what was requested.\r
+ EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated\r
+ resources (proposed resources) for all the PCI root bridges. After the\r
+ hardware is programmed, reassigning resources will not be supported.\r
+ The bus settings are not affected.\r
+ EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI\r
+ root bridges and resets the I/O and memory apertures to their initial\r
+ state. The bus settings are not affected. If the request to allocate\r
+ resources fails, the PCI enumerator can use this notification to\r
+ deallocate previous resources, adjust the requests, and retry\r
+ allocation.\r
+ EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is\r
+ required here. This notification can be used to perform any chipsetspecific\r
+ programming.\r
+\r
+ @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ @param[in] Phase The phase during enumeration\r
+\r
+ @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error\r
+ is valid for a Phase of EfiPciHostBridgeAllocateResources if\r
+ SubmitResources() has not been called for one or more\r
+ PCI root bridges before this call\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid\r
+ for a Phase of EfiPciHostBridgeSetResources.\r
+ @retval EFI_INVALID_PARAMETER Invalid phase parameter\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the\r
+ previously submitted resource requests cannot be fulfilled or\r
+ were only partially fulfilled.\r
+ @retval EFI_SUCCESS The notification was accepted without any errors.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+NotifyPhase(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r
+ );\r
+\r
+/**\r
+ Return the device handle of the next PCI root bridge that is associated with this Host Bridge.\r
+\r
+ This function is called multiple times to retrieve the device handles of all the PCI root bridges that\r
+ are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI\r
+ root bridges. On each call, the handle that was returned by the previous call is passed into the\r
+ interface, and on output the interface returns the device handle of the next PCI root bridge. The\r
+ caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
+ for that root bridge. When there are no more PCI root bridges to report, the interface returns\r
+ EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they\r
+ are returned by this function.\r
+ For D945 implementation, there is only one root bridge in PCI host bridge.\r
+\r
+ @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge.\r
+\r
+ @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the\r
+ specific Host bridge and return EFI_SUCCESS.\r
+ @retval EFI_NOT_FOUND Can not find the any more root bridge in specific host bridge.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was\r
+ returned on a previous call to GetNextRootBridge().\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GetNextRootBridge(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN OUT EFI_HANDLE *RootBridgeHandle\r
+ );\r
+\r
+/**\r
+ Returns the allocation attributes of a PCI root bridge.\r
+\r
+ The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary\r
+ from one PCI root bridge to another. These attributes are different from the decode-related\r
+ attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The\r
+ RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device\r
+ handles of all the root bridges that are associated with this host bridge must be obtained by calling\r
+ GetNextRootBridge(). The attributes are static in the sense that they do not change during or\r
+ after the enumeration process. The hardware may provide mechanisms to change the attributes on\r
+ the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is\r
+ installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in\r
+ "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.\r
+ For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to\r
+ include requests for the prefetchable memory in the nonprefetchable memory pool and not request any\r
+ prefetchable memory.\r
+ Attribute Description\r
+ ------------------------------------ ----------------------------------------------------------------------\r
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root bridge does not support separate\r
+ windows for nonprefetchable and prefetchable memory. A PCI bus\r
+ driver needs to include requests for prefetchable memory in the\r
+ nonprefetchable memory pool.\r
+\r
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root bridge supports 64-bit memory\r
+ windows. If this bit is not set, the PCI bus driver needs to include\r
+ requests for a 64-bit memory address in the corresponding 32-bit\r
+ memory pool.\r
+\r
+ @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested. Type\r
+ EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.\r
+ @param[out] Attributes The pointer to attribte of root bridge, it is output parameter\r
+\r
+ @retval EFI_INVALID_PARAMETER Attribute pointer is NULL\r
+ @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.\r
+ @retval EFI_SUCCESS Success to get attribute of interested root bridge.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GetAttributes(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ OUT UINT64 *Attributes\r
+ );\r
+\r
+/**\r
+ Sets up the specified PCI root bridge for the bus enumeration process.\r
+\r
+ This member function sets up the root bridge for bus enumeration and returns the PCI bus range\r
+ over which the search should be performed in ACPI 2.0 resource descriptor format.\r
+\r
+ @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.\r
+ @param[in] RootBridgeHandle The PCI Root Bridge to be set up.\r
+ @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor.\r
+\r
+ @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle\r
+ @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.\r
+ @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+StartBusEnumeration(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ OUT VOID **Configuration\r
+ );\r
+\r
+/**\r
+ Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.\r
+\r
+ This member function programs the specified PCI root bridge to decode the bus range that is\r
+ specified by the input parameter Configuration.\r
+ The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.\r
+\r
+ @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance\r
+ @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be programmed\r
+ @param[in] Configuration The pointer to the PCI bus resource descriptor\r
+\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.\r
+ @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.\r
+ @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource descriptor.\r
+ @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than\r
+ bus descriptors.\r
+ @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource descriptors.\r
+ @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.\r
+ @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
+ @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SetBusNumbers(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN VOID *Configuration\r
+ );\r
+\r
+/**\r
+ Submits the I/O and memory resource requirements for the specified PCI root bridge.\r
+\r
+ This function is used to submit all the I/O and memory resources that are required by the specified\r
+ PCI root bridge. The input parameter Configuration is used to specify the following:\r
+ - The various types of resources that are required\r
+ - The associated lengths in terms of ACPI 2.0 resource descriptor format\r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
+ @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being submitted.\r
+ @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor.\r
+\r
+ @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were accepted.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.\r
+ @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.\r
+ @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are\r
+ not supported by this PCI root bridge. This error will happen if the caller\r
+ did not combine resources according to Attributes that were returned by\r
+ GetAllocAttributes().\r
+ @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.\r
+ @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SubmitResources(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN VOID *Configuration\r
+ );\r
+\r
+/**\r
+ Returns the proposed resource settings for the specified PCI root bridge.\r
+\r
+ This member function returns the proposed resource settings for the specified PCI root bridge. The\r
+ proposed resource settings are prepared when NotifyPhase() is called with a Phase of\r
+ EfiPciHostBridgeAllocateResources. The output parameter Configuration\r
+ specifies the following:\r
+ - The various types of resources, excluding bus resources, that are allocated\r
+ - The associated lengths in terms of ACPI 2.0 resource descriptor format\r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
+ @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.\r
+ @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.\r
+\r
+ @retval EFI_SUCCESS The requested parameters were returned.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GetProposedResources(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ OUT VOID **Configuration\r
+ );\r
+\r
+/**\r
+ Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r
+ stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r
+ PCI controllers before enumeration.\r
+\r
+ This function is called during the PCI enumeration process. No specific action is expected from this\r
+ member function. It allows the host bridge driver to preinitialize individual PCI controllers before\r
+ enumeration.\r
+\r
+ @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
+ @param RootBridgeHandle The associated PCI root bridge handle. Type EFI_HANDLE is defined in\r
+ InstallProtocolInterface() in the UEFI 2.0 Specification.\r
+ @param PciAddress The address of the PCI device on the PCI bus. This address can be passed to the\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI\r
+ configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for\r
+ the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.\r
+ @param Phase The phase of the PCI device enumeration.\r
+\r
+ @retval EFI_SUCCESS The requested parameters were returned.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in\r
+ EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should\r
+ not enumerate this device, including its child devices if it is a PCI-to-PCI\r
+ bridge.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PreprocessController (\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
+ );\r
+\r
+\r
+//\r
+// Define resource status constant\r
+//\r
+#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL\r
+#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL\r
+\r
+\r
+//\r
+// Driver Instance Data Prototypes\r
+//\r
+\r
+typedef struct {\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;\r
+ UINTN NumberOfBytes;\r
+ UINTN NumberOfPages;\r
+ EFI_PHYSICAL_ADDRESS HostAddress;\r
+ EFI_PHYSICAL_ADDRESS MappedHostAddress;\r
+} MAP_INFO;\r
+\r
+typedef struct {\r
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;\r
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;\r
+\r
+typedef struct {\r
+ UINT64 BusBase;\r
+ UINT64 BusLimit;\r
+\r
+ UINT64 MemBase;\r
+ UINT64 MemLimit;\r
+\r
+ UINT64 IoBase;\r
+ UINT64 IoLimit;\r
+ UINT64 IoTranslation;\r
+} PCI_ROOT_BRIDGE_RESOURCE_APERTURE;\r
+\r
+typedef enum {\r
+ TypeIo = 0,\r
+ TypeMem32,\r
+ TypePMem32,\r
+ TypeMem64,\r
+ TypePMem64,\r
+ TypeBus,\r
+ TypeMax\r
+} PCI_RESOURCE_TYPE;\r
+\r
+typedef enum {\r
+ ResNone = 0,\r
+ ResSubmitted,\r
+ ResRequested,\r
+ ResAllocated,\r
+ ResStatusMax\r
+} RES_STATUS;\r
+\r
+typedef struct {\r
+ PCI_RESOURCE_TYPE Type;\r
+ UINT64 Base;\r
+ UINT64 Length;\r
+ UINT64 Alignment;\r
+ RES_STATUS Status;\r
+} PCI_RES_NODE;\r
+\r
+#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32('e', '2', 'p', 'b')\r
+\r
+typedef struct {\r
+ UINT32 Signature;\r
+ LIST_ENTRY Link;\r
+ EFI_HANDLE Handle;\r
+ UINT64 RootBridgeAttrib;\r
+ UINT64 Attributes;\r
+ UINT64 Supports;\r
+\r
+ //\r
+ // Specific for this memory controller: Bus, I/O, Mem\r
+ //\r
+ PCI_RES_NODE ResAllocNode[6];\r
+\r
+ //\r
+ // Addressing for Memory and I/O and Bus arrange\r
+ //\r
+ UINT64 BusBase;\r
+ UINT64 MemBase;\r
+ UINT64 IoBase;\r
+ UINT64 BusLimit;\r
+ UINT64 MemLimit;\r
+ UINT64 IoLimit;\r
+ UINT64 IoTranslation;\r
+\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;\r
+\r
+} PCI_ROOT_BRIDGE_INSTANCE;\r
+\r
+\r
+//\r
+// Driver Instance Data Macros\r
+//\r
+#define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \\r
+ CR(a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE)\r
+\r
+\r
+#define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) \\r
+ CR(a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)\r
+\r
+/**\r
+\r
+ Construct the Pci Root Bridge Io protocol\r
+\r
+ @param Protocol Point to protocol instance\r
+ @param HostBridgeHandle Handle of host bridge\r
+ @param Attri Attribute of host bridge\r
+ @param ResAperture ResourceAperture for host bridge\r
+\r
+ @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.\r
+\r
+**/\r
+EFI_STATUS\r
+RootBridgeConstructor (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,\r
+ IN EFI_HANDLE HostBridgeHandle,\r
+ IN UINT64 Attri,\r
+ IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture\r
+ );\r
+\r
+#endif\r
--- /dev/null
+## @file\r
+# The basic interfaces implementation to a single segment PCI Host Bridge driver.\r
+#\r
+# Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PciHostBridge\r
+ FILE_GUID = 9f609346-37cb-4eb7-801f-f55099373998\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+\r
+ ENTRY_POINT = InitializePciHostBridge\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+ ArmVirtPkg/ArmVirtPkg.dec\r
+\r
+[LibraryClasses]\r
+ UefiDriverEntryPoint\r
+ UefiBootServicesTableLib\r
+ DxeServicesTableLib\r
+ UefiLib\r
+ MemoryAllocationLib\r
+ BaseMemoryLib\r
+ BaseLib\r
+ DebugLib\r
+ DevicePathLib\r
+ IoLib\r
+ PciLib\r
+ PcdLib\r
+\r
+[Sources]\r
+ PciHostBridge.c\r
+ PciRootBridgeIo.c\r
+ PciHostBridge.h\r
+\r
+[Protocols]\r
+ gEfiPciHostBridgeResourceAllocationProtocolGuid ## PRODUCES\r
+ gEfiPciRootBridgeIoProtocolGuid ## PRODUCES\r
+ gEfiMetronomeArchProtocolGuid ## CONSUMES\r
+ gEfiDevicePathProtocolGuid ## PRODUCES\r
+\r
+[Pcd]\r
+ gArmPlatformTokenSpaceGuid.PcdPciBusMin\r
+ gArmPlatformTokenSpaceGuid.PcdPciBusMax\r
+ gArmPlatformTokenSpaceGuid.PcdPciIoBase\r
+ gArmPlatformTokenSpaceGuid.PcdPciIoSize\r
+ gArmPlatformTokenSpaceGuid.PcdPciIoTranslation\r
+ gArmPlatformTokenSpaceGuid.PcdPciMmio32Base\r
+ gArmPlatformTokenSpaceGuid.PcdPciMmio32Size\r
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
+\r
+[FeaturePcd]\r
+ gArmVirtTokenSpaceGuid.PcdKludgeMapPciMmioAsCached\r
+\r
+[depex]\r
+ gEfiMetronomeArchProtocolGuid AND\r
+ gEfiCpuArchProtocolGuid\r
--- /dev/null
+/** @file\r
+ PCI Root Bridge Io Protocol implementation\r
+\r
+Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials are\r
+licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "PciHostBridge.h"\r
+\r
+typedef struct {\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR SpaceDesp[TypeMax];\r
+ EFI_ACPI_END_TAG_DESCRIPTOR EndDesp;\r
+} RESOURCE_CONFIGURATION;\r
+\r
+RESOURCE_CONFIGURATION Configuration = {\r
+ {{0x8A, 0x2B, 1, 0, 0, 0, 0, 0, 0, 0},\r
+ {0x8A, 0x2B, 0, 0, 0, 32, 0, 0, 0, 0},\r
+ {0x8A, 0x2B, 0, 0, 6, 32, 0, 0, 0, 0},\r
+ {0x8A, 0x2B, 0, 0, 0, 64, 0, 0, 0, 0},\r
+ {0x8A, 0x2B, 0, 0, 6, 64, 0, 0, 0, 0},\r
+ {0x8A, 0x2B, 2, 0, 0, 0, 0, 0, 0, 0}},\r
+ {0x79, 0}\r
+};\r
+\r
+//\r
+// Protocol Member Function Prototypes\r
+//\r
+\r
+/**\r
+ Polls an address in memory mapped I/O space until an exit condition is met, or\r
+ a timeout occurs.\r
+\r
+ This function provides a standard way to poll a PCI memory location. A PCI memory read\r
+ operation is performed at the PCI memory address specified by Address for the width specified\r
+ by Width. The result of this PCI memory read operation is stored in Result. This PCI memory\r
+ read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result &\r
+ Mask) is equal to Value.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Width Signifies the width of the memory operations.\r
+ @param[in] Address The base address of the memory operations. The caller is\r
+ responsible for aligning Address if required.\r
+ @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask\r
+ are ignored. The bits in the bytes below Width which are zero in\r
+ Mask are ignored when polling the memory address.\r
+ @param[in] Value The comparison value used for the polling exit criteria.\r
+ @param[in] Delay The number of 100 ns units to poll. Note that timer available may\r
+ be of poorer granularity.\r
+ @param[out] Result Pointer to the last value read from the memory location.\r
+\r
+ @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid.\r
+ @retval EFI_INVALID_PARAMETER Result is NULL.\r
+ @retval EFI_TIMEOUT Delay expired before a match occurred.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoPollMem (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINT64 Mask,\r
+ IN UINT64 Value,\r
+ IN UINT64 Delay,\r
+ OUT UINT64 *Result\r
+ );\r
+\r
+/**\r
+ Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r
+ satisfied or after a defined duration.\r
+\r
+ This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is\r
+ performed at the PCI I/O address specified by Address for the width specified by Width.\r
+ The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is\r
+ repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal\r
+ to Value.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Width Signifies the width of the I/O operations.\r
+ @param[in] Address The base address of the I/O operations. The caller is responsible\r
+ for aligning Address if required.\r
+ @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask\r
+ are ignored. The bits in the bytes below Width which are zero in\r
+ Mask are ignored when polling the I/O address.\r
+ @param[in] Value The comparison value used for the polling exit criteria.\r
+ @param[in] Delay The number of 100 ns units to poll. Note that timer available may\r
+ be of poorer granularity.\r
+ @param[out] Result Pointer to the last value read from the memory location.\r
+\r
+ @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid.\r
+ @retval EFI_INVALID_PARAMETER Result is NULL.\r
+ @retval EFI_TIMEOUT Delay expired before a match occurred.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoPollIo (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINT64 Mask,\r
+ IN UINT64 Value,\r
+ IN UINT64 Delay,\r
+ OUT UINT64 *Result\r
+ );\r
+\r
+/**\r
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
+\r
+ The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller\r
+ registers in the PCI root bridge memory space.\r
+ The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
+ any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Width Signifies the width of the memory operation.\r
+ @param[in] Address The base address of the memory operation. The caller is\r
+ responsible for aligning the Address if required.\r
+ @param[in] Count The number of memory operations to perform. Bytes moved is\r
+ Width size * Count, starting at Address.\r
+ @param[out] Buffer For read operations, the destination buffer to store the results. For\r
+ write operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoMemRead (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
+\r
+ The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller\r
+ registers in the PCI root bridge memory space.\r
+ The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
+ any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Width Signifies the width of the memory operation.\r
+ @param[in] Address The base address of the memory operation. The caller is\r
+ responsible for aligning the Address if required.\r
+ @param[in] Count The number of memory operations to perform. Bytes moved is\r
+ Width size * Count, starting at Address.\r
+ @param[in] Buffer For read operations, the destination buffer to store the results. For\r
+ write operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoMemWrite (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Width Signifies the width of the memory operations.\r
+ @param[in] UserAddress The base address of the I/O operation. The caller is responsible for\r
+ aligning the Address if required.\r
+ @param[in] Count The number of I/O operations to perform. Bytes moved is Width\r
+ size * Count, starting at Address.\r
+ @param[out] UserBuffer For read operations, the destination buffer to store the results. For\r
+ write operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoIoRead (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 UserAddress,\r
+ IN UINTN Count,\r
+ OUT VOID *UserBuffer\r
+ );\r
+\r
+/**\r
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Width Signifies the width of the memory operations.\r
+ @param[in] UserAddress The base address of the I/O operation. The caller is responsible for\r
+ aligning the Address if required.\r
+ @param[in] Count The number of I/O operations to perform. Bytes moved is Width\r
+ size * Count, starting at Address.\r
+ @param[in] UserBuffer For read operations, the destination buffer to store the results. For\r
+ write operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoIoWrite (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 UserAddress,\r
+ IN UINTN Count,\r
+ IN VOID *UserBuffer\r
+ );\r
+\r
+/**\r
+ Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI\r
+ root bridge memory space.\r
+\r
+ The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory\r
+ space to another region of PCI root bridge memory space. This is especially useful for video scroll\r
+ operation on a memory mapped video buffer.\r
+ The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
+ any alignment and memory width restrictions that a PCI root bridge on a platform might require.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
+ @param[in] Width Signifies the width of the memory operations.\r
+ @param[in] DestAddress The destination address of the memory operation. The caller is\r
+ responsible for aligning the DestAddress if required.\r
+ @param[in] SrcAddress The source address of the memory operation. The caller is\r
+ responsible for aligning the SrcAddress if required.\r
+ @param[in] Count The number of memory operations to perform. Bytes moved is\r
+ Width size * Count, starting at DestAddress and SrcAddress.\r
+\r
+ @retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoCopyMem (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 DestAddress,\r
+ IN UINT64 SrcAddress,\r
+ IN UINTN Count\r
+ );\r
+\r
+/**\r
+ Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.\r
+\r
+ The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration\r
+ registers for a PCI controller.\r
+ The PCI Configuration operations are carried out exactly as requested. The caller is responsible for\r
+ any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might\r
+ require.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Width Signifies the width of the memory operations.\r
+ @param[in] Address The address within the PCI configuration space for the PCI controller.\r
+ @param[in] Count The number of PCI configuration operations to perform. Bytes\r
+ moved is Width size * Count, starting at Address.\r
+ @param[out] Buffer For read operations, the destination buffer to store the results. For\r
+ write operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoPciRead (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.\r
+\r
+ The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration\r
+ registers for a PCI controller.\r
+ The PCI Configuration operations are carried out exactly as requested. The caller is responsible for\r
+ any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might\r
+ require.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Width Signifies the width of the memory operations.\r
+ @param[in] Address The address within the PCI configuration space for the PCI controller.\r
+ @param[in] Count The number of PCI configuration operations to perform. Bytes\r
+ moved is Width size * Count, starting at Address.\r
+ @param[in] Buffer For read operations, the destination buffer to store the results. For\r
+ write operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoPciWrite (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Provides the PCI controller-specific addresses required to access system memory from a\r
+ DMA bus master.\r
+\r
+ The Map() function provides the PCI controller specific addresses needed to access system\r
+ memory. This function is used to map system memory for PCI bus master DMA accesses.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Operation Indicates if the bus master is going to read or write to system memory.\r
+ @param[in] HostAddress The system memory address to map to the PCI controller.\r
+ @param[in, out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.\r
+ @param[out] DeviceAddress The resulting map address for the bus master PCI controller to use\r
+ to access the system memory's HostAddress.\r
+ @param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete.\r
+\r
+ @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
+ @retval EFI_INVALID_PARAMETER Operation is invalid.\r
+ @retval EFI_INVALID_PARAMETER HostAddress is NULL.\r
+ @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL.\r
+ @retval EFI_INVALID_PARAMETER DeviceAddress is NULL.\r
+ @retval EFI_INVALID_PARAMETER Mapping is NULL.\r
+ @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r
+ @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoMap (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,\r
+ IN VOID *HostAddress,\r
+ IN OUT UINTN *NumberOfBytes,\r
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
+ OUT VOID **Mapping\r
+ );\r
+\r
+/**\r
+ Completes the Map() operation and releases any corresponding resources.\r
+\r
+ The Unmap() function completes the Map() operation and releases any corresponding resources.\r
+ If the operation was an EfiPciOperationBusMasterWrite or\r
+ EfiPciOperationBusMasterWrite64, the data is committed to the target system memory.\r
+ Any resources used for the mapping are freed.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Mapping The mapping value returned from Map().\r
+\r
+ @retval EFI_SUCCESS The range was unmapped.\r
+ @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r
+ @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoUnmap (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN VOID *Mapping\r
+ );\r
+\r
+/**\r
+ Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or\r
+ EfiPciOperationBusMasterCommonBuffer64 mapping.\r
+\r
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param Type This parameter is not used and must be ignored.\r
+ @param MemoryType The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.\r
+ @param Pages The number of pages to allocate.\r
+ @param HostAddress A pointer to store the base system memory address of the allocated range.\r
+ @param Attributes The requested bit mask of attributes for the allocated range. Only\r
+ the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED,\r
+ and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.\r
+\r
+ @retval EFI_SUCCESS The requested memory pages were allocated.\r
+ @retval EFI_INVALID_PARAMETER MemoryType is invalid.\r
+ @retval EFI_INVALID_PARAMETER HostAddress is NULL.\r
+ @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
+ MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.\r
+ @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoAllocateBuffer (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_ALLOCATE_TYPE Type,\r
+ IN EFI_MEMORY_TYPE MemoryType,\r
+ IN UINTN Pages,\r
+ OUT VOID **HostAddress,\r
+ IN UINT64 Attributes\r
+ );\r
+\r
+/**\r
+ Frees memory that was allocated with AllocateBuffer().\r
+\r
+ The FreeBuffer() function frees memory that was allocated with AllocateBuffer().\r
+\r
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param Pages The number of pages to free.\r
+ @param HostAddress The base system memory address of the allocated range.\r
+\r
+ @retval EFI_SUCCESS The requested memory pages were freed.\r
+ @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
+ was not allocated with AllocateBuffer().\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoFreeBuffer (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN UINTN Pages,\r
+ OUT VOID *HostAddress\r
+ );\r
+\r
+/**\r
+ Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
+\r
+ The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system\r
+ memory. Posted write transactions are generated by PCI bus masters when they perform write\r
+ transactions to target addresses in system memory.\r
+ This function does not flush posted write transactions from any PCI bridges. A PCI controller\r
+ specific action must be taken to guarantee that the posted write transactions have been flushed from\r
+ the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with\r
+ a PCI read transaction from the PCI controller prior to calling Flush().\r
+\r
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+\r
+ @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r
+ bridge to system memory.\r
+ @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r
+ host bridge due to a hardware error.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoFlush (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This\r
+ );\r
+\r
+/**\r
+ Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the\r
+ attributes that a PCI root bridge is currently using.\r
+\r
+ The GetAttributes() function returns the mask of attributes that this PCI root bridge supports\r
+ and the mask of attributes that the PCI root bridge is currently using.\r
+\r
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param Supported A pointer to the mask of attributes that this PCI root bridge\r
+ supports setting with SetAttributes().\r
+ @param Attributes A pointer to the mask of attributes that this PCI root bridge is\r
+ currently using.\r
+\r
+ @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root\r
+ bridge supports is returned in Supports. If Attributes is\r
+ not NULL, then the attributes that the PCI root bridge is currently\r
+ using is returned in Attributes.\r
+ @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoGetAttributes (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ OUT UINT64 *Supported,\r
+ OUT UINT64 *Attributes\r
+ );\r
+\r
+/**\r
+ Sets attributes for a resource range on a PCI root bridge.\r
+\r
+ The SetAttributes() function sets the attributes specified in Attributes for the PCI root\r
+ bridge on the resource range specified by ResourceBase and ResourceLength. Since the\r
+ granularity of setting these attributes may vary from resource type to resource type, and from\r
+ platform to platform, the actual resource range and the one passed in by the caller may differ. As a\r
+ result, this function may set the attributes specified by Attributes on a larger resource range\r
+ than the caller requested. The actual range is returned in ResourceBase and\r
+ ResourceLength. The caller is responsible for verifying that the actual range for which the\r
+ attributes were set is acceptable.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Attributes The mask of attributes to set. If the attribute bit\r
+ MEMORY_WRITE_COMBINE, MEMORY_CACHED, or\r
+ MEMORY_DISABLE is set, then the resource range is specified by\r
+ ResourceBase and ResourceLength. If\r
+ MEMORY_WRITE_COMBINE, MEMORY_CACHED, and\r
+ MEMORY_DISABLE are not set, then ResourceBase and\r
+ ResourceLength are ignored, and may be NULL.\r
+ @param[in, out] ResourceBase A pointer to the base address of the resource range to be modified\r
+ by the attributes specified by Attributes.\r
+ @param[in, out] ResourceLength A pointer to the length of the resource range to be modified by the\r
+ attributes specified by Attributes.\r
+\r
+ @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.\r
+ @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.\r
+ @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoSetAttributes (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN UINT64 Attributes,\r
+ IN OUT UINT64 *ResourceBase,\r
+ IN OUT UINT64 *ResourceLength\r
+ );\r
+\r
+/**\r
+ Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0\r
+ resource descriptors.\r
+\r
+ There are only two resource descriptor types from the ACPI Specification that may be used to\r
+ describe the current resources allocated to a PCI root bridge. These are the QWORD Address\r
+ Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The\r
+ QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic\r
+ or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD\r
+ Address Space Descriptors followed by an End Tag.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that describe the\r
+ current configuration of this PCI root bridge. The storage for the\r
+ ACPI 2.0 resource descriptors is allocated by this function. The\r
+ caller must treat the return buffer as read-only data, and the buffer\r
+ must not be freed by the caller.\r
+\r
+ @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.\r
+ @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.\r
+ @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoConfiguration (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ OUT VOID **Resources\r
+ );\r
+\r
+//\r
+// Memory Controller Pci Root Bridge Io Module Variables\r
+//\r
+EFI_METRONOME_ARCH_PROTOCOL *mMetronome;\r
+\r
+//\r
+// Lookup table for increment values based on transfer widths\r
+//\r
+UINT8 mInStride[] = {\r
+ 1, // EfiPciWidthUint8\r
+ 2, // EfiPciWidthUint16\r
+ 4, // EfiPciWidthUint32\r
+ 8, // EfiPciWidthUint64\r
+ 0, // EfiPciWidthFifoUint8\r
+ 0, // EfiPciWidthFifoUint16\r
+ 0, // EfiPciWidthFifoUint32\r
+ 0, // EfiPciWidthFifoUint64\r
+ 1, // EfiPciWidthFillUint8\r
+ 2, // EfiPciWidthFillUint16\r
+ 4, // EfiPciWidthFillUint32\r
+ 8 // EfiPciWidthFillUint64\r
+};\r
+\r
+//\r
+// Lookup table for increment values based on transfer widths\r
+//\r
+UINT8 mOutStride[] = {\r
+ 1, // EfiPciWidthUint8\r
+ 2, // EfiPciWidthUint16\r
+ 4, // EfiPciWidthUint32\r
+ 8, // EfiPciWidthUint64\r
+ 1, // EfiPciWidthFifoUint8\r
+ 2, // EfiPciWidthFifoUint16\r
+ 4, // EfiPciWidthFifoUint32\r
+ 8, // EfiPciWidthFifoUint64\r
+ 0, // EfiPciWidthFillUint8\r
+ 0, // EfiPciWidthFillUint16\r
+ 0, // EfiPciWidthFillUint32\r
+ 0 // EfiPciWidthFillUint64\r
+};\r
+\r
+/**\r
+\r
+ Construct the Pci Root Bridge Io protocol\r
+\r
+ @param Protocol Point to protocol instance\r
+ @param HostBridgeHandle Handle of host bridge\r
+ @param Attri Attribute of host bridge\r
+ @param ResAperture ResourceAperture for host bridge\r
+\r
+ @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.\r
+\r
+**/\r
+EFI_STATUS\r
+RootBridgeConstructor (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,\r
+ IN EFI_HANDLE HostBridgeHandle,\r
+ IN UINT64 Attri,\r
+ IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
+ PCI_RESOURCE_TYPE Index;\r
+\r
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (Protocol);\r
+\r
+ //\r
+ // The host to PCI bridge. The host memory addresses are direct mapped to PCI\r
+ // addresses, so there's no need to translate them. IO addresses need\r
+ // translation however.\r
+ //\r
+ PrivateData->MemBase = ResAperture->MemBase;\r
+ PrivateData->IoBase = ResAperture->IoBase;\r
+ PrivateData->IoTranslation = ResAperture->IoTranslation;\r
+\r
+ //\r
+ // The host bridge only supports 32bit addressing for memory\r
+ // and standard IA32 16bit io\r
+ //\r
+ PrivateData->MemLimit = ResAperture->MemLimit;\r
+ PrivateData->IoLimit = ResAperture->IoLimit;\r
+\r
+ //\r
+ // Bus Aperture for this Root Bridge (Possible Range)\r
+ //\r
+ PrivateData->BusBase = ResAperture->BusBase;\r
+ PrivateData->BusLimit = ResAperture->BusLimit;\r
+\r
+ //\r
+ // Specific for this chipset\r
+ //\r
+ for (Index = TypeIo; Index < TypeMax; Index++) {\r
+ PrivateData->ResAllocNode[Index].Type = Index;\r
+ PrivateData->ResAllocNode[Index].Base = 0;\r
+ PrivateData->ResAllocNode[Index].Length = 0;\r
+ PrivateData->ResAllocNode[Index].Status = ResNone;\r
+ }\r
+\r
+ PrivateData->RootBridgeAttrib = Attri;\r
+\r
+ PrivateData->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | \\r
+ EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \\r
+ EFI_PCI_ATTRIBUTE_VGA_MEMORY | \\r
+ EFI_PCI_ATTRIBUTE_VGA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+ PrivateData->Attributes = PrivateData->Supports;\r
+\r
+ Protocol->ParentHandle = HostBridgeHandle;\r
+\r
+ Protocol->PollMem = RootBridgeIoPollMem;\r
+ Protocol->PollIo = RootBridgeIoPollIo;\r
+\r
+ Protocol->Mem.Read = RootBridgeIoMemRead;\r
+ Protocol->Mem.Write = RootBridgeIoMemWrite;\r
+\r
+ Protocol->Io.Read = RootBridgeIoIoRead;\r
+ Protocol->Io.Write = RootBridgeIoIoWrite;\r
+\r
+ Protocol->CopyMem = RootBridgeIoCopyMem;\r
+\r
+ Protocol->Pci.Read = RootBridgeIoPciRead;\r
+ Protocol->Pci.Write = RootBridgeIoPciWrite;\r
+\r
+ Protocol->Map = RootBridgeIoMap;\r
+ Protocol->Unmap = RootBridgeIoUnmap;\r
+\r
+ Protocol->AllocateBuffer = RootBridgeIoAllocateBuffer;\r
+ Protocol->FreeBuffer = RootBridgeIoFreeBuffer;\r
+\r
+ Protocol->Flush = RootBridgeIoFlush;\r
+\r
+ Protocol->GetAttributes = RootBridgeIoGetAttributes;\r
+ Protocol->SetAttributes = RootBridgeIoSetAttributes;\r
+\r
+ Protocol->Configuration = RootBridgeIoConfiguration;\r
+\r
+ Protocol->SegmentNumber = 0;\r
+\r
+ Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **)&mMetronome);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.\r
+\r
+ The I/O operations are carried out exactly as requested. The caller is responsible\r
+ for satisfying any alignment and I/O width restrictions that a PI System on a\r
+ platform might require. For example on some platforms, width requests of\r
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
+ be handled by the driver.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] OperationType I/O operation type: IO/MMIO/PCI.\r
+ @param[in] Width Signifies the width of the I/O or Memory operation.\r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Count The number of I/O operations to perform. The number of\r
+ bytes moved is Width size * Count, starting at Address.\r
+ @param[in] Buffer For read operations, the destination buffer to store the results.\r
+ For write operations, the source buffer from which to write data.\r
+\r
+ @retval EFI_SUCCESS The parameters for this request pass the checks.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
+ and Count is not valid for this PI system.\r
+\r
+**/\r
+EFI_STATUS\r
+RootBridgeIoCheckParameter (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN OPERATION_TYPE OperationType,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;\r
+ UINT32 Stride;\r
+ UINT64 Base;\r
+ UINT64 Limit;\r
+\r
+ //\r
+ // Check to see if Buffer is NULL\r
+ //\r
+ if (Buffer == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Check to see if Width is in the valid range\r
+ //\r
+ if ((UINT32)Width >= EfiPciWidthMaximum) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // For FIFO type, the target address won't increase during the access,\r
+ // so treat Count as 1\r
+ //\r
+ if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {\r
+ Count = 1;\r
+ }\r
+\r
+ //\r
+ // Check to see if Width is in the valid range for I/O Port operations\r
+ //\r
+ Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ if ((OperationType != MemOperation) && (Width == EfiPciWidthUint64)) {\r
+ ASSERT (FALSE);\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Check to see if Address is aligned\r
+ //\r
+ Stride = mInStride[Width];\r
+ if ((Address & (UINT64)(Stride - 1)) != 0) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
+\r
+ //\r
+ // Check to see if any address associated with this transfer exceeds the maximum\r
+ // allowed address. The maximum address implied by the parameters passed in is\r
+ // Address + Size * Count. If the following condition is met, then the transfer\r
+ // is not supported.\r
+ //\r
+ // Address + Size * Count > Limit + 1\r
+ //\r
+ // Since Limit can be the maximum integer value supported by the CPU and Count\r
+ // can also be the maximum integer value supported by the CPU, this range\r
+ // check must be adjusted to avoid all oveflow conditions.\r
+ //\r
+ if (OperationType == IoOperation) {\r
+ Base = PrivateData->IoBase;\r
+ Limit = PrivateData->IoLimit;\r
+ } else if (OperationType == MemOperation) {\r
+ Base = PrivateData->MemBase;\r
+ Limit = PrivateData->MemLimit;\r
+ } else {\r
+ PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;\r
+ if (PciRbAddr->Bus < PrivateData->BusBase || PciRbAddr->Bus > PrivateData->BusLimit) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (PciRbAddr->Device > MAX_PCI_DEVICE_NUMBER || PciRbAddr->Function > MAX_PCI_FUNCTION_NUMBER) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (PciRbAddr->ExtendedRegister != 0) {\r
+ Address = PciRbAddr->ExtendedRegister;\r
+ } else {\r
+ Address = PciRbAddr->Register;\r
+ }\r
+ Base = 0;\r
+ Limit = MAX_PCI_REG_ADDRESS;\r
+ }\r
+\r
+ if (Limit < Address) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (Address < Base) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Base <= Address <= Limit\r
+ //\r
+ if (Address == 0 && Limit == MAX_UINT64) {\r
+ //\r
+ // 2^64 bytes are valid to transfer. With Stride == 1, that's simply\r
+ // impossible to reach in Count; with Stride in {2, 4, 8}, we can divide\r
+ // both 2^64 and Stride with 2.\r
+ //\r
+ if (Stride > 1 && Count > DivU64x32 (BIT63, Stride / 2)) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+ } else {\r
+ //\r
+ // (Limit - Address) does not wrap, and it is smaller than MAX_UINT64.\r
+ //\r
+ if (Count > DivU64x32 (Limit - Address + 1, Stride)) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Internal help function for read and write memory space.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Write Switch value for Read or Write.\r
+ @param[in] Width Signifies the width of the memory operations.\r
+ @param[in] UserAddress The address within the PCI configuration space for the PCI controller.\r
+ @param[in] Count The number of PCI configuration operations to perform. Bytes\r
+ moved is Width size * Count, starting at Address.\r
+ @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For\r
+ write operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+RootBridgeIoMemRW (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN BOOLEAN Write,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINT8 InStride;\r
+ UINT8 OutStride;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;\r
+ UINT8 *Uint8Buffer;\r
+\r
+ Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address, Count, Buffer);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ InStride = mInStride[Width];\r
+ OutStride = mOutStride[Width];\r
+ OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
+ if (Write) {\r
+ switch (OperationWidth) {\r
+ case EfiPciWidthUint8:\r
+ MmioWrite8 ((UINTN)Address, *Uint8Buffer);\r
+ break;\r
+ case EfiPciWidthUint16:\r
+ MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));\r
+ break;\r
+ case EfiPciWidthUint32:\r
+ MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));\r
+ break;\r
+ case EfiPciWidthUint64:\r
+ MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));\r
+ break;\r
+ default:\r
+ //\r
+ // The RootBridgeIoCheckParameter call above will ensure that this\r
+ // path is not taken.\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
+ }\r
+ } else {\r
+ switch (OperationWidth) {\r
+ case EfiPciWidthUint8:\r
+ *Uint8Buffer = MmioRead8 ((UINTN)Address);\r
+ break;\r
+ case EfiPciWidthUint16:\r
+ *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);\r
+ break;\r
+ case EfiPciWidthUint32:\r
+ *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);\r
+ break;\r
+ case EfiPciWidthUint64:\r
+ *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);\r
+ break;\r
+ default:\r
+ //\r
+ // The RootBridgeIoCheckParameter call above will ensure that this\r
+ // path is not taken.\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Internal help function for read and write IO space.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Write Switch value for Read or Write.\r
+ @param[in] Width Signifies the width of the memory operations.\r
+ @param[in] UserAddress The address within the PCI configuration space for the PCI controller.\r
+ @param[in] Count The number of PCI configuration operations to perform. Bytes\r
+ moved is Width size * Count, starting at Address.\r
+ @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For\r
+ write operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+RootBridgeIoIoRW (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN BOOLEAN Write,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
+ UINT8 InStride;\r
+ UINT8 OutStride;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;\r
+ UINT8 *Uint8Buffer;\r
+\r
+ Status = RootBridgeIoCheckParameter (This, IoOperation, Width, Address, Count, Buffer);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
+ //\r
+ // The addition below is performed in UINT64 modular arithmetic, in\r
+ // accordance with the definition of PcdPciIoTranslation in\r
+ // "ArmPlatformPkg.dec". Meaning, the addition below may in fact *decrease*\r
+ // Address, implementing a negative offset translation.\r
+ //\r
+ Address += PrivateData->IoTranslation;\r
+\r
+ InStride = mInStride[Width];\r
+ OutStride = mOutStride[Width];\r
+ OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+\r
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
+ if (Write) {\r
+ switch (OperationWidth) {\r
+ case EfiPciWidthUint8:\r
+ MmioWrite8 ((UINTN)Address, *Uint8Buffer);\r
+ break;\r
+ case EfiPciWidthUint16:\r
+ MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));\r
+ break;\r
+ case EfiPciWidthUint32:\r
+ MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));\r
+ break;\r
+ default:\r
+ //\r
+ // The RootBridgeIoCheckParameter call above will ensure that this\r
+ // path is not taken.\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
+ }\r
+ } else {\r
+ switch (OperationWidth) {\r
+ case EfiPciWidthUint8:\r
+ *Uint8Buffer = MmioRead8 ((UINTN)Address);\r
+ break;\r
+ case EfiPciWidthUint16:\r
+ *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);\r
+ break;\r
+ case EfiPciWidthUint32:\r
+ *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);\r
+ break;\r
+ default:\r
+ //\r
+ // The RootBridgeIoCheckParameter call above will ensure that this\r
+ // path is not taken.\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Internal help function for read and write PCI configuration space.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Write Switch value for Read or Write.\r
+ @param[in] Width Signifies the width of the memory operations.\r
+ @param[in] UserAddress The address within the PCI configuration space for the PCI controller.\r
+ @param[in] Count The number of PCI configuration operations to perform. Bytes\r
+ moved is Width size * Count, starting at Address.\r
+ @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For\r
+ write operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+RootBridgeIoPciRW (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN BOOLEAN Write,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINT8 InStride;\r
+ UINT8 OutStride;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;\r
+ UINT8 *Uint8Buffer;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;\r
+ UINTN PcieRegAddr;\r
+\r
+ Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address, Count, Buffer);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;\r
+\r
+ PcieRegAddr = (UINTN) PCI_LIB_ADDRESS (\r
+ PciRbAddr->Bus,\r
+ PciRbAddr->Device,\r
+ PciRbAddr->Function,\r
+ (PciRbAddr->ExtendedRegister != 0) ? \\r
+ PciRbAddr->ExtendedRegister :\r
+ PciRbAddr->Register\r
+ );\r
+\r
+ InStride = mInStride[Width];\r
+ OutStride = mOutStride[Width];\r
+ OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ for (Uint8Buffer = Buffer; Count > 0; PcieRegAddr += InStride, Uint8Buffer += OutStride, Count--) {\r
+ if (Write) {\r
+ switch (OperationWidth) {\r
+ case EfiPciWidthUint8:\r
+ PciWrite8 (PcieRegAddr, *Uint8Buffer);\r
+ break;\r
+ case EfiPciWidthUint16:\r
+ PciWrite16 (PcieRegAddr, *((UINT16 *)Uint8Buffer));\r
+ break;\r
+ case EfiPciWidthUint32:\r
+ PciWrite32 (PcieRegAddr, *((UINT32 *)Uint8Buffer));\r
+ break;\r
+ default:\r
+ //\r
+ // The RootBridgeIoCheckParameter call above will ensure that this\r
+ // path is not taken.\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
+ }\r
+ } else {\r
+ switch (OperationWidth) {\r
+ case EfiPciWidthUint8:\r
+ *Uint8Buffer = PciRead8 (PcieRegAddr);\r
+ break;\r
+ case EfiPciWidthUint16:\r
+ *((UINT16 *)Uint8Buffer) = PciRead16 (PcieRegAddr);\r
+ break;\r
+ case EfiPciWidthUint32:\r
+ *((UINT32 *)Uint8Buffer) = PciRead32 (PcieRegAddr);\r
+ break;\r
+ default:\r
+ //\r
+ // The RootBridgeIoCheckParameter call above will ensure that this\r
+ // path is not taken.\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Polls an address in memory mapped I/O space until an exit condition is met, or\r
+ a timeout occurs.\r
+\r
+ This function provides a standard way to poll a PCI memory location. A PCI memory read\r
+ operation is performed at the PCI memory address specified by Address for the width specified\r
+ by Width. The result of this PCI memory read operation is stored in Result. This PCI memory\r
+ read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result &\r
+ Mask) is equal to Value.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Width Signifies the width of the memory operations.\r
+ @param[in] Address The base address of the memory operations. The caller is\r
+ responsible for aligning Address if required.\r
+ @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask\r
+ are ignored. The bits in the bytes below Width which are zero in\r
+ Mask are ignored when polling the memory address.\r
+ @param[in] Value The comparison value used for the polling exit criteria.\r
+ @param[in] Delay The number of 100 ns units to poll. Note that timer available may\r
+ be of poorer granularity.\r
+ @param[out] Result Pointer to the last value read from the memory location.\r
+\r
+ @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid.\r
+ @retval EFI_INVALID_PARAMETER Result is NULL.\r
+ @retval EFI_TIMEOUT Delay expired before a match occurred.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoPollMem (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINT64 Mask,\r
+ IN UINT64 Value,\r
+ IN UINT64 Delay,\r
+ OUT UINT64 *Result\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINT64 NumberOfTicks;\r
+ UINT32 Remainder;\r
+\r
+ if (Result == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if ((UINT32)Width > EfiPciWidthUint64) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // No matter what, always do a single poll.\r
+ //\r
+ Status = This->Mem.Read (This, Width, Address, 1, Result);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ if ((*Result & Mask) == Value) {\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ if (Delay == 0) {\r
+ return EFI_SUCCESS;\r
+\r
+ } else {\r
+\r
+ //\r
+ // Determine the proper # of metronome ticks to wait for polling the\r
+ // location. The nuber of ticks is Roundup (Delay / mMetronome->TickPeriod)+1\r
+ // The "+1" to account for the possibility of the first tick being short\r
+ // because we started in the middle of a tick.\r
+ //\r
+ // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome\r
+ // protocol definition is updated.\r
+ //\r
+ NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod, &Remainder);\r
+ if (Remainder != 0) {\r
+ NumberOfTicks += 1;\r
+ }\r
+ NumberOfTicks += 1;\r
+\r
+ while (NumberOfTicks != 0) {\r
+\r
+ mMetronome->WaitForTick (mMetronome, 1);\r
+\r
+ Status = This->Mem.Read (This, Width, Address, 1, Result);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ if ((*Result & Mask) == Value) {\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ NumberOfTicks -= 1;\r
+ }\r
+ }\r
+ return EFI_TIMEOUT;\r
+}\r
+\r
+/**\r
+ Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r
+ satisfied or after a defined duration.\r
+\r
+ This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is\r
+ performed at the PCI I/O address specified by Address for the width specified by Width.\r
+ The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is\r
+ repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal\r
+ to Value.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Width Signifies the width of the I/O operations.\r
+ @param[in] Address The base address of the I/O operations. The caller is responsible\r
+ for aligning Address if required.\r
+ @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask\r
+ are ignored. The bits in the bytes below Width which are zero in\r
+ Mask are ignored when polling the I/O address.\r
+ @param[in] Value The comparison value used for the polling exit criteria.\r
+ @param[in] Delay The number of 100 ns units to poll. Note that timer available may\r
+ be of poorer granularity.\r
+ @param[out] Result Pointer to the last value read from the memory location.\r
+\r
+ @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid.\r
+ @retval EFI_INVALID_PARAMETER Result is NULL.\r
+ @retval EFI_TIMEOUT Delay expired before a match occurred.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoPollIo (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINT64 Mask,\r
+ IN UINT64 Value,\r
+ IN UINT64 Delay,\r
+ OUT UINT64 *Result\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINT64 NumberOfTicks;\r
+ UINT32 Remainder;\r
+\r
+ //\r
+ // No matter what, always do a single poll.\r
+ //\r
+\r
+ if (Result == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if ((UINT32)Width > EfiPciWidthUint64) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ Status = This->Io.Read (This, Width, Address, 1, Result);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ if ((*Result & Mask) == Value) {\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ if (Delay == 0) {\r
+ return EFI_SUCCESS;\r
+\r
+ } else {\r
+\r
+ //\r
+ // Determine the proper # of metronome ticks to wait for polling the\r
+ // location. The number of ticks is Roundup (Delay / mMetronome->TickPeriod)+1\r
+ // The "+1" to account for the possibility of the first tick being short\r
+ // because we started in the middle of a tick.\r
+ //\r
+ NumberOfTicks = DivU64x32Remainder (Delay, (UINT32)mMetronome->TickPeriod, &Remainder);\r
+ if (Remainder != 0) {\r
+ NumberOfTicks += 1;\r
+ }\r
+ NumberOfTicks += 1;\r
+\r
+ while (NumberOfTicks != 0) {\r
+\r
+ mMetronome->WaitForTick (mMetronome, 1);\r
+\r
+ Status = This->Io.Read (This, Width, Address, 1, Result);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ if ((*Result & Mask) == Value) {\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ NumberOfTicks -= 1;\r
+ }\r
+ }\r
+ return EFI_TIMEOUT;\r
+}\r
+\r
+/**\r
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
+\r
+ The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller\r
+ registers in the PCI root bridge memory space.\r
+ The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
+ any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Width Signifies the width of the memory operation.\r
+ @param[in] Address The base address of the memory operation. The caller is\r
+ responsible for aligning the Address if required.\r
+ @param[in] Count The number of memory operations to perform. Bytes moved is\r
+ Width size * Count, starting at Address.\r
+ @param[out] Buffer For read operations, the destination buffer to store the results. For\r
+ write operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoMemRead (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
+ )\r
+{\r
+ return RootBridgeIoMemRW (This, FALSE, Width, Address, Count, Buffer);\r
+}\r
+\r
+/**\r
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
+\r
+ The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller\r
+ registers in the PCI root bridge memory space.\r
+ The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
+ any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Width Signifies the width of the memory operation.\r
+ @param[in] Address The base address of the memory operation. The caller is\r
+ responsible for aligning the Address if required.\r
+ @param[in] Count The number of memory operations to perform. Bytes moved is\r
+ Width size * Count, starting at Address.\r
+ @param[in] Buffer For read operations, the destination buffer to store the results. For\r
+ write operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoMemWrite (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer);\r
+}\r
+\r
+/**\r
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Width Signifies the width of the memory operations.\r
+ @param[in] Address The base address of the I/O operation. The caller is responsible for\r
+ aligning the Address if required.\r
+ @param[in] Count The number of I/O operations to perform. Bytes moved is Width\r
+ size * Count, starting at Address.\r
+ @param[out] Buffer For read operations, the destination buffer to store the results. For\r
+ write operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoIoRead (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
+ )\r
+{\r
+ return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer);\r
+}\r
+\r
+/**\r
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Width Signifies the width of the memory operations.\r
+ @param[in] Address The base address of the I/O operation. The caller is responsible for\r
+ aligning the Address if required.\r
+ @param[in] Count The number of I/O operations to perform. Bytes moved is Width\r
+ size * Count, starting at Address.\r
+ @param[in] Buffer For read operations, the destination buffer to store the results. For\r
+ write operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoIoWrite (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer);\r
+}\r
+\r
+/**\r
+ Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI\r
+ root bridge memory space.\r
+\r
+ The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory\r
+ space to another region of PCI root bridge memory space. This is especially useful for video scroll\r
+ operation on a memory mapped video buffer.\r
+ The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
+ any alignment and memory width restrictions that a PCI root bridge on a platform might require.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
+ @param[in] Width Signifies the width of the memory operations.\r
+ @param[in] DestAddress The destination address of the memory operation. The caller is\r
+ responsible for aligning the DestAddress if required.\r
+ @param[in] SrcAddress The source address of the memory operation. The caller is\r
+ responsible for aligning the SrcAddress if required.\r
+ @param[in] Count The number of memory operations to perform. Bytes moved is\r
+ Width size * Count, starting at DestAddress and SrcAddress.\r
+\r
+ @retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoCopyMem (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 DestAddress,\r
+ IN UINT64 SrcAddress,\r
+ IN UINTN Count\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ BOOLEAN Direction;\r
+ UINTN Stride;\r
+ UINTN Index;\r
+ UINT64 Result;\r
+\r
+ if ((UINT32)Width > EfiPciWidthUint64) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (DestAddress == SrcAddress) {\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ Stride = (UINTN)(1 << Width);\r
+\r
+ Direction = TRUE;\r
+ if ((DestAddress > SrcAddress) && (DestAddress < (SrcAddress + Count * Stride))) {\r
+ Direction = FALSE;\r
+ SrcAddress = SrcAddress + (Count-1) * Stride;\r
+ DestAddress = DestAddress + (Count-1) * Stride;\r
+ }\r
+\r
+ for (Index = 0;Index < Count;Index++) {\r
+ Status = RootBridgeIoMemRead (\r
+ This,\r
+ Width,\r
+ SrcAddress,\r
+ 1,\r
+ &Result\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ Status = RootBridgeIoMemWrite (\r
+ This,\r
+ Width,\r
+ DestAddress,\r
+ 1,\r
+ &Result\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ if (Direction) {\r
+ SrcAddress += Stride;\r
+ DestAddress += Stride;\r
+ } else {\r
+ SrcAddress -= Stride;\r
+ DestAddress -= Stride;\r
+ }\r
+ }\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.\r
+\r
+ The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration\r
+ registers for a PCI controller.\r
+ The PCI Configuration operations are carried out exactly as requested. The caller is responsible for\r
+ any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might\r
+ require.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Width Signifies the width of the memory operations.\r
+ @param[in] Address The address within the PCI configuration space for the PCI controller.\r
+ @param[in] Count The number of PCI configuration operations to perform. Bytes\r
+ moved is Width size * Count, starting at Address.\r
+ @param[out] Buffer For read operations, the destination buffer to store the results. For\r
+ write operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoPciRead (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
+ )\r
+{\r
+ return RootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);\r
+}\r
+\r
+/**\r
+ Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.\r
+\r
+ The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration\r
+ registers for a PCI controller.\r
+ The PCI Configuration operations are carried out exactly as requested. The caller is responsible for\r
+ any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might\r
+ require.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Width Signifies the width of the memory operations.\r
+ @param[in] Address The address within the PCI configuration space for the PCI controller.\r
+ @param[in] Count The number of PCI configuration operations to perform. Bytes\r
+ moved is Width size * Count, starting at Address.\r
+ @param[in] Buffer For read operations, the destination buffer to store the results. For\r
+ write operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoPciWrite (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ return RootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);\r
+}\r
+\r
+/**\r
+ Provides the PCI controller-specific addresses required to access system memory from a\r
+ DMA bus master.\r
+\r
+ The Map() function provides the PCI controller specific addresses needed to access system\r
+ memory. This function is used to map system memory for PCI bus master DMA accesses.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Operation Indicates if the bus master is going to read or write to system memory.\r
+ @param[in] HostAddress The system memory address to map to the PCI controller.\r
+ @param[in, out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.\r
+ @param[out] DeviceAddress The resulting map address for the bus master PCI controller to use\r
+ to access the system memory's HostAddress.\r
+ @param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete.\r
+\r
+ @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
+ @retval EFI_INVALID_PARAMETER Operation is invalid.\r
+ @retval EFI_INVALID_PARAMETER HostAddress is NULL.\r
+ @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL.\r
+ @retval EFI_INVALID_PARAMETER DeviceAddress is NULL.\r
+ @retval EFI_INVALID_PARAMETER Mapping is NULL.\r
+ @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r
+ @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoMap (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,\r
+ IN VOID *HostAddress,\r
+ IN OUT UINTN *NumberOfBytes,\r
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
+ OUT VOID **Mapping\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
+ MAP_INFO *MapInfo;\r
+\r
+ if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Initialize the return values to their defaults\r
+ //\r
+ *Mapping = NULL;\r
+\r
+ //\r
+ // Make sure that Operation is valid\r
+ //\r
+ if ((UINT32)Operation >= EfiPciOperationMaximum) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Most PCAT like chipsets can not handle performing DMA above 4GB.\r
+ // If any part of the DMA transfer being mapped is above 4GB, then\r
+ // map the DMA transfer to a buffer below 4GB.\r
+ //\r
+ PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress;\r
+ if ((PhysicalAddress + *NumberOfBytes) > 0x100000000ULL) {\r
+\r
+ //\r
+ // Common Buffer operations can not be remapped. If the common buffer\r
+ // if above 4GB, then it is not possible to generate a mapping, so return\r
+ // an error.\r
+ //\r
+ if (Operation == EfiPciOperationBusMasterCommonBuffer || Operation == EfiPciOperationBusMasterCommonBuffer64) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ //\r
+ // Allocate a MAP_INFO structure to remember the mapping when Unmap() is\r
+ // called later.\r
+ //\r
+ Status = gBS->AllocatePool (\r
+ EfiBootServicesData,\r
+ sizeof(MAP_INFO),\r
+ (VOID **)&MapInfo\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ *NumberOfBytes = 0;\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // Return a pointer to the MAP_INFO structure in Mapping\r
+ //\r
+ *Mapping = MapInfo;\r
+\r
+ //\r
+ // Initialize the MAP_INFO structure\r
+ //\r
+ MapInfo->Operation = Operation;\r
+ MapInfo->NumberOfBytes = *NumberOfBytes;\r
+ MapInfo->NumberOfPages = EFI_SIZE_TO_PAGES(*NumberOfBytes);\r
+ MapInfo->HostAddress = PhysicalAddress;\r
+ MapInfo->MappedHostAddress = 0x00000000ffffffff;\r
+\r
+ //\r
+ // Allocate a buffer below 4GB to map the transfer to.\r
+ //\r
+ Status = gBS->AllocatePages (\r
+ AllocateMaxAddress,\r
+ EfiBootServicesData,\r
+ MapInfo->NumberOfPages,\r
+ &MapInfo->MappedHostAddress\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ gBS->FreePool (MapInfo);\r
+ *NumberOfBytes = 0;\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // If this is a read operation from the Bus Master's point of view,\r
+ // then copy the contents of the real buffer into the mapped buffer\r
+ // so the Bus Master can read the contents of the real buffer.\r
+ //\r
+ if (Operation == EfiPciOperationBusMasterRead || Operation == EfiPciOperationBusMasterRead64) {\r
+ CopyMem (\r
+ (VOID *)(UINTN)MapInfo->MappedHostAddress,\r
+ (VOID *)(UINTN)MapInfo->HostAddress,\r
+ MapInfo->NumberOfBytes\r
+ );\r
+ }\r
+\r
+ //\r
+ // The DeviceAddress is the address of the maped buffer below 4GB\r
+ //\r
+ *DeviceAddress = MapInfo->MappedHostAddress;\r
+ } else {\r
+ //\r
+ // The transfer is below 4GB, so the DeviceAddress is simply the HostAddress\r
+ //\r
+ *DeviceAddress = PhysicalAddress;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Completes the Map() operation and releases any corresponding resources.\r
+\r
+ The Unmap() function completes the Map() operation and releases any corresponding resources.\r
+ If the operation was an EfiPciOperationBusMasterWrite or\r
+ EfiPciOperationBusMasterWrite64, the data is committed to the target system memory.\r
+ Any resources used for the mapping are freed.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Mapping The mapping value returned from Map().\r
+\r
+ @retval EFI_SUCCESS The range was unmapped.\r
+ @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r
+ @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoUnmap (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN VOID *Mapping\r
+ )\r
+{\r
+ MAP_INFO *MapInfo;\r
+\r
+ //\r
+ // See if the Map() operation associated with this Unmap() required a mapping buffer.\r
+ // If a mapping buffer was not required, then this function simply returns EFI_SUCCESS.\r
+ //\r
+ if (Mapping != NULL) {\r
+ //\r
+ // Get the MAP_INFO structure from Mapping\r
+ //\r
+ MapInfo = (MAP_INFO *)Mapping;\r
+\r
+ //\r
+ // If this is a write operation from the Bus Master's point of view,\r
+ // then copy the contents of the mapped buffer into the real buffer\r
+ // so the processor can read the contents of the real buffer.\r
+ //\r
+ if (MapInfo->Operation == EfiPciOperationBusMasterWrite || MapInfo->Operation == EfiPciOperationBusMasterWrite64) {\r
+ CopyMem (\r
+ (VOID *)(UINTN)MapInfo->HostAddress,\r
+ (VOID *)(UINTN)MapInfo->MappedHostAddress,\r
+ MapInfo->NumberOfBytes\r
+ );\r
+ }\r
+\r
+ //\r
+ // Free the mapped buffer and the MAP_INFO structure.\r
+ //\r
+ gBS->FreePages (MapInfo->MappedHostAddress, MapInfo->NumberOfPages);\r
+ gBS->FreePool (Mapping);\r
+ }\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or\r
+ EfiPciOperationBusMasterCommonBuffer64 mapping.\r
+\r
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param Type This parameter is not used and must be ignored.\r
+ @param MemoryType The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.\r
+ @param Pages The number of pages to allocate.\r
+ @param HostAddress A pointer to store the base system memory address of the allocated range.\r
+ @param Attributes The requested bit mask of attributes for the allocated range. Only\r
+ the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED,\r
+ and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.\r
+\r
+ @retval EFI_SUCCESS The requested memory pages were allocated.\r
+ @retval EFI_INVALID_PARAMETER MemoryType is invalid.\r
+ @retval EFI_INVALID_PARAMETER HostAddress is NULL.\r
+ @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
+ MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.\r
+ @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoAllocateBuffer (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_ALLOCATE_TYPE Type,\r
+ IN EFI_MEMORY_TYPE MemoryType,\r
+ IN UINTN Pages,\r
+ OUT VOID **HostAddress,\r
+ IN UINT64 Attributes\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
+\r
+ //\r
+ // Validate Attributes\r
+ //\r
+ if ((Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) != 0) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ //\r
+ // Check for invalid inputs\r
+ //\r
+ if (HostAddress == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData\r
+ //\r
+ if (MemoryType != EfiBootServicesData && MemoryType != EfiRuntimeServicesData) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Limit allocations to memory below 4GB\r
+ //\r
+ PhysicalAddress = (EFI_PHYSICAL_ADDRESS)(0xffffffff);\r
+\r
+ Status = gBS->AllocatePages (AllocateMaxAddress, MemoryType, Pages, &PhysicalAddress);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ *HostAddress = (VOID *)(UINTN)PhysicalAddress;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Frees memory that was allocated with AllocateBuffer().\r
+\r
+ The FreeBuffer() function frees memory that was allocated with AllocateBuffer().\r
+\r
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param Pages The number of pages to free.\r
+ @param HostAddress The base system memory address of the allocated range.\r
+\r
+ @retval EFI_SUCCESS The requested memory pages were freed.\r
+ @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
+ was not allocated with AllocateBuffer().\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoFreeBuffer (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN UINTN Pages,\r
+ OUT VOID *HostAddress\r
+ )\r
+{\r
+ return gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress, Pages);\r
+}\r
+\r
+/**\r
+ Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
+\r
+ The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system\r
+ memory. Posted write transactions are generated by PCI bus masters when they perform write\r
+ transactions to target addresses in system memory.\r
+ This function does not flush posted write transactions from any PCI bridges. A PCI controller\r
+ specific action must be taken to guarantee that the posted write transactions have been flushed from\r
+ the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with\r
+ a PCI read transaction from the PCI controller prior to calling Flush().\r
+\r
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+\r
+ @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r
+ bridge to system memory.\r
+ @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r
+ host bridge due to a hardware error.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoFlush (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This\r
+ )\r
+{\r
+ //\r
+ // not supported yet\r
+ //\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the\r
+ attributes that a PCI root bridge is currently using.\r
+\r
+ The GetAttributes() function returns the mask of attributes that this PCI root bridge supports\r
+ and the mask of attributes that the PCI root bridge is currently using.\r
+\r
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param Supported A pointer to the mask of attributes that this PCI root bridge\r
+ supports setting with SetAttributes().\r
+ @param Attributes A pointer to the mask of attributes that this PCI root bridge is\r
+ currently using.\r
+\r
+ @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root\r
+ bridge supports is returned in Supports. If Attributes is\r
+ not NULL, then the attributes that the PCI root bridge is currently\r
+ using is returned in Attributes.\r
+ @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoGetAttributes (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ OUT UINT64 *Supported,\r
+ OUT UINT64 *Attributes\r
+ )\r
+{\r
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
+\r
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);\r
+\r
+ if (Attributes == NULL && Supported == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Set the return value for Supported and Attributes\r
+ //\r
+ if (Supported != NULL) {\r
+ *Supported = PrivateData->Supports;\r
+ }\r
+\r
+ if (Attributes != NULL) {\r
+ *Attributes = PrivateData->Attributes;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Sets attributes for a resource range on a PCI root bridge.\r
+\r
+ The SetAttributes() function sets the attributes specified in Attributes for the PCI root\r
+ bridge on the resource range specified by ResourceBase and ResourceLength. Since the\r
+ granularity of setting these attributes may vary from resource type to resource type, and from\r
+ platform to platform, the actual resource range and the one passed in by the caller may differ. As a\r
+ result, this function may set the attributes specified by Attributes on a larger resource range\r
+ than the caller requested. The actual range is returned in ResourceBase and\r
+ ResourceLength. The caller is responsible for verifying that the actual range for which the\r
+ attributes were set is acceptable.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[in] Attributes The mask of attributes to set. If the attribute bit\r
+ MEMORY_WRITE_COMBINE, MEMORY_CACHED, or\r
+ MEMORY_DISABLE is set, then the resource range is specified by\r
+ ResourceBase and ResourceLength. If\r
+ MEMORY_WRITE_COMBINE, MEMORY_CACHED, and\r
+ MEMORY_DISABLE are not set, then ResourceBase and\r
+ ResourceLength are ignored, and may be NULL.\r
+ @param[in, out] ResourceBase A pointer to the base address of the resource range to be modified\r
+ by the attributes specified by Attributes.\r
+ @param[in, out] ResourceLength A pointer to the length of the resource range to be modified by the\r
+ attributes specified by Attributes.\r
+\r
+ @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.\r
+ @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.\r
+ @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoSetAttributes (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN UINT64 Attributes,\r
+ IN OUT UINT64 *ResourceBase,\r
+ IN OUT UINT64 *ResourceLength\r
+ )\r
+{\r
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
+\r
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);\r
+\r
+ if (Attributes != 0) {\r
+ if ((Attributes & (~(PrivateData->Supports))) != 0) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+ }\r
+\r
+ //\r
+ // This is a generic driver for a PC-AT class system. It does not have any\r
+ // chipset specific knowlegde, so none of the attributes can be set or\r
+ // cleared. Any attempt to set attribute that are already set will succeed,\r
+ // and any attempt to set an attribute that is not supported will fail.\r
+ //\r
+ if (Attributes & (~PrivateData->Attributes)) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0\r
+ resource descriptors.\r
+\r
+ There are only two resource descriptor types from the ACPI Specification that may be used to\r
+ describe the current resources allocated to a PCI root bridge. These are the QWORD Address\r
+ Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The\r
+ QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic\r
+ or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD\r
+ Address Space Descriptors followed by an End Tag.\r
+\r
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that describe the\r
+ current configuration of this PCI root bridge. The storage for the\r
+ ACPI 2.0 resource descriptors is allocated by this function. The\r
+ caller must treat the return buffer as read-only data, and the buffer\r
+ must not be freed by the caller.\r
+\r
+ @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.\r
+ @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.\r
+ @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoConfiguration (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ OUT VOID **Resources\r
+ )\r
+{\r
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
+ UINTN Index;\r
+\r
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
+\r
+ for (Index = 0; Index < TypeMax; Index++) {\r
+ if (PrivateData->ResAllocNode[Index].Status == ResAllocated) {\r
+ Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base;\r
+ Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1;\r
+ Configuration.SpaceDesp[Index].AddrLen = PrivateData->ResAllocNode[Index].Length;\r
+ }\r
+ }\r
+\r
+ *Resources = &Configuration;\r
+ return EFI_SUCCESS;\r
+}\r
+\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include "PrePi.h"\r
+\r
+#include <Chipset/AArch64.h>\r
+\r
+VOID\r
+ArchInitialize (\r
+ VOID\r
+ )\r
+{\r
+ // Enable Floating Point\r
+ if (FixedPcdGet32 (PcdVFPEnabled)) {\r
+ ArmEnableVFP ();\r
+ }\r
+\r
+ if (ArmReadCurrentEL () == AARCH64_EL2) {\r
+ // Trap General Exceptions. All exceptions that would be routed to EL1 are routed to EL2\r
+ ArmWriteHcr (ARM_HCR_TGE);\r
+ }\r
+}\r
--- /dev/null
+//\r
+// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+// Copyright (c) 2015, Linaro Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLibV8.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <AutoGen.h>\r
+\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)\r
+GCC_ASM_IMPORT(ArmReadMpidr)\r
+GCC_ASM_IMPORT(ArmPlatformPeiBootAction)\r
+GCC_ASM_IMPORT(ArmPlatformStackSet)\r
+GCC_ASM_EXPORT(_ModuleEntryPoint)\r
+\r
+StartupAddr: .8byte ASM_PFX(CEntryPoint)\r
+\r
+ASM_PFX(_ModuleEntryPoint):\r
+ //\r
+ // We are built as a ET_DYN PIE executable, so we need to process all\r
+ // relative relocations regardless of whether or not we are executing from\r
+ // the same offset we were linked at. This is only possible if we are\r
+ // running from RAM.\r
+ //\r
+ adr x8, __reloc_base\r
+ adr x9, __reloc_start\r
+ adr x10, __reloc_end\r
+\r
+.Lreloc_loop:\r
+ cmp x9, x10\r
+ bhs .Lreloc_done\r
+\r
+ //\r
+ // AArch64 uses the ELF64 RELA format, which means each entry in the\r
+ // relocation table consists of\r
+ //\r
+ // UINT64 offset : the relative offset of the value that needs to\r
+ // be relocated\r
+ // UINT64 info : relocation type and symbol index (the latter is\r
+ // not used for R_AARCH64_RELATIVE relocations)\r
+ // UINT64 addend : value to be added to the value being relocated\r
+ //\r
+ ldp x11, x12, [x9], #24 // read offset into x11 and info into x12\r
+ cmp x12, #0x403 // check info == R_AARCH64_RELATIVE?\r
+ bne .Lreloc_loop // not a relative relocation? then skip\r
+\r
+ ldr x12, [x9, #-8] // read addend into x12\r
+ add x12, x12, x8 // add reloc base to addend to get relocated value\r
+ str x12, [x11, x8] // write relocated value at offset\r
+ b .Lreloc_loop\r
+.Lreloc_done:\r
+\r
+ // Do early platform specific actions\r
+ bl ASM_PFX(ArmPlatformPeiBootAction)\r
+\r
+ // Get ID of this CPU in Multicore system\r
+ bl ASM_PFX(ArmReadMpidr)\r
+ // Keep a copy of the MpId register value\r
+ mov x10, x0\r
+\r
+// Check if we can install the stack at the top of the System Memory or if we need\r
+// to install the stacks at the bottom of the Firmware Device (case the FD is located\r
+// at the top of the DRAM)\r
+_SetupStackPosition:\r
+ // Compute Top of System Memory\r
+ ldr x1, PcdGet64 (PcdSystemMemoryBase)\r
+ ldr x2, PcdGet64 (PcdSystemMemorySize)\r
+ sub x2, x2, #1\r
+ add x1, x1, x2 // x1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize\r
+\r
+ // Calculate Top of the Firmware Device\r
+ ldr x2, PcdGet64 (PcdFdBaseAddress)\r
+ ldr w3, PcdGet32 (PcdFdSize)\r
+ sub x3, x3, #1\r
+ add x3, x3, x2 // x3 = FdTop = PcdFdBaseAddress + PcdFdSize\r
+\r
+ // UEFI Memory Size (stacks are allocated in this region)\r
+ LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryUefiRegionSize), x4)\r
+\r
+ //\r
+ // Reserve the memory for the UEFI region (contain stacks on its top)\r
+ //\r
+\r
+ // Calculate how much space there is between the top of the Firmware and the Top of the System Memory\r
+ subs x0, x1, x3 // x0 = SystemMemoryTop - FdTop\r
+ b.mi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM\r
+ cmp x0, x4\r
+ b.ge _SetupStack\r
+\r
+ // Case the top of stacks is the FdBaseAddress\r
+ mov x1, x2\r
+\r
+_SetupStack:\r
+ // x1 contains the top of the stack (and the UEFI Memory)\r
+\r
+ // Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment\r
+ // one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the\r
+ // top of the memory space)\r
+ adds x11, x1, #1\r
+ b.cs _SetupOverflowStack\r
+\r
+_SetupAlignedStack:\r
+ mov x1, x11\r
+ b _GetBaseUefiMemory\r
+\r
+_SetupOverflowStack:\r
+ // Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE\r
+ // aligned (4KB)\r
+ LoadConstantToReg (EFI_PAGE_MASK, x11)\r
+ and x11, x11, x1\r
+ sub x1, x1, x11\r
+\r
+_GetBaseUefiMemory:\r
+ // Calculate the Base of the UEFI Memory\r
+ sub x11, x1, x4\r
+\r
+_GetStackBase:\r
+ // r1 = The top of the Mpcore Stacks\r
+ // Stack for the primary core = PrimaryCoreStack\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), x2)\r
+ sub x12, x1, x2\r
+\r
+ // Stack for the secondary core = Number of Cores - 1\r
+ LoadConstantToReg (FixedPcdGet32(PcdCoreCount), x0)\r
+ sub x0, x0, #1\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), x1)\r
+ mul x1, x1, x0\r
+ sub x12, x12, x1\r
+\r
+ // x12 = The base of the MpCore Stacks (primary stack & secondary stacks)\r
+ mov x0, x12\r
+ mov x1, x10\r
+ //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), x2)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), x3)\r
+ bl ASM_PFX(ArmPlatformStackSet)\r
+\r
+ // Is it the Primary Core ?\r
+ mov x0, x10\r
+ bl ASM_PFX(ArmPlatformIsPrimaryCore)\r
+ cmp x0, #1\r
+ bne _PrepareArguments\r
+\r
+_ReserveGlobalVariable:\r
+ LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), x0)\r
+ // InitializePrimaryStack($GlobalVariableSize, $Tmp1, $Tmp2)\r
+ InitializePrimaryStack(x0, x1, x2)\r
+\r
+_PrepareArguments:\r
+ mov x0, x10\r
+ mov x1, x11\r
+ mov x2, x12\r
+ mov x3, sp\r
+\r
+ // Move sec startup address into a data register\r
+ // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
+ ldr x4, StartupAddr\r
+\r
+ // Jump to PrePiCore C code\r
+ // x0 = MpId\r
+ // x1 = UefiMemoryBase\r
+ // x2 = StacksBase\r
+ // x3 = GlobalVariableBase\r
+ blr x4\r
+\r
+_NeverReturn:\r
+ b _NeverReturn\r
--- /dev/null
+#/** @file\r
+#\r
+# Copyright (c) 2011-2015, ARM Ltd. All rights reserved.<BR>\r
+# Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmVirtPrePiUniCoreRelocatable\r
+ FILE_GUID = f7d9fd14-9335-4389-80c5-334d6abfcced\r
+ MODULE_TYPE = SEC\r
+ VALID_ARCHITECTURES = AARCH64\r
+ VERSION_STRING = 1.0\r
+\r
+[Sources]\r
+ PrePi.c\r
+\r
+[Sources.AArch64]\r
+ AArch64/ArchPrePi.c\r
+ AArch64/ModuleEntryPoint.S\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+ ArmVirtPkg/ArmVirtPkg.dec\r
+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ DebugLib\r
+ ArmLib\r
+ IoLib\r
+ TimerLib\r
+ SerialPortLib\r
+ ExtractGuidedSectionLib\r
+ LzmaDecompressLib\r
+ PeCoffGetEntryPointLib\r
+ PrePiLib\r
+ ArmPlatformLib\r
+ ArmPlatformStackLib\r
+ MemoryAllocationLib\r
+ HobLib\r
+ PrePiHobListPointerLib\r
+ PlatformPeiLib\r
+ MemoryInitPeiLib\r
+ CacheMaintenanceLib\r
+\r
+[Ppis]\r
+ gArmMpCoreInfoPpiGuid\r
+\r
+[Guids]\r
+ gArmGlobalVariableGuid\r
+ gArmMpCoreInfoGuid\r
+\r
+[FeaturePcd]\r
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob\r
+ gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores\r
+\r
+[FixedPcd]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString\r
+\r
+ gArmTokenSpaceGuid.PcdVFPEnabled\r
+\r
+ gArmTokenSpaceGuid.PcdFdSize\r
+ gArmTokenSpaceGuid.PcdFvSize\r
+\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize\r
+\r
+ gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize\r
+\r
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize\r
+\r
+ gArmPlatformTokenSpaceGuid.PcdCoreCount\r
+\r
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize\r
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize\r
+\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode\r
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData\r
+\r
+[Pcd]\r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize\r
+ gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress\r
+ gArmTokenSpaceGuid.PcdFdBaseAddress\r
+ gArmTokenSpaceGuid.PcdFvBaseAddress\r
+\r
+[BuildOptions]\r
+ GCC:*_*_AARCH64_DLINK_FLAGS = -pie -T $(MODULE_DIR)/Scripts/PrePi-PIE.lds\r
--- /dev/null
+/** @file\r
+ LZMA Decompress Library header file\r
+\r
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __LZMA_DECOMPRESS_H___\r
+#define __LZMA_DECOMPRESS_H___\r
+\r
+/**\r
+ Examines a GUIDed section and returns the size of the decoded buffer and the\r
+ size of an scratch buffer required to actually decode the data in a GUIDed section.\r
+\r
+ Examines a GUIDed section specified by InputSection.\r
+ If GUID for InputSection does not match the GUID that this handler supports,\r
+ then RETURN_UNSUPPORTED is returned.\r
+ If the required information can not be retrieved from InputSection,\r
+ then RETURN_INVALID_PARAMETER is returned.\r
+ If the GUID of InputSection does match the GUID that this handler supports,\r
+ then the size required to hold the decoded buffer is returned in OututBufferSize,\r
+ the size of an optional scratch buffer is returned in ScratchSize, and the Attributes field\r
+ from EFI_GUID_DEFINED_SECTION header of InputSection is returned in SectionAttribute.\r
+\r
+ If InputSection is NULL, then ASSERT().\r
+ If OutputBufferSize is NULL, then ASSERT().\r
+ If ScratchBufferSize is NULL, then ASSERT().\r
+ If SectionAttribute is NULL, then ASSERT().\r
+\r
+\r
+ @param[in] InputSection A pointer to a GUIDed section of an FFS formatted file.\r
+ @param[out] OutputBufferSize A pointer to the size, in bytes, of an output buffer required\r
+ if the buffer specified by InputSection were decoded.\r
+ @param[out] ScratchBufferSize A pointer to the size, in bytes, required as scratch space\r
+ if the buffer specified by InputSection were decoded.\r
+ @param[out] SectionAttribute A pointer to the attributes of the GUIDed section. See the Attributes\r
+ field of EFI_GUID_DEFINED_SECTION in the PI Specification.\r
+\r
+ @retval RETURN_SUCCESS The information about InputSection was returned.\r
+ @retval RETURN_UNSUPPORTED The section specified by InputSection does not match the GUID this handler supports.\r
+ @retval RETURN_INVALID_PARAMETER The information can not be retrieved from the section specified by InputSection.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+LzmaGuidedSectionGetInfo (\r
+ IN CONST VOID *InputSection,\r
+ OUT UINT32 *OutputBufferSize,\r
+ OUT UINT32 *ScratchBufferSize,\r
+ OUT UINT16 *SectionAttribute\r
+ );\r
+\r
+/**\r
+ Decompress a LZAM compressed GUIDed section into a caller allocated output buffer.\r
+\r
+ Decodes the GUIDed section specified by InputSection.\r
+ If GUID for InputSection does not match the GUID that this handler supports, then RETURN_UNSUPPORTED is returned.\r
+ If the data in InputSection can not be decoded, then RETURN_INVALID_PARAMETER is returned.\r
+ If the GUID of InputSection does match the GUID that this handler supports, then InputSection\r
+ is decoded into the buffer specified by OutputBuffer and the authentication status of this\r
+ decode operation is returned in AuthenticationStatus. If the decoded buffer is identical to the\r
+ data in InputSection, then OutputBuffer is set to point at the data in InputSection. Otherwise,\r
+ the decoded data will be placed in caller allocated buffer specified by OutputBuffer.\r
+\r
+ If InputSection is NULL, then ASSERT().\r
+ If OutputBuffer is NULL, then ASSERT().\r
+ If ScratchBuffer is NULL and this decode operation requires a scratch buffer, then ASSERT().\r
+ If AuthenticationStatus is NULL, then ASSERT().\r
+\r
+\r
+ @param[in] InputSection A pointer to a GUIDed section of an FFS formatted file.\r
+ @param[out] OutputBuffer A pointer to a buffer that contains the result of a decode operation.\r
+ @param[out] ScratchBuffer A caller allocated buffer that may be required by this function\r
+ as a scratch buffer to perform the decode operation.\r
+ @param[out] AuthenticationStatus\r
+ A pointer to the authentication status of the decoded output buffer.\r
+ See the definition of authentication status in the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI\r
+ section of the PI Specification. EFI_AUTH_STATUS_PLATFORM_OVERRIDE must\r
+ never be set by this handler.\r
+\r
+ @retval RETURN_SUCCESS The buffer specified by InputSection was decoded.\r
+ @retval RETURN_UNSUPPORTED The section specified by InputSection does not match the GUID this handler supports.\r
+ @retval RETURN_INVALID_PARAMETER The section specified by InputSection can not be decoded.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+LzmaGuidedSectionExtraction (\r
+ IN CONST VOID *InputSection,\r
+ OUT VOID **OutputBuffer,\r
+ OUT VOID *ScratchBuffer, OPTIONAL\r
+ OUT UINT32 *AuthenticationStatus\r
+ );\r
+\r
+#endif // __LZMADECOMPRESS_H__\r
+\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Library/PrePiLib.h>\r
+#include <Library/PrintLib.h>\r
+#include <Library/PeCoffGetEntryPointLib.h>\r
+#include <Library/PrePiHobListPointerLib.h>\r
+#include <Library/TimerLib.h>\r
+#include <Library/PerformanceLib.h>\r
+#include <Library/CacheMaintenanceLib.h>\r
+\r
+#include <Ppi/GuidedSectionExtraction.h>\r
+#include <Ppi/ArmMpCoreInfo.h>\r
+#include <Guid/LzmaDecompress.h>\r
+#include <Guid/ArmGlobalVariableHob.h>\r
+\r
+#include "PrePi.h"\r
+#include "LzmaDecompress.h"\r
+\r
+// Not used when PrePi in run in XIP mode\r
+UINTN mGlobalVariableBase = 0;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+ExtractGuidedSectionLibConstructor (\r
+ VOID\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+LzmaDecompressLibConstructor (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+BuildGlobalVariableHob (\r
+ IN EFI_PHYSICAL_ADDRESS GlobalVariableBase,\r
+ IN UINT32 GlobalVariableSize\r
+ )\r
+{\r
+ ARM_HOB_GLOBAL_VARIABLE *Hob;\r
+\r
+ Hob = CreateHob (EFI_HOB_TYPE_GUID_EXTENSION, sizeof (ARM_HOB_GLOBAL_VARIABLE));\r
+ ASSERT(Hob != NULL);\r
+\r
+ CopyGuid (&(Hob->Header.Name), &gArmGlobalVariableGuid);\r
+ Hob->GlobalVariableBase = GlobalVariableBase;\r
+ Hob->GlobalVariableSize = GlobalVariableSize;\r
+}\r
+\r
+EFI_STATUS\r
+GetPlatformPpi (\r
+ IN EFI_GUID *PpiGuid,\r
+ OUT VOID **Ppi\r
+ )\r
+{\r
+ UINTN PpiListSize;\r
+ UINTN PpiListCount;\r
+ EFI_PEI_PPI_DESCRIPTOR *PpiList;\r
+ UINTN Index;\r
+\r
+ PpiListSize = 0;\r
+ ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);\r
+ PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);\r
+ for (Index = 0; Index < PpiListCount; Index++, PpiList++) {\r
+ if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {\r
+ *Ppi = PpiList->Ppi;\r
+ return EFI_SUCCESS;\r
+ }\r
+ }\r
+\r
+ return EFI_NOT_FOUND;\r
+}\r
+\r
+VOID\r
+PrePiMain (\r
+ IN UINTN UefiMemoryBase,\r
+ IN UINTN StacksBase,\r
+ IN UINTN GlobalVariableBase,\r
+ IN UINT64 StartTimeStamp\r
+ )\r
+{\r
+ EFI_HOB_HANDOFF_INFO_TABLE* HobList;\r
+ EFI_STATUS Status;\r
+ CHAR8 Buffer[100];\r
+ UINTN CharCount;\r
+ UINTN StacksSize;\r
+\r
+ // Initialize the architecture specific bits\r
+ ArchInitialize ();\r
+\r
+ // Declare the PI/UEFI memory region\r
+ HobList = HobConstructor (\r
+ (VOID*)UefiMemoryBase,\r
+ FixedPcdGet32 (PcdSystemMemoryUefiRegionSize),\r
+ (VOID*)UefiMemoryBase,\r
+ (VOID*)StacksBase // The top of the UEFI Memory is reserved for the stacks\r
+ );\r
+ PrePeiSetHobList (HobList);\r
+\r
+ //\r
+ // Ensure that the loaded image is invalidated in the caches, so that any\r
+ // modifications we made with the caches and MMU off (such as the applied\r
+ // relocations) don't become invisible once we turn them on.\r
+ //\r
+ InvalidateDataCacheRange((VOID *)(UINTN)PcdGet64 (PcdFdBaseAddress), PcdGet32 (PcdFdSize));\r
+\r
+ // Initialize MMU and Memory HOBs (Resource Descriptor HOBs)\r
+ Status = MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ // Initialize the Serial Port\r
+ SerialPortInitialize ();\r
+ CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware (version %s built at %a on %a)\n\r",\r
+ (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);\r
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);\r
+\r
+ // Create the Stacks HOB (reserve the memory for all stacks)\r
+ StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);\r
+ BuildStackHob (StacksBase, StacksSize);\r
+\r
+ // Declare the Global Variable HOB\r
+ BuildGlobalVariableHob (GlobalVariableBase, FixedPcdGet32 (PcdPeiGlobalVariableSize));\r
+\r
+ //TODO: Call CpuPei as a library\r
+ BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize), PcdGet8 (PcdPrePiCpuIoSize));\r
+\r
+ // Set the Boot Mode\r
+ SetBootMode (ArmPlatformGetBootMode ());\r
+\r
+ // Initialize Platform HOBs (CpuHob and FvHob)\r
+ Status = PlatformPeim ();\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ // Now, the HOB List has been initialized, we can register performance information\r
+ PERF_START (NULL, "PEI", NULL, StartTimeStamp);\r
+\r
+ // SEC phase needs to run library constructors by hand.\r
+ ExtractGuidedSectionLibConstructor ();\r
+ LzmaDecompressLibConstructor ();\r
+\r
+ // Build HOBs to pass up our version of stuff the DXE Core needs to save space\r
+ BuildPeCoffLoaderHob ();\r
+ BuildExtractSectionHob (\r
+ &gLzmaCustomDecompressGuid,\r
+ LzmaGuidedSectionGetInfo,\r
+ LzmaGuidedSectionExtraction\r
+ );\r
+\r
+ // Assume the FV that contains the SEC (our code) also contains a compressed FV.\r
+ Status = DecompressFirstFv ();\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ // Load the DXE Core and transfer control to it\r
+ Status = LoadDxeCoreFromFv (NULL, 0);\r
+ ASSERT_EFI_ERROR (Status);\r
+}\r
+\r
+VOID\r
+CEntryPoint (\r
+ IN UINTN MpId,\r
+ IN UINTN UefiMemoryBase,\r
+ IN UINTN StacksBase,\r
+ IN UINTN GlobalVariableBase\r
+ )\r
+{\r
+ UINT64 StartTimeStamp;\r
+\r
+ // Initialize the platform specific controllers\r
+ ArmPlatformInitialize (MpId);\r
+\r
+ if (PerformanceMeasurementEnabled ()) {\r
+ // Initialize the Timer Library to setup the Timer HW controller\r
+ TimerConstructor ();\r
+ // We cannot call yet the PerformanceLib because the HOB List has not been initialized\r
+ StartTimeStamp = GetPerformanceCounter ();\r
+ } else {\r
+ StartTimeStamp = 0;\r
+ }\r
+\r
+ // Data Cache enabled on Primary core when MMU is enabled.\r
+ ArmDisableDataCache ();\r
+ // Invalidate Data cache\r
+ ArmInvalidateDataCache ();\r
+ // Invalidate instruction cache\r
+ ArmInvalidateInstructionCache ();\r
+ // Enable Instruction Caches on all cores.\r
+ ArmEnableInstructionCache ();\r
+\r
+ // Define the Global Variable region\r
+ mGlobalVariableBase = GlobalVariableBase;\r
+\r
+ PrePiMain (UefiMemoryBase, StacksBase, GlobalVariableBase, StartTimeStamp);\r
+\r
+ // DXE Core should always load and never return\r
+ ASSERT (FALSE);\r
+}\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#ifndef _PREPI_H_\r
+#define _PREPI_H_\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Library/PcdLib.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/SerialPortLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
+\r
+#define SerialPrint(txt) SerialPortWrite (txt, AsciiStrLen(txt)+1);\r
+\r
+RETURN_STATUS\r
+EFIAPI\r
+TimerConstructor (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+PrePiMain (\r
+ IN UINTN UefiMemoryBase,\r
+ IN UINTN StacksBase,\r
+ IN UINTN GlobalVariableBase,\r
+ IN UINT64 StartTimeStamp\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+MemoryPeim (\r
+ IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,\r
+ IN UINT64 UefiMemorySize\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformPeim (\r
+ VOID\r
+ );\r
+\r
+// Either implemented by PrePiLib or by MemoryInitPei\r
+VOID\r
+BuildMemoryTypeInformationHob (\r
+ VOID\r
+ );\r
+\r
+EFI_STATUS\r
+GetPlatformPpi (\r
+ IN EFI_GUID *PpiGuid,\r
+ OUT VOID **Ppi\r
+ );\r
+\r
+// Initialize the Architecture specific controllers\r
+VOID\r
+ArchInitialize (\r
+ VOID\r
+ );\r
+\r
+#endif /* _PREPI_H_ */\r
--- /dev/null
+#/** @file\r
+#\r
+# Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+SECTIONS\r
+{\r
+ .text 0x0 : {\r
+ PROVIDE(__reloc_base = .);\r
+\r
+ *(.text .text*)\r
+ *(.got .got*)\r
+ *(.rodata .rodata*)\r
+ *(.data .data*)\r
+\r
+ . = ALIGN(0x20);\r
+ PROVIDE(__reloc_start = .);\r
+ *(.rela .rela*)\r
+ PROVIDE(__reloc_end = .);\r
+ }\r
+ .bss ALIGN(0x20) : { *(.bss .bss*) }\r
+\r
+ /DISCARD/ : {\r
+ *(.note.GNU-stack)\r
+ *(.gnu_debuglink)\r
+ *(.interp)\r
+ *(.dynamic)\r
+ *(.dynsym)\r
+ *(.dynstr)\r
+ *(.hash)\r
+ *(.comment)\r
+ }\r
+}\r
--- /dev/null
+/** @file\r
+* Device tree enumeration DXE driver for ARM Virtual Machines\r
+*\r
+* Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
+*\r
+* This program and the accompanying materials are\r
+* licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/VirtioMmioDeviceLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/DxeServicesLib.h>\r
+#include <Library/HobLib.h>\r
+#include <libfdt.h>\r
+#include <Library/XenIoMmioLib.h>\r
+\r
+#include <Guid/Fdt.h>\r
+#include <Guid/VirtioMmioTransport.h>\r
+#include <Guid/FdtHob.h>\r
+\r
+#pragma pack (1)\r
+typedef struct {\r
+ VENDOR_DEVICE_PATH Vendor;\r
+ UINT64 PhysBase;\r
+ EFI_DEVICE_PATH_PROTOCOL End;\r
+} VIRTIO_TRANSPORT_DEVICE_PATH;\r
+#pragma pack ()\r
+\r
+typedef enum {\r
+ PropertyTypeUnknown,\r
+ PropertyTypeGic,\r
+ PropertyTypeRtc,\r
+ PropertyTypeVirtio,\r
+ PropertyTypeUart,\r
+ PropertyTypeTimer,\r
+ PropertyTypePsci,\r
+ PropertyTypeFwCfg,\r
+ PropertyTypePciHost,\r
+ PropertyTypeGicV3,\r
+ PropertyTypeXen,\r
+} PROPERTY_TYPE;\r
+\r
+typedef struct {\r
+ PROPERTY_TYPE Type;\r
+ CHAR8 Compatible[32];\r
+} PROPERTY;\r
+\r
+STATIC CONST PROPERTY CompatibleProperties[] = {\r
+ { PropertyTypeGic, "arm,cortex-a15-gic" },\r
+ { PropertyTypeRtc, "arm,pl031" },\r
+ { PropertyTypeVirtio, "virtio,mmio" },\r
+ { PropertyTypeUart, "arm,pl011" },\r
+ { PropertyTypeTimer, "arm,armv7-timer" },\r
+ { PropertyTypeTimer, "arm,armv8-timer" },\r
+ { PropertyTypePsci, "arm,psci-0.2" },\r
+ { PropertyTypeFwCfg, "qemu,fw-cfg-mmio" },\r
+ { PropertyTypePciHost, "pci-host-ecam-generic" },\r
+ { PropertyTypeGicV3, "arm,gic-v3" },\r
+ { PropertyTypeXen, "xen,xen" },\r
+ { PropertyTypeUnknown, "" }\r
+};\r
+\r
+typedef struct {\r
+ UINT32 Type;\r
+ UINT32 Number;\r
+ UINT32 Flags;\r
+} INTERRUPT_PROPERTY;\r
+\r
+STATIC\r
+PROPERTY_TYPE\r
+GetTypeFromNode (\r
+ IN CONST CHAR8 *NodeType,\r
+ IN UINTN Size\r
+ )\r
+{\r
+ CONST CHAR8 *Compatible;\r
+ CONST PROPERTY *CompatibleProperty;\r
+\r
+ //\r
+ // A 'compatible' node may contain a sequence of NULL terminated\r
+ // compatible strings so check each one\r
+ //\r
+ for (Compatible = NodeType; Compatible < NodeType + Size && *Compatible;\r
+ Compatible += 1 + AsciiStrLen (Compatible)) {\r
+ for (CompatibleProperty = CompatibleProperties; CompatibleProperty->Compatible[0]; CompatibleProperty++) {\r
+ if (AsciiStrCmp (CompatibleProperty->Compatible, Compatible) == 0) {\r
+ return CompatibleProperty->Type;\r
+ }\r
+ }\r
+ }\r
+ return PropertyTypeUnknown;\r
+}\r
+\r
+//\r
+// We expect the "ranges" property of "pci-host-ecam-generic" to consist of\r
+// records like this.\r
+//\r
+#pragma pack (1)\r
+typedef struct {\r
+ UINT32 Type;\r
+ UINT64 ChildBase;\r
+ UINT64 CpuBase;\r
+ UINT64 Size;\r
+} DTB_PCI_HOST_RANGE_RECORD;\r
+#pragma pack ()\r
+\r
+#define DTB_PCI_HOST_RANGE_RELOCATABLE BIT31\r
+#define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30\r
+#define DTB_PCI_HOST_RANGE_ALIASED BIT29\r
+#define DTB_PCI_HOST_RANGE_MMIO32 BIT25\r
+#define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24)\r
+#define DTB_PCI_HOST_RANGE_IO BIT24\r
+#define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)\r
+\r
+/**\r
+ Process the device tree node describing the generic PCI host controller.\r
+\r
+ param[in] DeviceTreeBase Pointer to the device tree.\r
+\r
+ param[in] Node Offset of the device tree node whose "compatible"\r
+ property is "pci-host-ecam-generic".\r
+\r
+ param[in] RegProp Pointer to the "reg" property of Node. The caller\r
+ is responsible for ensuring that the size of the\r
+ property is 4 UINT32 cells.\r
+\r
+ @retval EFI_SUCCESS Parsing successful, properties parsed from Node\r
+ have been stored in dynamic PCDs.\r
+\r
+ @retval EFI_PROTOCOL_ERROR Parsing failed. PCDs are left unchanged.\r
+**/\r
+STATIC\r
+EFI_STATUS\r
+EFIAPI\r
+ProcessPciHost (\r
+ IN CONST VOID *DeviceTreeBase,\r
+ IN INT32 Node,\r
+ IN CONST VOID *RegProp\r
+ )\r
+{\r
+ UINT64 ConfigBase, ConfigSize;\r
+ CONST VOID *Prop;\r
+ INT32 Len;\r
+ UINT32 BusMin, BusMax;\r
+ UINT32 RecordIdx;\r
+ UINT64 IoBase, IoSize, IoTranslation;\r
+ UINT64 MmioBase, MmioSize, MmioTranslation;\r
+\r
+ //\r
+ // Fetch the ECAM window.\r
+ //\r
+ ConfigBase = fdt64_to_cpu (((CONST UINT64 *)RegProp)[0]);\r
+ ConfigSize = fdt64_to_cpu (((CONST UINT64 *)RegProp)[1]);\r
+\r
+ //\r
+ // Fetch the bus range (note: inclusive).\r
+ //\r
+ Prop = fdt_getprop (DeviceTreeBase, Node, "bus-range", &Len);\r
+ if (Prop == NULL || Len != 2 * sizeof(UINT32)) {\r
+ DEBUG ((EFI_D_ERROR, "%a: 'bus-range' not found or invalid\n",\r
+ __FUNCTION__));\r
+ return EFI_PROTOCOL_ERROR;\r
+ }\r
+ BusMin = fdt32_to_cpu (((CONST UINT32 *)Prop)[0]);\r
+ BusMax = fdt32_to_cpu (((CONST UINT32 *)Prop)[1]);\r
+\r
+ //\r
+ // Sanity check: the config space must accommodate all 4K register bytes of\r
+ // all 8 functions of all 32 devices of all buses.\r
+ //\r
+ if (BusMax < BusMin || BusMax - BusMin == MAX_UINT32 ||\r
+ DivU64x32 (ConfigSize, SIZE_4KB * 8 * 32) < BusMax - BusMin + 1) {\r
+ DEBUG ((EFI_D_ERROR, "%a: invalid 'bus-range' and/or 'reg'\n",\r
+ __FUNCTION__));\r
+ return EFI_PROTOCOL_ERROR;\r
+ }\r
+\r
+ //\r
+ // Iterate over "ranges".\r
+ //\r
+ Prop = fdt_getprop (DeviceTreeBase, Node, "ranges", &Len);\r
+ if (Prop == NULL || Len == 0 ||\r
+ Len % sizeof (DTB_PCI_HOST_RANGE_RECORD) != 0) {\r
+ DEBUG ((EFI_D_ERROR, "%a: 'ranges' not found or invalid\n", __FUNCTION__));\r
+ return EFI_PROTOCOL_ERROR;\r
+ }\r
+\r
+ //\r
+ // IoBase, IoTranslation, MmioBase and MmioTranslation are initialized only\r
+ // in order to suppress '-Werror=maybe-uninitialized' warnings *incorrectly*\r
+ // emitted by some gcc versions.\r
+ //\r
+ IoBase = 0;\r
+ IoTranslation = 0;\r
+ MmioBase = 0;\r
+ MmioTranslation = 0;\r
+\r
+ //\r
+ // IoSize and MmioSize are initialized to zero because the logic below\r
+ // requires it.\r
+ //\r
+ IoSize = 0;\r
+ MmioSize = 0;\r
+ for (RecordIdx = 0; RecordIdx < Len / sizeof (DTB_PCI_HOST_RANGE_RECORD);\r
+ ++RecordIdx) {\r
+ CONST DTB_PCI_HOST_RANGE_RECORD *Record;\r
+\r
+ Record = (CONST DTB_PCI_HOST_RANGE_RECORD *)Prop + RecordIdx;\r
+ switch (fdt32_to_cpu (Record->Type) & DTB_PCI_HOST_RANGE_TYPEMASK) {\r
+ case DTB_PCI_HOST_RANGE_IO:\r
+ IoBase = fdt64_to_cpu (Record->ChildBase);\r
+ IoSize = fdt64_to_cpu (Record->Size);\r
+ IoTranslation = fdt64_to_cpu (Record->CpuBase) - IoBase;\r
+ break;\r
+\r
+ case DTB_PCI_HOST_RANGE_MMIO32:\r
+ MmioBase = fdt64_to_cpu (Record->ChildBase);\r
+ MmioSize = fdt64_to_cpu (Record->Size);\r
+ MmioTranslation = fdt64_to_cpu (Record->CpuBase) - MmioBase;\r
+\r
+ if (MmioBase > MAX_UINT32 || MmioSize > MAX_UINT32 ||\r
+ MmioBase + MmioSize > SIZE_4GB) {\r
+ DEBUG ((EFI_D_ERROR, "%a: MMIO32 space invalid\n", __FUNCTION__));\r
+ return EFI_PROTOCOL_ERROR;\r
+ }\r
+\r
+ if (MmioTranslation != 0) {\r
+ DEBUG ((EFI_D_ERROR, "%a: unsupported nonzero MMIO32 translation "\r
+ "0x%Lx\n", __FUNCTION__, MmioTranslation));\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ break;\r
+ }\r
+ }\r
+ if (IoSize == 0 || MmioSize == 0) {\r
+ DEBUG ((EFI_D_ERROR, "%a: %a space empty\n", __FUNCTION__,\r
+ (IoSize == 0) ? "IO" : "MMIO32"));\r
+ return EFI_PROTOCOL_ERROR;\r
+ }\r
+\r
+ PcdSet64 (PcdPciExpressBaseAddress, ConfigBase);\r
+\r
+ PcdSet32 (PcdPciBusMin, BusMin);\r
+ PcdSet32 (PcdPciBusMax, BusMax);\r
+\r
+ PcdSet64 (PcdPciIoBase, IoBase);\r
+ PcdSet64 (PcdPciIoSize, IoSize);\r
+ PcdSet64 (PcdPciIoTranslation, IoTranslation);\r
+\r
+ PcdSet32 (PcdPciMmio32Base, (UINT32)MmioBase);\r
+ PcdSet32 (PcdPciMmio32Size, (UINT32)MmioSize);\r
+\r
+ PcdSetBool (PcdPciDisableBusEnumeration, FALSE);\r
+\r
+ DEBUG ((EFI_D_INFO, "%a: Config[0x%Lx+0x%Lx) Bus[0x%x..0x%x] "\r
+ "Io[0x%Lx+0x%Lx)@0x%Lx Mem[0x%Lx+0x%Lx)@0x%Lx\n", __FUNCTION__, ConfigBase,\r
+ ConfigSize, BusMin, BusMax, IoBase, IoSize, IoTranslation, MmioBase,\r
+ MmioSize, MmioTranslation));\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+InitializeVirtFdtDxe (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ VOID *Hob;\r
+ VOID *DeviceTreeBase;\r
+ INT32 Node, Prev;\r
+ INT32 RtcNode;\r
+ EFI_STATUS Status;\r
+ CONST CHAR8 *Type;\r
+ INT32 Len;\r
+ PROPERTY_TYPE PropType;\r
+ CONST VOID *RegProp;\r
+ VIRTIO_TRANSPORT_DEVICE_PATH *DevicePath;\r
+ EFI_HANDLE Handle;\r
+ UINT64 RegBase;\r
+ UINT64 DistBase, CpuBase, RedistBase;\r
+ CONST INTERRUPT_PROPERTY *InterruptProp;\r
+ INT32 SecIntrNum, IntrNum, VirtIntrNum, HypIntrNum;\r
+ CONST CHAR8 *PsciMethod;\r
+ UINT64 FwCfgSelectorAddress;\r
+ UINT64 FwCfgSelectorSize;\r
+ UINT64 FwCfgDataAddress;\r
+ UINT64 FwCfgDataSize;\r
+\r
+ Hob = GetFirstGuidHob(&gFdtHobGuid);\r
+ if (Hob == NULL || GET_GUID_HOB_DATA_SIZE (Hob) != sizeof (UINT64)) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+ DeviceTreeBase = (VOID *)(UINTN)*(UINT64 *)GET_GUID_HOB_DATA (Hob);\r
+\r
+ if (fdt_check_header (DeviceTreeBase) != 0) {\r
+ DEBUG ((EFI_D_ERROR, "%a: No DTB found @ 0x%p\n", __FUNCTION__, DeviceTreeBase));\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ Status = gBS->InstallConfigurationTable (&gFdtTableGuid, DeviceTreeBase);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ DEBUG ((EFI_D_INFO, "%a: DTB @ 0x%p\n", __FUNCTION__, DeviceTreeBase));\r
+\r
+ RtcNode = -1;\r
+ //\r
+ // Now enumerate the nodes and install peripherals that we are interested in,\r
+ // i.e., GIC, RTC and virtio MMIO nodes\r
+ //\r
+ for (Prev = 0;; Prev = Node) {\r
+ Node = fdt_next_node (DeviceTreeBase, Prev, NULL);\r
+ if (Node < 0) {\r
+ break;\r
+ }\r
+\r
+ Type = fdt_getprop (DeviceTreeBase, Node, "compatible", &Len);\r
+ if (Type == NULL) {\r
+ continue;\r
+ }\r
+\r
+ PropType = GetTypeFromNode (Type, Len);\r
+ if (PropType == PropertyTypeUnknown) {\r
+ continue;\r
+ }\r
+\r
+ //\r
+ // Get the 'reg' property of this node. For now, we will assume\r
+ // 8 byte quantities for base and size, respectively.\r
+ // TODO use #cells root properties instead\r
+ //\r
+ RegProp = fdt_getprop (DeviceTreeBase, Node, "reg", &Len);\r
+ ASSERT ((RegProp != NULL) || (PropType == PropertyTypeTimer) ||\r
+ (PropType == PropertyTypePsci));\r
+\r
+ switch (PropType) {\r
+ case PropertyTypePciHost:\r
+ ASSERT (Len == 2 * sizeof (UINT64));\r
+ Status = ProcessPciHost (DeviceTreeBase, Node, RegProp);\r
+ ASSERT_EFI_ERROR (Status);\r
+ break;\r
+\r
+ case PropertyTypeFwCfg:\r
+ ASSERT (Len == 2 * sizeof (UINT64));\r
+\r
+ FwCfgDataAddress = fdt64_to_cpu (((UINT64 *)RegProp)[0]);\r
+ FwCfgDataSize = 8;\r
+ FwCfgSelectorAddress = FwCfgDataAddress + FwCfgDataSize;\r
+ FwCfgSelectorSize = 2;\r
+\r
+ //\r
+ // The following ASSERT()s express\r
+ //\r
+ // Address + Size - 1 <= MAX_UINTN\r
+ //\r
+ // for both registers, that is, that the last byte in each MMIO range is\r
+ // expressible as a MAX_UINTN. The form below is mathematically\r
+ // equivalent, and it also prevents any unsigned overflow before the\r
+ // comparison.\r
+ //\r
+ ASSERT (FwCfgSelectorAddress <= MAX_UINTN - FwCfgSelectorSize + 1);\r
+ ASSERT (FwCfgDataAddress <= MAX_UINTN - FwCfgDataSize + 1);\r
+\r
+ PcdSet64 (PcdFwCfgSelectorAddress, FwCfgSelectorAddress);\r
+ PcdSet64 (PcdFwCfgDataAddress, FwCfgDataAddress);\r
+\r
+ DEBUG ((EFI_D_INFO, "Found FwCfg @ 0x%Lx/0x%Lx\n", FwCfgSelectorAddress,\r
+ FwCfgDataAddress));\r
+ break;\r
+\r
+ case PropertyTypeVirtio:\r
+ ASSERT (Len == 16);\r
+ //\r
+ // Create a unique device path for this transport on the fly\r
+ //\r
+ RegBase = fdt64_to_cpu (((UINT64 *)RegProp)[0]);\r
+ DevicePath = (VIRTIO_TRANSPORT_DEVICE_PATH *)CreateDeviceNode (\r
+ HARDWARE_DEVICE_PATH,\r
+ HW_VENDOR_DP,\r
+ sizeof (VIRTIO_TRANSPORT_DEVICE_PATH));\r
+ if (DevicePath == NULL) {\r
+ DEBUG ((EFI_D_ERROR, "%a: Out of memory\n", __FUNCTION__));\r
+ break;\r
+ }\r
+\r
+ CopyMem (&DevicePath->Vendor.Guid, &gVirtioMmioTransportGuid,\r
+ sizeof (EFI_GUID));\r
+ DevicePath->PhysBase = RegBase;\r
+ SetDevicePathNodeLength (&DevicePath->Vendor,\r
+ sizeof (*DevicePath) - sizeof (DevicePath->End));\r
+ SetDevicePathEndNode (&DevicePath->End);\r
+\r
+ Handle = NULL;\r
+ Status = gBS->InstallProtocolInterface (&Handle,\r
+ &gEfiDevicePathProtocolGuid, EFI_NATIVE_INTERFACE,\r
+ DevicePath);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_ERROR, "%a: Failed to install the EFI_DEVICE_PATH "\r
+ "protocol on a new handle (Status == %r)\n",\r
+ __FUNCTION__, Status));\r
+ FreePool (DevicePath);\r
+ break;\r
+ }\r
+\r
+ Status = VirtioMmioInstallDevice (RegBase, Handle);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_ERROR, "%a: Failed to install VirtIO transport @ 0x%Lx "\r
+ "on handle %p (Status == %r)\n", __FUNCTION__, RegBase,\r
+ Handle, Status));\r
+\r
+ Status = gBS->UninstallProtocolInterface (Handle,\r
+ &gEfiDevicePathProtocolGuid, DevicePath);\r
+ ASSERT_EFI_ERROR (Status);\r
+ FreePool (DevicePath);\r
+ }\r
+ break;\r
+\r
+ case PropertyTypeGic:\r
+ ASSERT (Len == 32);\r
+\r
+ DistBase = fdt64_to_cpu (((UINT64 *)RegProp)[0]);\r
+ CpuBase = fdt64_to_cpu (((UINT64 *)RegProp)[2]);\r
+ ASSERT (DistBase < MAX_UINT32);\r
+ ASSERT (CpuBase < MAX_UINT32);\r
+\r
+ PcdSet32 (PcdGicDistributorBase, (UINT32)DistBase);\r
+ PcdSet32 (PcdGicInterruptInterfaceBase, (UINT32)CpuBase);\r
+\r
+ DEBUG ((EFI_D_INFO, "Found GIC @ 0x%Lx/0x%Lx\n", DistBase, CpuBase));\r
+ break;\r
+\r
+ case PropertyTypeGicV3:\r
+ //\r
+ // The GIC v3 DT binding describes a series of at least 3 physical (base\r
+ // addresses, size) pairs: the distributor interface (GICD), at least one\r
+ // redistributor region (GICR) containing dedicated redistributor\r
+ // interfaces for all individual CPUs, and the CPU interface (GICC).\r
+ // Under virtualization, we assume that the first redistributor region\r
+ // listed covers the boot CPU. Also, our GICv3 driver only supports the\r
+ // system register CPU interface, so we can safely ignore the MMIO version\r
+ // which is listed after the sequence of redistributor interfaces.\r
+ // This means we are only interested in the first two memory regions\r
+ // supplied, and ignore everything else.\r
+ //\r
+ ASSERT (Len >= 32);\r
+\r
+ // RegProp[0..1] == { GICD base, GICD size }\r
+ DistBase = fdt64_to_cpu (((UINT64 *)RegProp)[0]);\r
+ ASSERT (DistBase < MAX_UINT32);\r
+\r
+ // RegProp[2..3] == { GICR base, GICR size }\r
+ RedistBase = fdt64_to_cpu (((UINT64 *)RegProp)[2]);\r
+ ASSERT (RedistBase < MAX_UINT32);\r
+\r
+ PcdSet32 (PcdGicDistributorBase, (UINT32)DistBase);\r
+ PcdSet32 (PcdGicRedistributorsBase, (UINT32)RedistBase);\r
+\r
+ DEBUG ((EFI_D_INFO, "Found GIC v3 (re)distributor @ 0x%Lx (0x%Lx)\n",\r
+ DistBase, RedistBase));\r
+ break;\r
+\r
+ case PropertyTypeRtc:\r
+ ASSERT (Len == 16);\r
+\r
+ RegBase = fdt64_to_cpu (((UINT64 *)RegProp)[0]);\r
+ ASSERT (RegBase < MAX_UINT32);\r
+\r
+ PcdSet32 (PcdPL031RtcBase, (UINT32)RegBase);\r
+\r
+ DEBUG ((EFI_D_INFO, "Found PL031 RTC @ 0x%Lx\n", RegBase));\r
+ RtcNode = Node;\r
+ break;\r
+\r
+ case PropertyTypeTimer:\r
+ //\r
+ // - interrupts : Interrupt list for secure, non-secure, virtual and\r
+ // hypervisor timers, in that order.\r
+ //\r
+ InterruptProp = fdt_getprop (DeviceTreeBase, Node, "interrupts", &Len);\r
+ ASSERT (Len == 36 || Len == 48);\r
+\r
+ SecIntrNum = fdt32_to_cpu (InterruptProp[0].Number)\r
+ + (InterruptProp[0].Type ? 16 : 0);\r
+ IntrNum = fdt32_to_cpu (InterruptProp[1].Number)\r
+ + (InterruptProp[1].Type ? 16 : 0);\r
+ VirtIntrNum = fdt32_to_cpu (InterruptProp[2].Number)\r
+ + (InterruptProp[2].Type ? 16 : 0);\r
+ HypIntrNum = Len < 48 ? 0 : fdt32_to_cpu (InterruptProp[3].Number)\r
+ + (InterruptProp[3].Type ? 16 : 0);\r
+\r
+ DEBUG ((EFI_D_INFO, "Found Timer interrupts %d, %d, %d, %d\n",\r
+ SecIntrNum, IntrNum, VirtIntrNum, HypIntrNum));\r
+\r
+ PcdSet32 (PcdArmArchTimerSecIntrNum, SecIntrNum);\r
+ PcdSet32 (PcdArmArchTimerIntrNum, IntrNum);\r
+ PcdSet32 (PcdArmArchTimerVirtIntrNum, VirtIntrNum);\r
+ PcdSet32 (PcdArmArchTimerHypIntrNum, HypIntrNum);\r
+ break;\r
+\r
+ case PropertyTypePsci:\r
+ PsciMethod = fdt_getprop (DeviceTreeBase, Node, "method", &Len);\r
+\r
+ if (PsciMethod && AsciiStrnCmp (PsciMethod, "hvc", 3) == 0) {\r
+ PcdSet32 (PcdArmPsciMethod, 1);\r
+ } else if (PsciMethod && AsciiStrnCmp (PsciMethod, "smc", 3) == 0) {\r
+ PcdSet32 (PcdArmPsciMethod, 2);\r
+ } else {\r
+ DEBUG ((EFI_D_ERROR, "%a: Unknown PSCI method \"%a\"\n", __FUNCTION__,\r
+ PsciMethod));\r
+ }\r
+ break;\r
+\r
+ case PropertyTypeXen:\r
+ ASSERT (Len == 16);\r
+\r
+ //\r
+ // Retrieve the reg base from this node and wire it up to the\r
+ // MMIO flavor of the XenBus root device I/O protocol\r
+ //\r
+ RegBase = fdt64_to_cpu (((UINT64 *)RegProp)[0]);\r
+ Handle = NULL;\r
+ Status = XenIoMmioInstall (&Handle, RegBase);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_ERROR, "%a: XenIoMmioInstall () failed on a new handle "\r
+ "(Status == %r)\n", __FUNCTION__, Status));\r
+ break;\r
+ }\r
+\r
+ DEBUG ((EFI_D_INFO, "Found Xen node with Grant table @ 0x%Lx\n", RegBase));\r
+\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+\r
+ //\r
+ // UEFI takes ownership of the RTC hardware, and exposes its functionality\r
+ // through the UEFI Runtime Services GetTime, SetTime, etc. This means we\r
+ // need to disable it in the device tree to prevent the OS from attaching its\r
+ // device driver as well.\r
+ //\r
+ if ((RtcNode != -1) &&\r
+ fdt_setprop_string (DeviceTreeBase, RtcNode, "status",\r
+ "disabled") != 0) {\r
+ DEBUG ((EFI_D_WARN, "Failed to set PL031 status to 'disabled'\n"));\r
+ }\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+## @file\r
+# Device tree enumeration DXE driver for ARM Virtual Machines\r
+#\r
+# Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials are\r
+# licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = VirtFdtDxe\r
+ FILE_GUID = 9AD7DCB4-E6EC-472E-96BF-81C219A3F77E\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+\r
+ ENTRY_POINT = InitializeVirtFdtDxe\r
+\r
+[Sources]\r
+ VirtFdtDxe.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+ ArmVirtPkg/ArmVirtPkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ OvmfPkg/OvmfPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ PcdLib\r
+ UefiDriverEntryPoint\r
+ DxeServicesLib\r
+ FdtLib\r
+ VirtioMmioDeviceLib\r
+ HobLib\r
+ XenIoMmioLib\r
+\r
+[Guids]\r
+ gFdtTableGuid\r
+ gVirtioMmioTransportGuid\r
+ gFdtHobGuid\r
+\r
+[Pcd]\r
+ gArmVirtTokenSpaceGuid.PcdArmPsciMethod\r
+ gArmVirtTokenSpaceGuid.PcdFwCfgSelectorAddress\r
+ gArmVirtTokenSpaceGuid.PcdFwCfgDataAddress\r
+ gArmTokenSpaceGuid.PcdGicDistributorBase\r
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum\r
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum\r
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum\r
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum\r
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcBase\r
+ gArmPlatformTokenSpaceGuid.PcdPciBusMin\r
+ gArmPlatformTokenSpaceGuid.PcdPciBusMax\r
+ gArmPlatformTokenSpaceGuid.PcdPciIoBase\r
+ gArmPlatformTokenSpaceGuid.PcdPciIoSize\r
+ gArmPlatformTokenSpaceGuid.PcdPciIoTranslation\r
+ gArmPlatformTokenSpaceGuid.PcdPciMmio32Base\r
+ gArmPlatformTokenSpaceGuid.PcdPciMmio32Size\r
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration\r
+\r
+[Protocols]\r
+ gEfiDevicePathProtocolGuid\r
+\r
+[Depex]\r
+ TRUE\r
projects / mirror_edk2.git / commitdiff