Add code to identify D0 stepping ValleyView SoC.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Shifei Lu <shifeix.a.lu@intel.com>
Reviewed-by: David Wei <david.wei@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17034 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcu.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcu.h
index 29629890c0117bd024f9c6f54c804a36e5c50ff8..bf3c3c86c3dbe6ec018494fecc7b81dbbabb5644 100644 (file)
--- a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcu.h
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcu.h
@@ -119,6 +119,8 @@ typedef enum {
 #define V_PCH_LPC_RID_B                           0x0C  // B3 Stepping (25 x 27)\r
 #define V_PCH_LPC_RID_C                           0x0D  // C0 Stepping (17 x 17)\r
 #define V_PCH_LPC_RID_D                           0x0E  // C0 Stepping (25 x 27)\r
+#define V_PCH_LPC_RID_E                           0x10  // D0 Stepping (17 x 17)\r
+#define V_PCH_LPC_RID_F                           0x11  // D0 Stepping (25 x 27)\r
 \r
 #define R_PCH_LPC_MLT                             0x0D  // Master Latency Timer\r
 #define B_PCH_LPC_MLT_MLC                         0xF8  // Master Latency Count\r

diff --git a/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.c b/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.c
index c92308f4e9a2d4770447269ded0e9cc9c979441d..a509b07c69aab34bb2218fd945d057abd357cbf1 100644 (file)
--- a/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.c
+++ b/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.c
@@ -83,7 +83,12 @@ PchStepping (
     case V_PCH_LPC_RID_D:\r
       return PchC0;\r
       break;\r
-\r
+    \r
+    case V_PCH_LPC_RID_E:\r
+    case V_PCH_LPC_RID_F:\r
+      return PchD0;\r
+      break;\r
+        \r
     default:\r
       return PchSteppingMax;\r
       break;\r