Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-1.\r
\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
+ December 2015, Appendix A VMX Capability Reporting Facility, Section A.1.\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
+ December 2015, Appendix A VMX Capability Reporting Facility, Section A.6.\r
+\r
**/\r
\r
#ifndef __ARCHITECTURAL_MSR_H__\r
\r
\r
/**\r
- SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1. CPUID.01H: ECX[6] =\r
+ SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =\r
1.\r
\r
@param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B)\r
UINT64 Uint64;\r
} MSR_IA32_SMM_MONITOR_CTL_REGISTER;\r
\r
+/**\r
+ MSEG header that is located at the physical address specified by the MsegBase\r
+ field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r
+**/\r
+typedef struct {\r
+ UINT32 MsegHeaderRevision;\r
+ UINT32 MonitorFeatures;\r
+ UINT32 GdtrLimit;\r
+ UINT32 GdtrBaseOffset;\r
+ UINT32 CsSelector;\r
+ UINT32 EipOffset;\r
+ UINT32 EspOffset;\r
+ UINT32 Cr3Offset;\r
+ //\r
+ // Pad header so total size is 2KB\r
+ //\r
+ UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];\r
+} MSEG_HEADER;\r
+\r
\r
/**\r
Base address of the logical processor's SMRAM image (RO, SMM only). If\r
\r
<b>Example usage</b>\r
@code\r
- UINT64 Msr;\r
+ MSR_IA32_VMX_BASIC_REGISTER Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_IA32_VMX_BASIC);\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC);\r
@endcode\r
@note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.\r
**/\r
#define MSR_IA32_VMX_BASIC 0x00000480\r
\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_VMX_BASIC\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 30:0] VMCS revision identifier used by the processor. Processors\r
+ /// that use the same VMCS revision identifier use the same size for VMCS\r
+ /// regions (see subsequent item on bits 44:32).\r
+ ///\r
+ /// @note Earlier versions of this manual specified that the VMCS revision\r
+ /// identifier was a 32-bit field in bits 31:0 of this MSR. For all\r
+ /// processors produced prior to this change, bit 31 of this MSR was read\r
+ /// as 0.\r
+ ///\r
+ UINT32 VmcsRevisonId:31;\r
+ UINT32 MustBeZero:1;\r
+ ///\r
+ /// [Bit 44:32] Reports the number of bytes that software should allocate\r
+ /// for the VMXON region and any VMCS region. It is a value greater than\r
+ /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).\r
+ ///\r
+ UINT32 VmcsSize:13;\r
+ UINT32 Reserved1:3;\r
+ ///\r
+ /// [Bit 48] Indicates the width of the physical addresses that may be used\r
+ /// for the VMXON region, each VMCS, and data structures referenced by\r
+ /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX\r
+ /// transitions). If the bit is 0, these addresses are limited to the\r
+ /// processor's physical-address width. If the bit is 1, these addresses\r
+ /// are limited to 32 bits. This bit is always 0 for processors that\r
+ /// support Intel 64 architecture.\r
+ ///\r
+ /// @note On processors that support Intel 64 architecture, the pointer\r
+ /// must not set bits beyond the processor's physical address width.\r
+ ///\r
+ UINT32 VmcsAddressWidth:1;\r
+ ///\r
+ /// [Bit 49] If bit 49 is read as 1, the logical processor supports the\r
+ /// dual-monitor treatment of system-management interrupts and\r
+ /// system-management mode. See Section 34.15 for details of this treatment.\r
+ ///\r
+ UINT32 DualMonitor:1;\r
+ ///\r
+ /// [Bit 53:50] report the memory type that should be used for the VMCS,\r
+ /// for data structures referenced by pointers in the VMCS (I/O bitmaps,\r
+ /// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG\r
+ /// header. If software needs to access these data structures (e.g., to\r
+ /// modify the contents of the MSR bitmaps), it can configure the paging\r
+ /// structures to map them into the linear-address space. If it does so,\r
+ /// it should establish mappings that use the memory type reported bits\r
+ /// 53:50 in this MSR.\r
+ ///\r
+ /// As of this writing, all processors that support VMX operation indicate\r
+ /// the write-back type.\r
+ ///\r
+ /// If software needs to access these data structures (e.g., to modify\r
+ /// the contents of the MSR bitmaps), it can configure the paging\r
+ /// structures to map them into the linear-address space. If it does so,\r
+ /// it should establish mappings that use the memory type reported in this\r
+ /// MSR.\r
+ ///\r
+ /// @note Alternatively, software may map any of these regions or\r
+ /// structures with the UC memory type. (This may be necessary for the MSEG\r
+ /// header.) Doing so is discouraged unless necessary as it will cause the\r
+ /// performance of software accesses to those structures to suffer.\r
+ ///\r
+ ///\r
+ UINT32 MemoryType:4;\r
+ ///\r
+ /// [Bit 54] If bit 54 is read as 1, the logical processor reports\r
+ /// information in the VM-exit instruction-information field on VM exits\r
+ /// due to execution of the INS and OUTS instructions. This reporting is\r
+ /// done only if this bit is read as 1.\r
+ ///\r
+ UINT32 InsOutsReporting:1;\r
+ ///\r
+ /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may\r
+ /// be cleared to 0. See Appendix A.2 for details. It also reports support\r
+ /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS,\r
+ /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and\r
+ /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2,\r
+ /// Appendix A.4, and Appendix A.5 for details.\r
+ ///\r
+ UINT32 VmxControls:1;\r
+ UINT32 Reserved2:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_VMX_BASIC_REGISTER;\r
+\r
+///\r
+/// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType\r
+///\r
+#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00\r
+#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06\r
+///\r
+/// @}\r
+///\r
+\r
\r
/**\r
Capability Reporting Register of Pinbased VM-execution Controls (R/O) See\r
\r
<b>Example usage</b>\r
@code\r
- UINT64 Msr;\r
+ IA32_VMX_MISC_REGISTER Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_IA32_VMX_MISC);\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC);\r
@endcode\r
@note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.\r
**/\r
#define MSR_IA32_VMX_MISC 0x00000485\r
\r
+/**\r
+ MSR information returned for MSR index #IA32_VMX_MISC\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 4:0] Reports a value X that specifies the relationship between the\r
+ /// rate of the VMX-preemption timer and that of the timestamp counter (TSC).\r
+ /// Specifically, the VMX-preemption timer (if it is active) counts down by\r
+ /// 1 every time bit X in the TSC changes due to a TSC increment.\r
+ ///\r
+ UINT32 VmxTimerRatio:5;\r
+ ///\r
+ /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA\r
+ /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more\r
+ /// details. This bit is read as 1 on any logical processor that supports\r
+ /// the 1-setting of the "unrestricted guest" VM-execution control.\r
+ ///\r
+ UINT32 VmExitEferLma:1;\r
+ ///\r
+ /// [Bit 6] reports (if set) the support for activity state 1 (HLT).\r
+ ///\r
+ UINT32 HltActivityStateSupported:1;\r
+ ///\r
+ /// [Bit 7] reports (if set) the support for activity state 2 (shutdown).\r
+ ///\r
+ UINT32 ShutdownActivityStateSupported:1;\r
+ ///\r
+ /// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).\r
+ ///\r
+ UINT32 WaitForSipiActivityStateSupported:1;\r
+ UINT32 Reserved1:6;\r
+ ///\r
+ /// [Bit 15] If read as 1, the RDMSR instruction can be used in system-\r
+ /// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).\r
+ /// See Section 34.15.6.4.\r
+ ///\r
+ UINT32 SmBaseMsrSupported:1;\r
+ ///\r
+ /// [Bits 24:16] Indicate the number of CR3-target values supported by the\r
+ /// processor. This number is a value between 0 and 256, inclusive (bit 24\r
+ /// is set if and only if bits 23:16 are clear).\r
+ ///\r
+ UINT32 NumberOfCr3TargetValues:9;\r
+ ///\r
+ /// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum\r
+ /// number of MSRs that should appear in the VM-exit MSR-store list, the\r
+ /// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if\r
+ /// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the\r
+ /// recommended maximum number of MSRs to be included in each list. If the\r
+ /// limit is exceeded, undefined processor behavior may result (including a\r
+ /// machine check during the VMX transition).\r
+ ///\r
+ UINT32 MsrStoreListMaximum:3;\r
+ ///\r
+ /// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set\r
+ /// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1\r
+ /// (see Section 34.14.4).\r
+ ///\r
+ UINT32 BlockSmiSupported:1;\r
+ ///\r
+ /// [Bit 29] read as 1, software can use VMWRITE to write to any supported\r
+ /// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit\r
+ /// information fields.\r
+ ///\r
+ UINT32 VmWriteSupported:1;\r
+ UINT32 Reserved2:2;\r
+ ///\r
+ /// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the\r
+ /// processor.\r
+ ///\r
+ UINT32 MsegRevisionIdentifier:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} IA32_VMX_MISC_REGISTER;\r
+\r
\r
/**\r
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,\r
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