UefiCpuPkg/MpLib.c: Add checking CR0 PG bit

If CR0 PG bit is not set, it means paging is not enabled on BSP. Thus, Execute
Disable feature is not working actually. Thus, we cannot enable it on APs.

v2:
  Correct the commit log.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>

diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 55fe812d292ab3c8f3609e95f0cab8073ce88034..bb93526dd990cd7132c52c321ec6a9009842d026 100644 (file)
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -1,7 +1,7 @@
 /** @file\r
   CPU MP Initialize Library common functions.\r
 \r
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -18,8 +18,11 @@ EFI_GUID mCpuInitMpLibHobGuid = CPU_INIT_MP_LIB_HOB_GUID;
 \r
 /**\r
   The function will check if BSP Execute Disable is enabled.\r
-  DxeIpl may have enabled Execute Disable for BSP,\r
-  APs need to get the status and sync up the settings.\r
+\r
+  DxeIpl may have enabled Execute Disable for BSP, APs need to\r
+  get the status and sync up the settings.\r
+  If BSP's CR0.Paging is not set, BSP execute Disble feature is\r
+  not working actually.\r
 \r
   @retval TRUE      BSP Execute Disable is enabled.\r
   @retval FALSE     BSP Execute Disable is not enabled.\r
@@ -33,23 +36,30 @@ IsBspExecuteDisableEnabled (
   CPUID_EXTENDED_CPU_SIG_EDX  Edx;\r
   MSR_IA32_EFER_REGISTER      EferMsr;\r
   BOOLEAN                     Enabled;\r
+  IA32_CR0                    Cr0;\r
 \r
   Enabled = FALSE;\r
-  AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);\r
-  if (Eax >= CPUID_EXTENDED_CPU_SIG) {\r
-    AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &Edx.Uint32);\r
+  Cr0.UintN = AsmReadCr0 ();\r
+  if (Cr0.Bits.PG != 0) {\r
     //\r
-    // CPUID 0x80000001\r
-    // Bit 20: Execute Disable Bit available.\r
+    // If CR0 Paging bit is set\r
     //\r
-    if (Edx.Bits.NX != 0) {\r
-      EferMsr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);\r
+    AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);\r
+    if (Eax >= CPUID_EXTENDED_CPU_SIG) {\r
+      AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &Edx.Uint32);\r
       //\r
-      // MSR 0xC0000080\r
-      // Bit 11: Execute Disable Bit enable.\r
+      // CPUID 0x80000001\r
+      // Bit 20: Execute Disable Bit available.\r
       //\r
-      if (EferMsr.Bits.NXE != 0) {\r
-        Enabled = TRUE;\r
+      if (Edx.Bits.NX != 0) {\r
+        EferMsr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);\r
+        //\r
+        // MSR 0xC0000080\r
+        // Bit 11: Execute Disable Bit enable.\r
+        //\r
+        if (EferMsr.Bits.NXE != 0) {\r
+          Enabled = TRUE;\r
+        }\r
       }\r
     }\r
   }\r