UefiCpuPkg/Include: Add Ivy Bridge MSR include file

Add Ivy Bridge MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-9.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>

diff --git a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
new file mode 100644 (file)
index 0000000..0b08c0a
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
@@ -0,0 +1,2830 @@
+/** @file\r
+  MSR Definitions for Intel processors based on the Ivy Bridge microarchitecture.\r
+\r
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+  are provided for MSRs that contain one or more bit fields.  If the MSR value\r
+  returned is a single 32-bit or 64-bit value, then a data structure is not\r
+  provided for that MSR.\r
+\r
+  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+  @par Specification Reference:\r
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-9.\r
+\r
+**/\r
+\r
+#ifndef __IVY_BRIDGE_MSR_H__\r
+#define __IVY_BRIDGE_MSR_H__\r
+\r
+#include <Register/ArchitecturalMsr.h>\r
+\r
+/**\r
+  Package. See http://biosbits.org.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_PLATFORM_INFO (0x000000CE)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER  Msr;\r
+\r
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_PLATFORM_INFO             0x000000CE\r
+\r
+/**\r
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO\r
+**/\r
+typedef union {\r
+  ///\r
+  /// Individual bit fields\r
+  ///\r
+  struct {\r
+    UINT32  Reserved1:8;\r
+    ///\r
+    /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio\r
+    /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
+    /// MHz.\r
+    ///\r
+    UINT32  MaximumNonTurboRatio:8;\r
+    UINT32  Reserved2:12;\r
+    ///\r
+    /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When\r
+    /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
+    /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
+    /// Turbo mode is disabled.\r
+    ///\r
+    UINT32  RatioLimit:1;\r
+    ///\r
+    /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When\r
+    /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
+    /// and when set to 0, indicates TDP Limit for Turbo mode is not\r
+    /// programmable.\r
+    ///\r
+    UINT32  TDPLimit:1;\r
+    UINT32  Reserved3:2;\r
+    ///\r
+    /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O)  When set to 1,\r
+    /// indicates that LPM is supported, and when set to 0, indicates LPM is\r
+    /// not supported.\r
+    ///\r
+    UINT32  LowPowerModeSupport:1;\r
+    ///\r
+    /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base\r
+    /// TDP level available. 01: One additional TDP level available. 02: Two\r
+    /// additional TDP level available. 11: Reserved.\r
+    ///\r
+    UINT32  ConfigTDPLevels:2;\r
+    UINT32  Reserved4:5;\r
+    ///\r
+    /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the\r
+    /// minimum ratio (maximum efficiency) that the processor can operates, in\r
+    /// units of 100MHz.\r
+    ///\r
+    UINT32  MaximumEfficiencyRatio:8;\r
+    ///\r
+    /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the\r
+    /// minimum supported operating ratio in units of 100 MHz.\r
+    ///\r
+    UINT32  MinimumOperatingRatio:8;\r
+    UINT32  Reserved5:8;\r
+  } Bits;\r
+  ///\r
+  /// All bit fields as a 64-bit value\r
+  ///\r
+  UINT64  Uint64;\r
+} MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER;\r
+\r
+\r
+/**\r
+  Core. C-State Configuration Control (R/W)  Note: C-state values are\r
+  processor specific C-state code names, unrelated to MWAIT extension C-state\r
+  parameters or ACPI C-States. See http://biosbits.org.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;\r
+\r
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL    0x000000E2\r
+\r
+/**\r
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL\r
+**/\r
+typedef union {\r
+  ///\r
+  /// Individual bit fields\r
+  ///\r
+  struct {\r
+    ///\r
+    /// [Bits 2:0] Package C-State Limit (R/W)  Specifies the lowest\r
+    /// processor-specific C-state code name (consuming the least power). for\r
+    /// the package. The default is set as factory-configured package C-state\r
+    /// limit. The following C-state code name encodings are supported: 000b:\r
+    /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:\r
+    /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:\r
+    /// This field cannot be used to limit package C-state to C3.\r
+    ///\r
+    UINT32  Limit:3;\r
+    UINT32  Reserved1:7;\r
+    ///\r
+    /// [Bit 10] I/O MWAIT Redirection Enable (R/W)  When set, will map\r
+    /// IO_read instructions sent to IO register specified by\r
+    /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
+    ///\r
+    UINT32  IO_MWAIT:1;\r
+    UINT32  Reserved2:4;\r
+    ///\r
+    /// [Bit 15] CFG Lock (R/WO)  When set, lock bits 15:0 of this register\r
+    /// until next reset.\r
+    ///\r
+    UINT32  CFGLock:1;\r
+    UINT32  Reserved3:9;\r
+    ///\r
+    /// [Bit 25] C3 state auto demotion enable (R/W)  When set, the processor\r
+    /// will conditionally demote C6/C7 requests to C3 based on uncore\r
+    /// auto-demote information.\r
+    ///\r
+    UINT32  C3AutoDemotion:1;\r
+    ///\r
+    /// [Bit 26] C1 state auto demotion enable (R/W)  When set, the processor\r
+    /// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
+    /// auto-demote information.\r
+    ///\r
+    UINT32  C1AutoDemotion:1;\r
+    ///\r
+    /// [Bit 27] Enable C3 undemotion (R/W)  When set, enables undemotion from\r
+    /// demoted C3.\r
+    ///\r
+    UINT32  C3Undemotion:1;\r
+    ///\r
+    /// [Bit 28] Enable C1 undemotion (R/W)  When set, enables undemotion from\r
+    /// demoted C1.\r
+    ///\r
+    UINT32  C1Undemotion:1;\r
+    UINT32  Reserved4:3;\r
+    UINT32  Reserved5:32;\r
+  } Bits;\r
+  ///\r
+  /// All bit fields as a 32-bit value\r
+  ///\r
+  UINT32  Uint32;\r
+  ///\r
+  /// All bit fields as a 64-bit value\r
+  ///\r
+  UINT64  Uint64;\r
+} MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+  Package. Base TDP Ratio (R/O).\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL (0x00000648)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER  Msr;\r
+\r
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL        0x00000648\r
+\r
+/**\r
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL\r
+**/\r
+typedef union {\r
+  ///\r
+  /// Individual bit fields\r
+  ///\r
+  struct {\r
+    ///\r
+    /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this\r
+    /// specific processor (in units of 100 MHz).\r
+    ///\r
+    UINT32  Config_TDP_Base:8;\r
+    UINT32  Reserved1:24;\r
+    UINT32  Reserved2:32;\r
+  } Bits;\r
+  ///\r
+  /// All bit fields as a 32-bit value\r
+  ///\r
+  UINT32  Uint32;\r
+  ///\r
+  /// All bit fields as a 64-bit value\r
+  ///\r
+  UINT64  Uint64;\r
+} MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER;\r
+\r
+\r
+/**\r
+  Package. ConfigTDP Level 1 ratio and power level (R/O).\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 (0x00000649)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER  Msr;\r
+\r
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1         0x00000649\r
+\r
+/**\r
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1\r
+**/\r
+typedef union {\r
+  ///\r
+  /// Individual bit fields\r
+  ///\r
+  struct {\r
+    ///\r
+    /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.\r
+    ///\r
+    UINT32  PKG_TDP_LVL1:15;\r
+    UINT32  Reserved1:1;\r
+    ///\r
+    /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used\r
+    /// for this specific processor.\r
+    ///\r
+    UINT32  Config_TDP_LVL1_Ratio:8;\r
+    UINT32  Reserved2:8;\r
+    ///\r
+    /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP\r
+    /// Level 1.\r
+    ///\r
+    UINT32  PKG_MAX_PWR_LVL1:15;\r
+    UINT32  Reserved3:1;\r
+    ///\r
+    /// [Bits 62:48] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP\r
+    /// Level 1.\r
+    ///\r
+    UINT32  PKG_MIN_PWR_LVL1:15;\r
+    UINT32  Reserved4:1;\r
+  } Bits;\r
+  ///\r
+  /// All bit fields as a 64-bit value\r
+  ///\r
+  UINT64  Uint64;\r
+} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER;\r
+\r
+\r
+/**\r
+  Package. ConfigTDP Level 2 ratio and power level (R/O).\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 (0x0000064A)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER  Msr;\r
+\r
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2         0x0000064A\r
+\r
+/**\r
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2\r
+**/\r
+typedef union {\r
+  ///\r
+  /// Individual bit fields\r
+  ///\r
+  struct {\r
+    ///\r
+    /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.\r
+    ///\r
+    UINT32  PKG_TDP_LVL2:15;\r
+    UINT32  Reserved1:1;\r
+    ///\r
+    /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used\r
+    /// for this specific processor.\r
+    ///\r
+    UINT32  Config_TDP_LVL2_Ratio:8;\r
+    UINT32  Reserved2:8;\r
+    ///\r
+    /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP\r
+    /// Level 2.\r
+    ///\r
+    UINT32  PKG_MAX_PWR_LVL2:15;\r
+    UINT32  Reserved3:1;\r
+    ///\r
+    /// [Bits 62:48] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP\r
+    /// Level 2.\r
+    ///\r
+    UINT32  PKG_MIN_PWR_LVL2:15;\r
+    UINT32  Reserved4:1;\r
+  } Bits;\r
+  ///\r
+  /// All bit fields as a 64-bit value\r
+  ///\r
+  UINT64  Uint64;\r
+} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER;\r
+\r
+\r
+/**\r
+  Package. ConfigTDP Control (R/W).\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL (0x0000064B)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER  Msr;\r
+\r
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL, Msr.Uint64);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL        0x0000064B\r
+\r
+/**\r
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL\r
+**/\r
+typedef union {\r
+  ///\r
+  /// Individual bit fields\r
+  ///\r
+  struct {\r
+    ///\r
+    /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.\r
+    ///\r
+    UINT32  TDP_LEVEL:2;\r
+    UINT32  Reserved1:29;\r
+    ///\r
+    /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of\r
+    /// this register is locked until a reset.\r
+    ///\r
+    UINT32  Config_TDP_Lock:1;\r
+    UINT32  Reserved2:32;\r
+  } Bits;\r
+  ///\r
+  /// All bit fields as a 32-bit value\r
+  ///\r
+  UINT32  Uint32;\r
+  ///\r
+  /// All bit fields as a 64-bit value\r
+  ///\r
+  UINT64  Uint64;\r
+} MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+  Package. ConfigTDP Control (R/W).\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO (0x0000064C)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER  Msr;\r
+\r
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO, Msr.Uint64);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO    0x0000064C\r
+\r
+/**\r
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO\r
+**/\r
+typedef union {\r
+  ///\r
+  /// Individual bit fields\r
+  ///\r
+  struct {\r
+    ///\r
+    /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this\r
+    /// field.\r
+    ///\r
+    UINT32  MAX_NON_TURBO_RATIO:8;\r
+    UINT32  Reserved1:23;\r
+    ///\r
+    /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the\r
+    /// content of this register is locked until a reset.\r
+    ///\r
+    UINT32  TURBO_ACTIVATION_RATIO_Lock:1;\r
+    UINT32  Reserved2:32;\r
+  } Bits;\r
+  ///\r
+  /// All bit fields as a 32-bit value\r
+  ///\r
+  UINT32  Uint32;\r
+  ///\r
+  /// All bit fields as a 64-bit value\r
+  ///\r
+  UINT64  Uint64;\r
+} MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER;\r
+\r
+\r
+/**\r
+  Package. Protected Processor Inventory Number Enable Control (R/W).\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_PPIN_CTL (0x0000004E)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  MSR_IVY_BRIDGE_PPIN_CTL_REGISTER  Msr;\r
+\r
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PPIN_CTL, Msr.Uint64);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_PPIN_CTL                  0x0000004E\r
+\r
+/**\r
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_PPIN_CTL\r
+**/\r
+typedef union {\r
+  ///\r
+  /// Individual bit fields\r
+  ///\r
+  struct {\r
+    ///\r
+    /// [Bit 0] LockOut (R/WO) Set 1to prevent further writes to MSR_PPIN_CTL.\r
+    /// Writing 1 to MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit\r
+    /// 1] is clear, Default is 0. BIOS should provide an opt-in menu to\r
+    /// enable the user to turn on MSR_PPIN_CTL[bit 1] for privileged\r
+    /// inventory initialization agent to access MSR_PPIN. After reading\r
+    /// MSR_PPIN, the privileged inventory initialization agent should write\r
+    /// '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and\r
+    /// prevent unauthorized modification to MSR_PPIN_CTL.\r
+    ///\r
+    UINT32  LockOut:1;\r
+    ///\r
+    /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible\r
+    /// using RDMSR. Once set, attempt to write 1 to MSR_PPIN_CTL[bit 0] will\r
+    /// cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default\r
+    /// is 0.\r
+    ///\r
+    UINT32  Enable_PPIN:1;\r
+    UINT32  Reserved1:30;\r
+    UINT32  Reserved2:32;\r
+  } Bits;\r
+  ///\r
+  /// All bit fields as a 32-bit value\r
+  ///\r
+  UINT32  Uint32;\r
+  ///\r
+  /// All bit fields as a 64-bit value\r
+  ///\r
+  UINT64  Uint64;\r
+} MSR_IVY_BRIDGE_PPIN_CTL_REGISTER;\r
+\r
+\r
+/**\r
+  Package. Protected Processor Inventory Number (R/O). Protected Processor\r
+  Inventory Number (R/O) A unique value within a given CPUID\r
+  family/model/stepping signature that a privileged inventory initialization\r
+  agent can access to identify each physical processor, when access to\r
+  MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if\r
+  MSR_PPIN_CTL[bits 1:0] = '10b'.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_PPIN (0x0000004F)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_PPIN                      0x0000004F\r
+\r
+\r
+/**\r
+  Package. See http://biosbits.org.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_PLATFORM_INFO_1 (0x000000CE)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER  Msr;\r
+\r
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1, Msr.Uint64);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_PLATFORM_INFO_1           0x000000CE\r
+\r
+/**\r
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO_1\r
+**/\r
+typedef union {\r
+  ///\r
+  /// Individual bit fields\r
+  ///\r
+  struct {\r
+    UINT32  Reserved1:8;\r
+    ///\r
+    /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio\r
+    /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
+    /// MHz.\r
+    ///\r
+    UINT32  MaximumNonTurboRatio:8;\r
+    UINT32  Reserved2:7;\r
+    ///\r
+    /// [Bit 23] Package. PPIN_CAP (R/O) When set to 1, indicates that\r
+    /// Protected Processor Inventory Number (PPIN) capability can be enabled\r
+    /// for privileged system inventory agent to read PPIN from MSR_PPIN. When\r
+    /// set to 0, PPIN capability is not supported. An attempt to access\r
+    /// MSR_PPIN_CTL or MSR_PPIN will cause #GP.\r
+    ///\r
+    UINT32  PPIN_CAP:1;\r
+    UINT32  Reserved3:4;\r
+    ///\r
+    /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When\r
+    /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
+    /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
+    /// Turbo mode is disabled.\r
+    ///\r
+    UINT32  RatioLimit:1;\r
+    ///\r
+    /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When\r
+    /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
+    /// and when set to 0, indicates TDP Limit for Turbo mode is not\r
+    /// programmable.\r
+    ///\r
+    UINT32  TDPLimit:1;\r
+    ///\r
+    /// [Bit 30] Package. Programmable TJ OFFSET (R/O)  When set to 1,\r
+    /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to\r
+    /// specify an temperature offset.\r
+    ///\r
+    UINT32  TJOFFSET:1;\r
+    UINT32  Reserved4:1;\r
+    UINT32  Reserved5:8;\r
+    ///\r
+    /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the\r
+    /// minimum ratio (maximum efficiency) that the processor can operates, in\r
+    /// units of 100MHz.\r
+    ///\r
+    UINT32  MaximumEfficiencyRatio:8;\r
+    UINT32  Reserved6:16;\r
+  } Bits;\r
+  ///\r
+  /// All bit fields as a 64-bit value\r
+  ///\r
+  UINT64  Uint64;\r
+} MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER;\r
+\r
+\r
+/**\r
+  Package. MC Bank Error Configuration (R/W).\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_ERROR_CONTROL (0x0000017F)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER  Msr;\r
+\r
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL, Msr.Uint64);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_ERROR_CONTROL             0x0000017F\r
+\r
+/**\r
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_ERROR_CONTROL\r
+**/\r
+typedef union {\r
+  ///\r
+  /// Individual bit fields\r
+  ///\r
+  struct {\r
+    UINT32  Reserved1:1;\r
+    ///\r
+    /// [Bit 1] MemError Log Enable (R/W)  When set, enables IMC status bank\r
+    /// to log additional info in bits 36:32.\r
+    ///\r
+    UINT32  MemErrorLogEnable:1;\r
+    UINT32  Reserved2:30;\r
+    UINT32  Reserved3:32;\r
+  } Bits;\r
+  ///\r
+  /// All bit fields as a 32-bit value\r
+  ///\r
+  UINT32  Uint32;\r
+  ///\r
+  /// All bit fields as a 64-bit value\r
+  ///\r
+  UINT64  Uint64;\r
+} MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+  Package.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER  Msr;\r
+\r
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_TEMPERATURE_TARGET        0x000001A2\r
+\r
+/**\r
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_TEMPERATURE_TARGET\r
+**/\r
+typedef union {\r
+  ///\r
+  /// Individual bit fields\r
+  ///\r
+  struct {\r
+    UINT32  Reserved1:16;\r
+    ///\r
+    /// [Bits 23:16] Temperature Target (RO)  The minimum temperature at which\r
+    /// PROCHOT# will be asserted. The value is degree C.\r
+    ///\r
+    UINT32  TemperatureTarget:8;\r
+    ///\r
+    /// [Bits 27:24] TCC Activation Offset (R/W)  Specifies a temperature\r
+    /// offset in degrees C from the temperature target (bits 23:16). PROCHOT#\r
+    /// will assert at the offset target temperature. Write is permitted only\r
+    /// MSR_PLATFORM_INFO.[30] is set.\r
+    ///\r
+    UINT32  TCCActivationOffset:4;\r
+    UINT32  Reserved2:4;\r
+    UINT32  Reserved3:32;\r
+  } Bits;\r
+  ///\r
+  /// All bit fields as a 32-bit value\r
+  ///\r
+  UINT32  Uint32;\r
+  ///\r
+  /// All bit fields as a 64-bit value\r
+  ///\r
+  UINT64  Uint64;\r
+} MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER;\r
+\r
+\r
+/**\r
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
+  RW if MSR_PLATFORM_INFO.[28] = 1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 (0x000001AE)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER  Msr;\r
+\r
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1        0x000001AE\r
+\r
+/**\r
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1\r
+**/\r
+typedef union {\r
+  ///\r
+  /// Individual bit fields\r
+  ///\r
+  struct {\r
+    ///\r
+    /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio\r
+    /// limit of 9 core active.\r
+    ///\r
+    UINT32  Maximum9C:8;\r
+    ///\r
+    /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio\r
+    /// limit of 10core active.\r
+    ///\r
+    UINT32  Maximum10C:8;\r
+    ///\r
+    /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio\r
+    /// limit of 11 core active.\r
+    ///\r
+    UINT32  Maximum11C:8;\r
+    ///\r
+    /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio\r
+    /// limit of 12 core active.\r
+    ///\r
+    UINT32  Maximum12C:8;\r
+    ///\r
+    /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio\r
+    /// limit of 13 core active.\r
+    ///\r
+    UINT32  Maximum13C:8;\r
+    ///\r
+    /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio\r
+    /// limit of 14 core active.\r
+    ///\r
+    UINT32  Maximum14C:8;\r
+    ///\r
+    /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio\r
+    /// limit of 15 core active.\r
+    ///\r
+    UINT32  Maximum15C:8;\r
+    UINT32  Reserved:7;\r
+    ///\r
+    /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r
+    /// the processor uses override configuration specified in\r
+    /// MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor\r
+    /// uses factory-set configuration (Default).\r
+    ///\r
+    UINT32  TurboRatioLimitConfigurationSemaphore:1;\r
+  } Bits;\r
+  ///\r
+  /// All bit fields as a 64-bit value\r
+  ///\r
+  UINT64  Uint64;\r
+} MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER;\r
+\r
+\r
+/**\r
+  Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
+  15.3.2.4, "IA32_MCi_MISC MSRs.". Bank MC5 reports MC error from the Intel\r
+  QPI module.\r
+\r
+  * Bank MC6 reports MC error from the integrated I/O module.\r
+  * Banks MC7 and MC 8 report MC error from the two home agents.\r
+  * Banks MC9 through MC 16 report MC error from each channel of the integrated\r
+    memory controllers.\r
+  * Banks MC17 through MC31 reports MC error from a specific CBo\r
+    (core broadcast) and its corresponding slice of L3.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_MCi_CTL\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_CTL);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_CTL, Msr);\r
+  @endcode\r
+  @{\r
+**/\r
+#define MSR_IVY_BRIDGE_MC5_CTL                   0x00000414\r
+#define MSR_IVY_BRIDGE_MC6_CTL                   0x00000418\r
+#define MSR_IVY_BRIDGE_MC7_CTL                   0x0000041C\r
+#define MSR_IVY_BRIDGE_MC8_CTL                   0x00000420\r
+#define MSR_IVY_BRIDGE_MC9_CTL                   0x00000424\r
+#define MSR_IVY_BRIDGE_MC10_CTL                  0x00000428\r
+#define MSR_IVY_BRIDGE_MC11_CTL                  0x0000042C\r
+#define MSR_IVY_BRIDGE_MC12_CTL                  0x00000430\r
+#define MSR_IVY_BRIDGE_MC13_CTL                  0x00000434\r
+#define MSR_IVY_BRIDGE_MC14_CTL                  0x00000438\r
+#define MSR_IVY_BRIDGE_MC15_CTL                  0x0000043C\r
+#define MSR_IVY_BRIDGE_MC16_CTL                  0x00000440\r
+#define MSR_IVY_BRIDGE_MC17_CTL                  0x00000444\r
+#define MSR_IVY_BRIDGE_MC18_CTL                  0x00000448\r
+#define MSR_IVY_BRIDGE_MC19_CTL                  0x0000044C\r
+#define MSR_IVY_BRIDGE_MC20_CTL                  0x00000450\r
+#define MSR_IVY_BRIDGE_MC21_CTL                  0x00000454\r
+#define MSR_IVY_BRIDGE_MC22_CTL                  0x00000458\r
+#define MSR_IVY_BRIDGE_MC23_CTL                  0x0000045C\r
+#define MSR_IVY_BRIDGE_MC24_CTL                  0x00000460\r
+#define MSR_IVY_BRIDGE_MC25_CTL                  0x00000464\r
+#define MSR_IVY_BRIDGE_MC26_CTL                  0x00000468\r
+#define MSR_IVY_BRIDGE_MC27_CTL                  0x0000046C\r
+#define MSR_IVY_BRIDGE_MC28_CTL                  0x00000470\r
+#define MSR_IVY_BRIDGE_MC29_CTL                  0x00000474\r
+#define MSR_IVY_BRIDGE_MC30_CTL                  0x00000478\r
+#define MSR_IVY_BRIDGE_MC31_CTL                  0x0000047C\r
+/// @}\r
+\r
+\r
+/**\r
+  Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
+  15.3.2.4, "IA32_MCi_MISC MSRs.".\r
+\r
+  Bank MC20 reports MC error from a specific CBo (core broadcast) and\r
+  its corresponding slice of L3.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_MCi_STATUS\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_STATUS);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_STATUS, Msr);\r
+  @endcode\r
+  @{\r
+**/\r
+#define MSR_IVY_BRIDGE_MC5_STATUS                0x00000415\r
+#define MSR_IVY_BRIDGE_MC6_STATUS                0x00000419\r
+#define MSR_IVY_BRIDGE_MC7_STATUS                0x0000041D\r
+#define MSR_IVY_BRIDGE_MC8_STATUS                0x00000421\r
+#define MSR_IVY_BRIDGE_MC9_STATUS                0x00000425\r
+#define MSR_IVY_BRIDGE_MC10_STATUS               0x00000429\r
+#define MSR_IVY_BRIDGE_MC11_STATUS               0x0000042D\r
+#define MSR_IVY_BRIDGE_MC12_STATUS               0x00000431\r
+#define MSR_IVY_BRIDGE_MC13_STATUS               0x00000435\r
+#define MSR_IVY_BRIDGE_MC14_STATUS               0x00000439\r
+#define MSR_IVY_BRIDGE_MC15_STATUS               0x0000043D\r
+#define MSR_IVY_BRIDGE_MC16_STATUS               0x00000441\r
+#define MSR_IVY_BRIDGE_MC17_STATUS               0x00000445\r
+#define MSR_IVY_BRIDGE_MC18_STATUS               0x00000449\r
+#define MSR_IVY_BRIDGE_MC19_STATUS               0x0000044D\r
+#define MSR_IVY_BRIDGE_MC20_STATUS               0x00000451\r
+#define MSR_IVY_BRIDGE_MC21_STATUS               0x00000455\r
+#define MSR_IVY_BRIDGE_MC22_STATUS               0x00000459\r
+#define MSR_IVY_BRIDGE_MC23_STATUS               0x0000045D\r
+#define MSR_IVY_BRIDGE_MC24_STATUS               0x00000461\r
+#define MSR_IVY_BRIDGE_MC25_STATUS               0x00000465\r
+#define MSR_IVY_BRIDGE_MC26_STATUS               0x00000469\r
+#define MSR_IVY_BRIDGE_MC27_STATUS               0x0000046D\r
+#define MSR_IVY_BRIDGE_MC28_STATUS               0x00000471\r
+#define MSR_IVY_BRIDGE_MC29_STATUS               0x00000475\r
+#define MSR_IVY_BRIDGE_MC30_STATUS               0x00000479\r
+#define MSR_IVY_BRIDGE_MC31_STATUS               0x0000047D\r
+/// @}\r
+\r
+\r
+/**\r
+  Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
+  15.3.2.4, "IA32_MCi_MISC MSRs.".\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_MCi_ADDR\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_ADDR);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_ADDR, Msr);\r
+  @endcode\r
+  @{\r
+**/\r
+#define MSR_IVY_BRIDGE_MC5_ADDR                  0x00000416\r
+#define MSR_IVY_BRIDGE_MC6_ADDR                  0x0000041A\r
+#define MSR_IVY_BRIDGE_MC7_ADDR                  0x0000041E\r
+#define MSR_IVY_BRIDGE_MC8_ADDR                  0x00000422\r
+#define MSR_IVY_BRIDGE_MC9_ADDR                  0x00000426\r
+#define MSR_IVY_BRIDGE_MC10_ADDR                 0x0000042A\r
+#define MSR_IVY_BRIDGE_MC11_ADDR                 0x0000042E\r
+#define MSR_IVY_BRIDGE_MC12_ADDR                 0x00000432\r
+#define MSR_IVY_BRIDGE_MC13_ADDR                 0x00000436\r
+#define MSR_IVY_BRIDGE_MC14_ADDR                 0x0000043A\r
+#define MSR_IVY_BRIDGE_MC15_ADDR                 0x0000043E\r
+#define MSR_IVY_BRIDGE_MC16_ADDR                 0x00000442\r
+#define MSR_IVY_BRIDGE_MC17_ADDR                 0x00000446\r
+#define MSR_IVY_BRIDGE_MC18_ADDR                 0x0000044A\r
+#define MSR_IVY_BRIDGE_MC19_ADDR                 0x0000044E\r
+#define MSR_IVY_BRIDGE_MC20_ADDR                 0x00000452\r
+#define MSR_IVY_BRIDGE_MC21_ADDR                 0x00000456\r
+#define MSR_IVY_BRIDGE_MC22_ADDR                 0x0000045A\r
+#define MSR_IVY_BRIDGE_MC23_ADDR                 0x0000045E\r
+#define MSR_IVY_BRIDGE_MC24_ADDR                 0x00000462\r
+#define MSR_IVY_BRIDGE_MC25_ADDR                 0x00000466\r
+#define MSR_IVY_BRIDGE_MC26_ADDR                 0x0000046A\r
+#define MSR_IVY_BRIDGE_MC27_ADDR                 0x0000046E\r
+#define MSR_IVY_BRIDGE_MC28_ADDR                 0x00000472\r
+#define MSR_IVY_BRIDGE_MC29_ADDR                 0x00000476\r
+#define MSR_IVY_BRIDGE_MC30_ADDR                 0x0000047A\r
+#define MSR_IVY_BRIDGE_MC31_ADDR                 0x0000047E\r
+/// @}\r
+\r
+\r
+/**\r
+  Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
+  15.3.2.4, "IA32_MCi_MISC MSRs.".\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_MCi_MISC\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_MISC);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_MISC, Msr);\r
+  @endcode\r
+  @{\r
+**/\r
+#define MSR_IVY_BRIDGE_MC5_MISC                  0x00000417\r
+#define MSR_IVY_BRIDGE_MC6_MISC                  0x0000041B\r
+#define MSR_IVY_BRIDGE_MC7_MISC                  0x0000041F\r
+#define MSR_IVY_BRIDGE_MC8_MISC                  0x00000423\r
+#define MSR_IVY_BRIDGE_MC9_MISC                  0x00000427\r
+#define MSR_IVY_BRIDGE_MC10_MISC                 0x0000042B\r
+#define MSR_IVY_BRIDGE_MC11_MISC                 0x0000042F\r
+#define MSR_IVY_BRIDGE_MC12_MISC                 0x00000433\r
+#define MSR_IVY_BRIDGE_MC13_MISC                 0x00000437\r
+#define MSR_IVY_BRIDGE_MC14_MISC                 0x0000043B\r
+#define MSR_IVY_BRIDGE_MC15_MISC                 0x0000043F\r
+#define MSR_IVY_BRIDGE_MC16_MISC                 0x00000443\r
+#define MSR_IVY_BRIDGE_MC17_MISC                 0x00000447\r
+#define MSR_IVY_BRIDGE_MC18_MISC                 0x0000044B\r
+#define MSR_IVY_BRIDGE_MC19_MISC                 0x0000044F\r
+#define MSR_IVY_BRIDGE_MC20_MISC                 0x00000453\r
+#define MSR_IVY_BRIDGE_MC21_MISC                 0x00000457\r
+#define MSR_IVY_BRIDGE_MC22_MISC                 0x0000045B\r
+#define MSR_IVY_BRIDGE_MC23_MISC                 0x0000045F\r
+#define MSR_IVY_BRIDGE_MC24_MISC                 0x00000463\r
+#define MSR_IVY_BRIDGE_MC25_MISC                 0x00000467\r
+#define MSR_IVY_BRIDGE_MC26_MISC                 0x0000046B\r
+#define MSR_IVY_BRIDGE_MC27_MISC                 0x0000046F\r
+#define MSR_IVY_BRIDGE_MC28_MISC                 0x00000473\r
+#define MSR_IVY_BRIDGE_MC29_MISC                 0x00000477\r
+#define MSR_IVY_BRIDGE_MC30_MISC                 0x0000047B\r
+#define MSR_IVY_BRIDGE_MC31_MISC                 0x0000047F\r
+/// @}\r
+\r
+\r
+/**\r
+  Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_IA32_MC6_MISC (0x0000041B)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER  Msr;\r
+\r
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_IA32_MC6_MISC             0x0000041B\r
+\r
+/**\r
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC\r
+**/\r
+typedef union {\r
+  ///\r
+  /// Individual bit fields\r
+  ///\r
+  struct {\r
+    ///\r
+    /// [Bits 5:0] Recoverable Address LSB.\r
+    ///\r
+    UINT32  RecoverableAddressLSB:6;\r
+    ///\r
+    /// [Bits 8:6] Address Mode.\r
+    ///\r
+    UINT32  AddressMode:3;\r
+    UINT32  Reserved1:7;\r
+    ///\r
+    /// [Bits 31:16] PCI Express Requestor ID.\r
+    ///\r
+    UINT32  PCIExpressRequestorID:16;\r
+    ///\r
+    /// [Bits 39:32] PCI Express Segment Number.\r
+    ///\r
+    UINT32  PCIExpressSegmentNumber:8;\r
+    UINT32  Reserved2:24;\r
+  } Bits;\r
+  ///\r
+  /// All bit fields as a 64-bit value\r
+  ///\r
+  UINT64  Uint64;\r
+} MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER;\r
+\r
+\r
+/**\r
+  Package. Package RAPL Perf Status (R/O).\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_PKG_PERF_STATUS (0x00000613)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_PERF_STATUS);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_PKG_PERF_STATUS           0x00000613\r
+\r
+\r
+/**\r
+  Package. DRAM RAPL Power Limit Control (R/W)  See Section 14.9.5, "DRAM RAPL\r
+  Domain.".\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT          0x00000618\r
+\r
+\r
+/**\r
+  Package. DRAM Energy Status (R/O)  See Section 14.9.5, "DRAM RAPL Domain.".\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS        0x00000619\r
+\r
+\r
+/**\r
+  Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
+  RAPL Domain.".\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_PERF_STATUS);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_DRAM_PERF_STATUS          0x0000061B\r
+\r
+\r
+/**\r
+  Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_DRAM_POWER_INFO (0x0000061C)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_DRAM_POWER_INFO           0x0000061C\r
+\r
+\r
+/**\r
+  Thread. See Section 18.7.1.1, "Precise Event Based Sampling (PEBS).".\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+               Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER  Msr;\r
+\r
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE, Msr.Uint64);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_PEBS_ENABLE               0x000003F1\r
+\r
+/**\r
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_PEBS_ENABLE\r
+**/\r
+typedef union {\r
+  ///\r
+  /// Individual bit fields\r
+  ///\r
+  struct {\r
+    ///\r
+    /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
+    ///\r
+    UINT32  PEBS_EN_PMC0:1;\r
+    ///\r
+    /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).\r
+    ///\r
+    UINT32  PEBS_EN_PMC1:1;\r
+    ///\r
+    /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).\r
+    ///\r
+    UINT32  PEBS_EN_PMC2:1;\r
+    ///\r
+    /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).\r
+    ///\r
+    UINT32  PEBS_EN_PMC3:1;\r
+    UINT32  Reserved1:28;\r
+    ///\r
+    /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).\r
+    ///\r
+    UINT32  LL_EN_PMC0:1;\r
+    ///\r
+    /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).\r
+    ///\r
+    UINT32  LL_EN_PMC1:1;\r
+    ///\r
+    /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).\r
+    ///\r
+    UINT32  LL_EN_PMC2:1;\r
+    ///\r
+    /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).\r
+    ///\r
+    UINT32  LL_EN_PMC3:1;\r
+    UINT32  Reserved2:28;\r
+  } Bits;\r
+  ///\r
+  /// All bit fields as a 64-bit value\r
+  ///\r
+  UINT64  Uint64;\r
+} MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+  Package. Uncore perfmon per-socket global control.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_PMON_GLOBAL_CTL (0x00000C00)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL           0x00000C00\r
+\r
+\r
+/**\r
+  Package. Uncore perfmon per-socket global status.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS (0x00000C01)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS        0x00000C01\r
+\r
+\r
+/**\r
+  Package. Uncore perfmon per-socket global configuration.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG (0x00000C06)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG        0x00000C06\r
+\r
+\r
+/**\r
+  Package. Uncore U-box perfmon U-box wide status.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_U_PMON_BOX_STATUS (0x00000C15)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS         0x00000C15\r
+\r
+\r
+/**\r
+  Package. Uncore PCU perfmon box wide status.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS (0x00000C35)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS       0x00000C35\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 0 perfmon box wide filter1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 (0x00000D1A)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1       0x00000D1A\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 1 perfmon box wide filter1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 (0x00000D3A)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1       0x00000D3A\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 2 perfmon box wide filter1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 (0x00000D5A)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1       0x00000D5A\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 3 perfmon box wide filter1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 (0x00000D7A)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1       0x00000D7A\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 4 perfmon box wide filter1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 (0x00000D9A)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1       0x00000D9A\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 5 perfmon box wide filter1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 (0x00000DBA)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1       0x00000DBA\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 6 perfmon box wide filter1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 (0x00000DDA)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1       0x00000DDA\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 7 perfmon box wide filter1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 (0x00000DFA)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1       0x00000DFA\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 8 perfmon local box wide control.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_BOX_CTL (0x00000E04)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL           0x00000E04\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 (0x00000E10)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0          0x00000E10\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 (0x00000E11)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1          0x00000E11\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 (0x00000E12)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2          0x00000E12\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 (0x00000E13)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3          0x00000E13\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 8 perfmon box wide filter.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER (0x00000E14)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER        0x00000E14\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 8 perfmon counter 0.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_CTR0 (0x00000E16)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C8_PMON_CTR0              0x00000E16\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 8 perfmon counter 1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_CTR1 (0x00000E17)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C8_PMON_CTR1              0x00000E17\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 8 perfmon counter 2.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_CTR2 (0x00000E18)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C8_PMON_CTR2              0x00000E18\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 8 perfmon counter 3.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_CTR3 (0x00000E19)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C8_PMON_CTR3              0x00000E19\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 8 perfmon box wide filter1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 (0x00000E1A)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1       0x00000E1A\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 9 perfmon local box wide control.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_BOX_CTL (0x00000E24)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL           0x00000E24\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 (0x00000E30)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0          0x00000E30\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 (0x00000E31)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1          0x00000E31\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 (0x00000E32)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2          0x00000E32\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 (0x00000E33)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3          0x00000E33\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 9 perfmon box wide filter.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER (0x00000E34)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER        0x00000E34\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 9 perfmon counter 0.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_CTR0 (0x00000E36)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C9_PMON_CTR0              0x00000E36\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 9 perfmon counter 1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_CTR1 (0x00000E37)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C9_PMON_CTR1              0x00000E37\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 9 perfmon counter 2.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_CTR2 (0x00000E38)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C9_PMON_CTR2              0x00000E38\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 9 perfmon counter 3.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_CTR3 (0x00000E39)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C9_PMON_CTR3              0x00000E39\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 9 perfmon box wide filter1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 (0x00000E3A)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1       0x00000E3A\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 10 perfmon local box wide control.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_BOX_CTL (0x00000E44)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL          0x00000E44\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 (0x00000E50)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0         0x00000E50\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 (0x00000E51)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1         0x00000E51\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 (0x00000E52)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2         0x00000E52\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 (0x00000E53)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3         0x00000E53\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 10 perfmon box wide filter.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER (0x00000E54)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER       0x00000E54\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 10 perfmon counter 0.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_CTR0 (0x00000E56)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C10_PMON_CTR0             0x00000E56\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 10 perfmon counter 1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_CTR1 (0x00000E57)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C10_PMON_CTR1             0x00000E57\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 10 perfmon counter 2.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_CTR2 (0x00000E58)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C10_PMON_CTR2             0x00000E58\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 10 perfmon counter 3.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_CTR3 (0x00000E59)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C10_PMON_CTR3             0x00000E59\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 10 perfmon box wide filter1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 (0x00000E5A)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1      0x00000E5A\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 11 perfmon local box wide control.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_BOX_CTL (0x00000E64)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL          0x00000E64\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 (0x00000E70)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0         0x00000E70\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 (0x00000E71)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1         0x00000E71\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 (0x00000E72)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2         0x00000E72\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 (0x00000E73)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3         0x00000E73\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 11 perfmon box wide filter.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER (0x00000E74)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER       0x00000E74\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 11 perfmon counter 0.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_CTR0 (0x00000E76)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C11_PMON_CTR0             0x00000E76\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 11 perfmon counter 1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_CTR1 (0x00000E77)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C11_PMON_CTR1             0x00000E77\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 11 perfmon counter 2.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_CTR2 (0x00000E78)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C11_PMON_CTR2             0x00000E78\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 11 perfmon counter 3.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_CTR3 (0x00000E79)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C11_PMON_CTR3             0x00000E79\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 11 perfmon box wide filter1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 (0x00000E7A)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1      0x00000E7A\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 12 perfmon local box wide control.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_BOX_CTL (0x00000E84)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL          0x00000E84\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 (0x00000E90)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0         0x00000E90\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 (0x00000E91)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1         0x00000E91\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 (0x00000E92)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2         0x00000E92\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 (0x00000E93)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3         0x00000E93\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 12 perfmon box wide filter.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER (0x00000E94)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER       0x00000E94\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 12 perfmon counter 0.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_CTR0 (0x00000E96)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C12_PMON_CTR0             0x00000E96\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 12 perfmon counter 1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_CTR1 (0x00000E97)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C12_PMON_CTR1             0x00000E97\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 12 perfmon counter 2.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_CTR2 (0x00000E98)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C12_PMON_CTR2             0x00000E98\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 12 perfmon counter 3.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_CTR3 (0x00000E99)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C12_PMON_CTR3             0x00000E99\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 12 perfmon box wide filter1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 (0x00000E9A)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1      0x00000E9A\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 13 perfmon local box wide control.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_BOX_CTL (0x00000EA4)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL          0x00000EA4\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 (0x00000EB0)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0         0x00000EB0\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 (0x00000EB1)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1         0x00000EB1\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 (0x00000EB2)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2         0x00000EB2\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 (0x00000EB3)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3         0x00000EB3\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 13 perfmon box wide filter.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER (0x00000EB4)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER       0x00000EB4\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 13 perfmon counter 0.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_CTR0 (0x00000EB6)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C13_PMON_CTR0             0x00000EB6\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 13 perfmon counter 1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_CTR1 (0x00000EB7)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C13_PMON_CTR1             0x00000EB7\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 13 perfmon counter 2.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_CTR2 (0x00000EB8)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C13_PMON_CTR2             0x00000EB8\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 13 perfmon counter 3.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_CTR3 (0x00000EB9)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C13_PMON_CTR3             0x00000EB9\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 13 perfmon box wide filter1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 (0x00000EBA)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1      0x00000EBA\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 14 perfmon local box wide control.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_BOX_CTL (0x00000EC4)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL          0x00000EC4\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 (0x00000ED0)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0         0x00000ED0\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 (0x00000ED1)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1         0x00000ED1\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 (0x00000ED2)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2         0x00000ED2\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 (0x00000ED3)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3         0x00000ED3\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 14 perfmon box wide filter.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER (0x00000ED4)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER       0x00000ED4\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 14 perfmon counter 0.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_CTR0 (0x00000ED6)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C14_PMON_CTR0             0x00000ED6\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 14 perfmon counter 1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_CTR1 (0x00000ED7)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C14_PMON_CTR1             0x00000ED7\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 14 perfmon counter 2.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_CTR2 (0x00000ED8)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C14_PMON_CTR2             0x00000ED8\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 14 perfmon counter 3.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_CTR3 (0x00000ED9)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C14_PMON_CTR3             0x00000ED9\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 14 perfmon box wide filter1.\r
+\r
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 (0x00000EDA)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1);\r
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1      0x00000EDA\r
+\r
+#endif\r