MdePkg/BaseLib: add PatchInstructionX86()

Some edk2 modules generate X86 machine code at module execution time by:

- compiling "template" code with NASM at module build time,

- linking the object code into the module,

- and patching the immediate (constant) operands of some instructions when
  the module is executed.

Add a helper function to BaseLib so that the C code performing the
patching is easier to read and maintain.

The implementation in this patch is taken mainly from Mike Kinney's
mailing list messages at
<http://mid.mail-archive.com/E92EE9817A31E24EB0585FDF735412F5B895C360@ORSMSX113.amr.corp.intel.com>,
<http://mid.mail-archive.com/E92EE9817A31E24EB0585FDF735412F5B898BF66@ORSMSX112.amr.corp.intel.com>.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index e4455e71d5c3fab916ec14ab760204355b9c1c86..eb2899f8524e7a8e1856d68f0c25ced58c4253fb 100644 (file)
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -6881,6 +6881,20 @@ typedef struct {
 #define THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15   0x00000002\r
 #define THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL 0x00000004\r
 \r
+///\r
+/// Type definition for representing labels in NASM source code that allow for\r
+/// the patching of immediate operands of IA32 and X64 instructions.\r
+///\r
+/// While the type is technically defined as a function type (note: not a\r
+/// pointer-to-function type), such labels in NASM source code never stand for\r
+/// actual functions, and identifiers declared with this function type should\r
+/// never be called. This is also why the EFIAPI calling convention specifier\r
+/// is missing from the typedef, and why the typedef does not follow the usual\r
+/// edk2 coding style for function (or pointer-to-function) typedefs. The VOID\r
+/// return type and the VOID argument list are merely artifacts.\r
+///\r
+typedef VOID (X86_ASSEMBLY_PATCH_LABEL) (VOID);\r
+\r
 /**\r
   Retrieves CPUID information.\r
 \r
@@ -9068,5 +9082,47 @@ AsmWriteTr (
   IN UINT16 Selector\r
   );\r
 \r
+/**\r
+  Patch the immediate operand of an IA32 or X64 instruction such that the byte,\r
+  word, dword or qword operand is encoded at the end of the instruction's\r
+  binary representation.\r
+\r
+  This function should be used to update object code that was compiled with\r
+  NASM from assembly source code. Example:\r
+\r
+  NASM source code:\r
+\r
+        mov     eax, strict dword 0 ; the imm32 zero operand will be patched\r
+    ASM_PFX(gPatchCr3):\r
+        mov     cr3, eax\r
+\r
+  C source code:\r
+\r
+    X86_ASSEMBLY_PATCH_LABEL gPatchCr3;\r
+    PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);\r
+\r
+  @param[out] InstructionEnd  Pointer right past the instruction to patch. The\r
+                              immediate operand to patch is expected to\r
+                              comprise the trailing bytes of the instruction.\r
+                              If InstructionEnd is closer to address 0 than\r
+                              ValueSize permits, then ASSERT().\r
+\r
+  @param[in] PatchValue       The constant to write to the immediate operand.\r
+                              The caller is responsible for ensuring that\r
+                              PatchValue can be represented in the byte, word,\r
+                              dword or qword operand (as indicated through\r
+                              ValueSize); otherwise ASSERT().\r
+\r
+  @param[in] ValueSize        The size of the operand in bytes; must be 1, 2,\r
+                              4, or 8. ASSERT() otherwise.\r
+**/\r
+VOID\r
+EFIAPI\r
+PatchInstructionX86 (\r
+  OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,\r
+  IN  UINT64                   PatchValue,\r
+  IN  UINTN                    ValueSize\r
+  );\r
+\r
 #endif // defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
 #endif // !defined (__BASE_LIB__)\r

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 80d00ebed75ba00e25a257d3542e00f92cf5cccc..5fbbd02a94b62e74ffe155c78a48bb2925e6c420 100644 (file)
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -431,6 +431,7 @@
   X86DisablePaging64.c\r
   X86DisablePaging32.c\r
   X86RdRand.c\r
+  X86PatchInstruction.c\r
 \r
 [Sources.X64]\r
   X64/Thunk16.nasm\r
@@ -757,6 +758,7 @@
   X86DisablePaging64.c\r
   X86DisablePaging32.c\r
   X86RdRand.c\r
+  X86PatchInstruction.c\r
   X64/GccInline.c | GCC\r
   X64/Thunk16.S | XCODE \r
   X64/SwitchStack.nasm| GCC\r

diff --git a/MdePkg/Library/BaseLib/X86PatchInstruction.c b/MdePkg/Library/BaseLib/X86PatchInstruction.c
new file mode 100644 (file)
index 0000000..536d47a
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X86PatchInstruction.c
@@ -0,0 +1,89 @@
+/** @file\r
+  IA-32/x64 PatchInstructionX86()\r
+\r
+  Copyright (C) 2018, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (C) 2018, Red Hat, Inc.\r
+\r
+  This program and the accompanying materials are licensed and made available\r
+  under the terms and conditions of the BSD License which accompanies this\r
+  distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+  Patch the immediate operand of an IA32 or X64 instruction such that the byte,\r
+  word, dword or qword operand is encoded at the end of the instruction's\r
+  binary representation.\r
+\r
+  This function should be used to update object code that was compiled with\r
+  NASM from assembly source code. Example:\r
+\r
+  NASM source code:\r
+\r
+        mov     eax, strict dword 0 ; the imm32 zero operand will be patched\r
+    ASM_PFX(gPatchCr3):\r
+        mov     cr3, eax\r
+\r
+  C source code:\r
+\r
+    X86_ASSEMBLY_PATCH_LABEL gPatchCr3;\r
+    PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);\r
+\r
+  @param[out] InstructionEnd  Pointer right past the instruction to patch. The\r
+                              immediate operand to patch is expected to\r
+                              comprise the trailing bytes of the instruction.\r
+                              If InstructionEnd is closer to address 0 than\r
+                              ValueSize permits, then ASSERT().\r
+\r
+  @param[in] PatchValue       The constant to write to the immediate operand.\r
+                              The caller is responsible for ensuring that\r
+                              PatchValue can be represented in the byte, word,\r
+                              dword or qword operand (as indicated through\r
+                              ValueSize); otherwise ASSERT().\r
+\r
+  @param[in] ValueSize        The size of the operand in bytes; must be 1, 2,\r
+                              4, or 8. ASSERT() otherwise.\r
+**/\r
+VOID\r
+EFIAPI\r
+PatchInstructionX86 (\r
+  OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,\r
+  IN  UINT64                   PatchValue,\r
+  IN  UINTN                    ValueSize\r
+  )\r
+{\r
+  //\r
+  // The equality ((UINTN)InstructionEnd == ValueSize) would assume a zero-size\r
+  // instruction at address 0; forbid it.\r
+  //\r
+  ASSERT ((UINTN)InstructionEnd > ValueSize);\r
+\r
+  switch (ValueSize) {\r
+  case 1:\r
+    ASSERT (PatchValue <= MAX_UINT8);\r
+    *((UINT8 *)(UINTN)InstructionEnd - 1) = (UINT8)PatchValue;\r
+    break;\r
+\r
+  case 2:\r
+    ASSERT (PatchValue <= MAX_UINT16);\r
+    WriteUnaligned16 ((UINT16 *)(UINTN)InstructionEnd - 1, (UINT16)PatchValue);\r
+    break;\r
+\r
+  case 4:\r
+    ASSERT (PatchValue <= MAX_UINT32);\r
+    WriteUnaligned32 ((UINT32 *)(UINTN)InstructionEnd - 1, (UINT32)PatchValue);\r
+    break;\r
+\r
+  case 8:\r
+    WriteUnaligned64 ((UINT64 *)(UINTN)InstructionEnd - 1, PatchValue);\r
+    break;\r
+\r
+  default:\r
+    ASSERT (FALSE);\r
+  }\r
+}\r