UefiCpuPkg/PiSmmCpuDxeSmm: Replace mIsBsp by mBspApicId check

This patch is to replace mIsBsp by mBspApicId check.
mIsBsp becomes the local variable (IsBsp), then it can be
checked dynamically in the function. Instead, we define the
mBspApicId, which is to record the BSP ApicId used for
compare in SmmInitHandler. With this change, SmmInitHandler
can be run in parallel during SMM init.

Note:
This patch is the per-prepared work by refining the
SmmInitHandler, then, we can do the next step to
combine 2 SMIs (gcSmmInitTemplate & gcSmiHandlerTemplate)
into one (gcSmiHandlerTemplate), the new SMI handler
will call the SmmInitHandler in parallel to do the init.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zeng Star <star.zeng@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index 2ac655d032816ba0e8064f56a2f103cd6e4a8ca1..6e795d1756525037bdd0aa8f4afa99ffe33995f4 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -59,7 +59,6 @@ SMM_CPU_PRIVATE_DATA  *gSmmCpuPrivate = &mSmmCpuPrivateData;
 // SMM Relocation variables\r
 //\r
 volatile BOOLEAN  *mRebased;\r
-volatile BOOLEAN  mIsBsp;\r
 \r
 ///\r
 /// Handle for the SMM CPU Protocol\r
@@ -85,6 +84,8 @@ EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL  mSmmMemoryAttribute = {
 \r
 EFI_CPU_INTERRUPT_HANDLER  mExternalVectorTable[EXCEPTION_VECTOR_NUMBER];\r
 \r
+UINT32            mBspApicId       = 0;\r
+\r
 //\r
 // SMM stack information\r
 //\r
@@ -343,8 +344,9 @@ SmmInitHandler (
   VOID\r
   )\r
 {\r
-  UINT32  ApicId;\r
-  UINTN   Index;\r
+  UINT32   ApicId;\r
+  UINTN    Index;\r
+  BOOLEAN  IsBsp;\r
 \r
   //\r
   // Update SMM IDT entries' code segment and load IDT\r
@@ -352,6 +354,8 @@ SmmInitHandler (
   AsmWriteIdtr (&gcSmiIdtr);\r
   ApicId = GetApicId ();\r
 \r
+  IsBsp = (BOOLEAN)(mBspApicId == ApicId);\r
+\r
   ASSERT (mNumberOfCpus <= mMaxNumberOfCpus);\r
 \r
   for (Index = 0; Index < mNumberOfCpus; Index++) {\r
@@ -361,7 +365,7 @@ SmmInitHandler (
       //\r
       SmmCpuFeaturesInitializeProcessor (\r
         Index,\r
-        mIsBsp,\r
+        IsBsp,\r
         gSmmCpuPrivate->ProcessorInfo,\r
         &mCpuHotPlugData\r
         );\r
@@ -371,7 +375,7 @@ SmmInitHandler (
         // Check XD and BTS features on each processor on normal boot\r
         //\r
         CheckFeatureSupported ();\r
-      } else if (mIsBsp) {\r
+      } else if (IsBsp) {\r
         //\r
         // BSP rebase is already done above.\r
         // Initialize private data during S3 resume\r
@@ -407,7 +411,6 @@ SmmRelocateBases (
   SMRAM_SAVE_STATE_MAP  BakBuf2;\r
   SMRAM_SAVE_STATE_MAP  *CpuStatePtr;\r
   UINT8                 *U8Ptr;\r
-  UINT32                ApicId;\r
   UINTN                 Index;\r
   UINTN                 BspIndex;\r
 \r
@@ -448,17 +451,16 @@ SmmRelocateBases (
   //\r
   // Retrieve the local APIC ID of current processor\r
   //\r
-  ApicId = GetApicId ();\r
+  mBspApicId = GetApicId ();\r
 \r
   //\r
   // Relocate SM bases for all APs\r
   // This is APs' 1st SMI - rebase will be done here, and APs' default SMI handler will be overridden by gcSmmInitTemplate\r
   //\r
-  mIsBsp   = FALSE;\r
   BspIndex = (UINTN)-1;\r
   for (Index = 0; Index < mNumberOfCpus; Index++) {\r
     mRebased[Index] = FALSE;\r
-    if (ApicId != (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {\r
+    if (mBspApicId != (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {\r
       SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId);\r
       //\r
       // Wait for this AP to finish its 1st SMI\r
@@ -477,8 +479,7 @@ SmmRelocateBases (
   // Relocate BSP's SMM base\r
   //\r
   ASSERT (BspIndex != (UINTN)-1);\r
-  mIsBsp = TRUE;\r
-  SendSmiIpi (ApicId);\r
+  SendSmiIpi (mBspApicId);\r
   //\r
   // Wait for the BSP to finish its 1st SMI\r
   //\r