+++ /dev/null
-/** @file\r
- Differentiated System Description Table Fields (SSDT)\r
-\r
- Copyright (c) 2014-2015, ARM Ltd. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include "ArmPlatform.h"\r
-\r
-/*\r
- See Reference [1] 6.2.12\r
- "There are two ways that _PRT can be used. ...\r
- In the second model, the PCI interrupts are hardwired to specific interrupt\r
- inputs on the interrupt controller and are not configurable. In this case,\r
- the Source field in _PRT does not reference a device, but instead contains\r
- the value zero, and the Source Index field contains the global system\r
- interrupt to which the PCI interrupt is hardwired."\r
-*/\r
-#define PRT_ENTRY(Address, Pin, Interrupt) \\r
- Package (4) { \\r
- Address, /* uses the same format as _ADR */ \\r
- Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \\r
- Zero, /* allocated from the global interrupt pool. */ \\r
- Interrupt /* global system interrupt number */ \\r
- }\r
-\r
-/*\r
- See Reference [1] 6.1.1\r
- "High word–Device #, Low word–Function #. (for example, device 3, function 2 is\r
- 0x00030002). To refer to all the functions on a device #, use a function number of FFFF)."\r
-*/\r
-#define ROOT_PRT_ENTRY(Pin, Interrupt) PRT_ENTRY(0x0000FFFF, Pin, Interrupt)\r
- // Device 0 for Bridge.\r
-\r
-\r
-DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {\r
- Scope(_SB) {\r
- //\r
- // PCI Root Complex\r
- //\r
- Device(PCI0)\r
- {\r
- Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge\r
- Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge\r
- Name(_SEG, Zero) // PCI Segment Group number\r
- Name(_BBN, Zero) // PCI Base Bus Number\r
- Name(_CCA, 1) // Initially mark the PCI coherent (for JunoR1)\r
-\r
- // Root Complex 0\r
- Device (RP0) {\r
- Name(_ADR, 0xF0000000) // Dev 0, Func 0\r
- }\r
-\r
- // PCI Routing Table\r
- Name(_PRT, Package() {\r
- ROOT_PRT_ENTRY(0, 168), // INTA\r
- ROOT_PRT_ENTRY(1, 169), // INTB\r
- ROOT_PRT_ENTRY(2, 170), // INTC\r
- ROOT_PRT_ENTRY(3, 171), // INTD\r
- })\r
- // Root complex resources\r
- Method (_CRS, 0, Serialized) {\r
- Name (RBUF, ResourceTemplate () {\r
- WordBusNumber ( // Bus numbers assigned to this root\r
- ResourceProducer,\r
- MinFixed, MaxFixed, PosDecode,\r
- 0, // AddressGranularity\r
- 0, // AddressMinimum - Minimum Bus Number\r
- 255, // AddressMaximum - Maximum Bus Number\r
- 0, // AddressTranslation - Set to 0\r
- 256 // RangeLength - Number of Busses\r
- )\r
-\r
- DWordMemory ( // 32-bit BAR Windows\r
- ResourceProducer, PosDecode,\r
- MinFixed, MaxFixed,\r
- Cacheable, ReadWrite,\r
- 0x00000000, // Granularity\r
- 0x50000000, // Min Base Address\r
- 0x57FFFFFF, // Max Base Address\r
- 0x00000000, // Translate\r
- 0x08000000 // Length\r
- )\r
-\r
- QWordMemory ( // 64-bit BAR Windows\r
- ResourceProducer, PosDecode,\r
- MinFixed, MaxFixed,\r
- Cacheable, ReadWrite,\r
- 0x00000000, // Granularity\r
- 0x4000000000, // Min Base Address\r
- 0x40FFFFFFFF, // Max Base Address\r
- 0x00000000, // Translate\r
- 0x100000000 // Length\r
- )\r
-\r
- DWordIo ( // IO window\r
- ResourceProducer,\r
- MinFixed,\r
- MaxFixed,\r
- PosDecode,\r
- EntireRange,\r
- 0x00000000, // Granularity\r
- 0x5f800000, // Min Base Address\r
- 0x5fffffff, // Max Base Address\r
- 0x5f800000, // Translate\r
- 0x00800000 // Length\r
- )\r
- }) // Name(RBUF)\r
-\r
- Return (RBUF)\r
- } // Method(_CRS)\r
-\r
- //\r
- // OS Control Handoff\r
- //\r
- Name(SUPP, Zero) // PCI _OSC Support Field value\r
- Name(CTRL, Zero) // PCI _OSC Control Field value\r
-\r
- /*\r
- See [1] 6.2.10, [2] 4.5\r
- */\r
- Method(_OSC,4) {\r
- // Check for proper UUID\r
- If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {\r
- // Create DWord-adressable fields from the Capabilities Buffer\r
- CreateDWordField(Arg3,0,CDW1)\r
- CreateDWordField(Arg3,4,CDW2)\r
- CreateDWordField(Arg3,8,CDW3)\r
-\r
- // Save Capabilities DWord2 & 3\r
- Store(CDW2,SUPP)\r
- Store(CDW3,CTRL)\r
-\r
- // Only allow native hot plug control if OS supports:\r
- // * ASPM\r
- // * Clock PM\r
- // * MSI/MSI-X\r
- If(LNotEqual(And(SUPP, 0x16), 0x16)) {\r
- And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)\r
- }\r
-\r
- // Always allow native PME, AER (no dependencies)\r
-\r
- // Never allow SHPC (no SHPC controller in this system)\r
- And(CTRL,0x1D,CTRL)\r
-\r
-#if 0\r
- If(LNot(And(CDW1,1))) { // Query flag clear?\r
- // Disable GPEs for features granted native control.\r
- If(And(CTRL,0x01)) { // Hot plug control granted?\r
- Store(0,HPCE) // clear the hot plug SCI enable bit\r
- Store(1,HPCS) // clear the hot plug SCI status bit\r
- }\r
- If(And(CTRL,0x04)) { // PME control granted?\r
- Store(0,PMCE) // clear the PME SCI enable bit\r
- Store(1,PMCS) // clear the PME SCI status bit\r
- }\r
- If(And(CTRL,0x10)) { // OS restoring PCIe cap structure?\r
- // Set status to not restore PCIe cap structure\r
- // upon resume from S3\r
- Store(1,S3CR)\r
- }\r
- }\r
-#endif\r
-\r
- If(LNotEqual(Arg1,One)) { // Unknown revision\r
- Or(CDW1,0x08,CDW1)\r
- }\r
-\r
- If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked\r
- Or(CDW1,0x10,CDW1)\r
- }\r
- // Update DWORD3 in the buffer\r
- Store(CTRL,CDW3)\r
- Return(Arg3)\r
- } Else {\r
- Or(CDW1,4,CDW1) // Unrecognized UUID\r
- Return(Arg3)\r
- }\r
- } // End _OSC\r
- } // PCI0\r
- }\r
-}\r
+++ /dev/null
-## @file\r
-#\r
-# ACPI table data and ASL sources required to boot the platform.\r
-#\r
-# Copyright (c) 2014-2015, ARM Ltd. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-##\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = JunoAcpiTables\r
- FILE_GUID = a1dd808e-1e95-4399-abc0-653c82e8530c\r
- MODULE_TYPE = USER_DEFINED\r
- VERSION_STRING = 1.0\r
-\r
-[Sources]\r
- Dsdt.asl\r
- Facs.aslc\r
- Fadt.aslc\r
- Gtdt.aslc\r
- Madt.aslc\r
- AcpiSsdtRootPci.asl # Juno R1 specific\r
-\r
-[Packages]\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
- ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec\r
- ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
- MdePkg/MdePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
-\r
-[FixedPcd]\r
- gArmPlatformTokenSpaceGuid.PcdCoreCount\r
- gArmTokenSpaceGuid.PcdGicDistributorBase\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
-\r
- gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum\r
- gArmTokenSpaceGuid.PcdArmArchTimerIntrNum\r
- gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum\r
- gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum\r
-\r
- gArmTokenSpaceGuid.PcdGenericWatchdogControlBase\r
- gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase\r
+++ /dev/null
-/** @file\r
- Differentiated System Description Table Fields (DSDT)\r
-\r
- Copyright (c) 2014-2015, ARM Ltd. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include "ArmPlatform.h"\r
-\r
-DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {\r
- Scope(_SB) {\r
- //\r
- // A57x2-A53x4 Processor declaration\r
- //\r
- Device(CPU0) { // A53-0: Cluster 1, Cpu 0\r
- Name(_HID, "ACPI0007")\r
- Name(_UID, 0)\r
- }\r
- Device(CPU1) { // A53-1: Cluster 1, Cpu 1\r
- Name(_HID, "ACPI0007")\r
- Name(_UID, 1)\r
- }\r
- Device(CPU2) { // A53-2: Cluster 1, Cpu 2\r
- Name(_HID, "ACPI0007")\r
- Name(_UID, 2)\r
- }\r
- Device(CPU3) { // A53-3: Cluster 1, Cpu 3\r
- Name(_HID, "ACPI0007")\r
- Name(_UID, 3)\r
- }\r
- Device(CPU4) { // A57-0: Cluster 0, Cpu 0\r
- Name(_HID, "ACPI0007")\r
- Name(_UID, 4)\r
- }\r
- Device(CPU5) { // A57-1: Cluster 0, Cpu 1\r
- Name(_HID, "ACPI0007")\r
- Name(_UID, 5)\r
- }\r
-\r
- //\r
- // Keyboard and Mouse\r
- //\r
- Device(KMI0) {\r
- Name(_HID, "ARMH0501")\r
- Name(_CID, "PL050_KBD")\r
- Name(_CRS, ResourceTemplate() {\r
- Memory32Fixed(ReadWrite, 0x1C060008, 0x4)\r
- Memory32Fixed(ReadWrite, 0x1C060000, 0x4)\r
- Memory32Fixed(ReadOnly, 0x1C060004, 0x4)\r
- Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 197 }\r
- })\r
- }\r
-\r
- //\r
- // LAN9118 Ethernet\r
- //\r
- Device(ETH0) {\r
- Name(_HID, "ARMH9118")\r
- Name(_UID, Zero)\r
- Name(_CRS, ResourceTemplate() {\r
- Memory32Fixed(ReadWrite, 0x1A000000, 0x1000)\r
- Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 192 }\r
- })\r
- Name(_DSD, Package() {\r
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),\r
- Package() {\r
- Package(2) {"phy-mode", "mii"},\r
- Package(2) {"reg-io-width", 4 },\r
- Package(2) {"smsc,irq-active-high",1},\r
- Package(2) {"smsc,irq-push-pull",1}\r
- }\r
- }) // _DSD()\r
- }\r
-\r
- // UART PL011\r
- Device(COM0) {\r
- Name(_HID, "ARMH0011")\r
- Name(_CID, "PL011")\r
- Name(_UID, Zero)\r
- Name(_CRS, ResourceTemplate() {\r
- Memory32Fixed(ReadWrite, 0x7FF80000, 0x1000)\r
- Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 115 }\r
- })\r
- }\r
-\r
- //\r
- // USB EHCI Host Controller\r
- //\r
- Device(USB0){\r
- Name(_HID, "ARMH0D20")\r
- Name(_CID, "PNP0D20")\r
- Name(_UID, 2)\r
- Name(_CCA, 0) //EHCI on this platform is not coherent!\r
-\r
- Method(_CRS, 0x0, Serialized){\r
- Name(RBUF, ResourceTemplate(){\r
- Memory32Fixed(ReadWrite, 0x7FFC0000, 0x10000)\r
- Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {149} // INT ID=149 GIC IRQ ID=117 for Juno SoC USB EHCI Controller\r
- })\r
- Return(RBUF)\r
- }\r
-\r
- //\r
- // Root Hub\r
- //\r
- Device(RHUB){\r
- Name(_ADR, 0x00000000) // Address of Root Hub should be 0 as per ACPI 5.0 spec\r
-\r
- //\r
- // Ports connected to Root Hub\r
- //\r
- Device(HUB1){\r
- Name(_ADR, 0x00000001)\r
- Name(_UPC, Package(){\r
- 0x00, // Port is NOT connectable\r
- 0xFF, // Don't care\r
- 0x00000000, // Reserved 0 must be zero\r
- 0x00000000 // Reserved 1 must be zero\r
- })\r
-\r
- Device(PRT1){\r
- Name(_ADR, 0x00000001)\r
- Name(_UPC, Package(){\r
- 0xFF, // Port is connectable\r
- 0x00, // Port connector is A\r
- 0x00000000,\r
- 0x00000000\r
- })\r
- Name(_PLD, Package(){\r
- Buffer(0x10){\r
- 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
- 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\r
- }\r
- })\r
- } // USB0_RHUB_HUB1_PRT1\r
- Device(PRT2){\r
- Name(_ADR, 0x00000002)\r
- Name(_UPC, Package(){\r
- 0xFF, // Port is connectable\r
- 0x00, // Port connector is A\r
- 0x00000000,\r
- 0x00000000\r
- })\r
- Name(_PLD, Package(){\r
- Buffer(0x10){\r
- 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
- 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\r
- }\r
- })\r
- } // USB0_RHUB_HUB1_PRT2\r
-\r
- Device(PRT3){\r
- Name(_ADR, 0x00000003)\r
- Name(_UPC, Package(){\r
- 0xFF, // Port is connectable\r
- 0x00, // Port connector is A\r
- 0x00000000,\r
- 0x00000000\r
- })\r
- Name(_PLD, Package(){\r
- Buffer(0x10){\r
- 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
- 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\r
- }\r
- })\r
- } // USB0_RHUB_HUB1_PRT3\r
-\r
- Device(PRT4){\r
- Name(_ADR, 0x00000004)\r
- Name(_UPC, Package(){\r
- 0xFF, // Port is connectable\r
- 0x00, // Port connector is A\r
- 0x00000000,\r
- 0x00000000\r
- })\r
- Name(_PLD, Package(){\r
- Buffer(0x10){\r
- 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
- 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\r
- }\r
- })\r
- } // USB0_RHUB_HUB1_PRT4\r
- } // USB0_RHUB_HUB1\r
- } // USB0_RHUB\r
- } // USB0\r
- } // Scope(_SB)\r
-}\r
+++ /dev/null
-/** @file\r
-* Firmware ACPI Control Structure (FACS)\r
-*\r
-* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <IndustryStandard/Acpi.h>\r
-\r
-EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = {\r
- EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature\r
- sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length\r
- 0xA152, // UINT32 HardwareSignature\r
- 0, // UINT32 FirmwareWakingVector\r
- 0, // UINT32 GlobalLock\r
- 0, // UINT32 Flags\r
- 0, // UINT64 XFirmwareWakingVector\r
- EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version;\r
- { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1]\r
- EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2]\r
- 0, // UINT32 OspmFlags "Platform firmware must\r
- // initialize this field to zero."\r
- { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[0]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[1]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[2]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[3]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[4]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[5]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[6]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[7]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[8]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[9]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[10]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[11]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[12]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[13]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[14]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[15]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[16]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[17]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[18]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[19]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[20]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[21]\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[22]\r
- EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved1[23]\r
-};\r
-\r
-//\r
-// Reference the table being generated to prevent the optimizer from removing the\r
-// data structure from the executable\r
-//\r
-VOID* CONST ReferenceAcpiTable = &Facs;\r
+++ /dev/null
-/** @file\r
-* Fixed ACPI Description Table (FADT)\r
-*\r
-* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include "ArmPlatform.h"\r
-#include <Library/AcpiLib.h>\r
-#include <IndustryStandard/Acpi.h>\r
-\r
-#ifdef ARM_JUNO_ACPI_5_0\r
-EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {\r
- ARM_ACPI_HEADER (\r
- EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
- EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE,\r
- EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION\r
- ),\r
-#else\r
-EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {\r
- ARM_ACPI_HEADER (\r
- EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
- EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE,\r
- EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION\r
- ),\r
-#endif\r
- 0, // UINT32 FirmwareCtrl\r
- 0, // UINT32 Dsdt\r
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0\r
- EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile\r
- 0, // UINT16 SciInt\r
- 0, // UINT32 SmiCmd\r
- 0, // UINT8 AcpiEnable\r
- 0, // UINT8 AcpiDisable\r
- 0, // UINT8 S4BiosReq\r
- 0, // UINT8 PstateCnt\r
- 0, // UINT32 Pm1aEvtBlk\r
- 0, // UINT32 Pm1bEvtBlk\r
- 0, // UINT32 Pm1aCntBlk\r
- 0, // UINT32 Pm1bCntBlk\r
- 0, // UINT32 Pm2CntBlk\r
- 0, // UINT32 PmTmrBlk\r
- 0, // UINT32 Gpe0Blk\r
- 0, // UINT32 Gpe1Blk\r
- 0, // UINT8 Pm1EvtLen\r
- 0, // UINT8 Pm1CntLen\r
- 0, // UINT8 Pm2CntLen\r
- 0, // UINT8 PmTmrLen\r
- 0, // UINT8 Gpe0BlkLen\r
- 0, // UINT8 Gpe1BlkLen\r
- 0, // UINT8 Gpe1Base\r
- 0, // UINT8 CstCnt\r
- 0, // UINT16 PLvl2Lat\r
- 0, // UINT16 PLvl3Lat\r
- 0, // UINT16 FlushSize\r
- 0, // UINT16 FlushStride\r
- 0, // UINT8 DutyOffset\r
- 0, // UINT8 DutyWidth\r
- 0, // UINT8 DayAlrm\r
- 0, // UINT8 MonAlrm\r
- 0, // UINT8 Century\r
- 0, // UINT16 IaPcBootArch\r
- 0, // UINT8 Reserved1\r
- EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags\r
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg\r
- 0, // UINT8 ResetValue\r
-#if ARM_JUNO_ACPI_5_0\r
- {EFI_ACPI_RESERVED_BYTE,EFI_ACPI_RESERVED_BYTE,EFI_ACPI_RESERVED_BYTE}, // UINT8 Reserved2[3]\r
-#else\r
- EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags\r
- EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision\r
-#endif\r
- 0, // UINT64 XFirmwareCtrl\r
- 0, // UINT64 XDsdt\r
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk\r
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk\r
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk\r
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk\r
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk\r
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk\r
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk\r
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk\r
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg\r
- NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg\r
-};\r
-\r
-//\r
-// Reference the table being generated to prevent the optimizer from removing the\r
-// data structure from the executable\r
-//\r
-VOID* CONST ReferenceAcpiTable = &Fadt;\r
+++ /dev/null
-/** @file\r
-* Generic Timer Description Table (GTDT)\r
-*\r
-* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include "ArmPlatform.h"\r
-#include <Library/AcpiLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <IndustryStandard/Acpi.h>\r
-\r
-#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT\r
-#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0\r
-#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE\r
-#define GTDT_GLOBAL_FLAGS_LEVEL 0\r
-\r
-// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer\r
-#ifdef SYSTEM_TIMER_BASE_ADDRESS\r
- #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)\r
-#else\r
- #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)\r
- #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF\r
-#endif\r
-\r
-#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE\r
-#define GTDT_TIMER_LEVEL_TRIGGERED 0\r
-#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY\r
-#define GTDT_TIMER_ACTIVE_HIGH 0\r
-\r
-#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)\r
-\r
-#ifdef ARM_JUNO_ACPI_5_0\r
- EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = {\r
- ARM_ACPI_HEADER(\r
- EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,\r
- EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE,\r
- EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION\r
- ),\r
- SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress\r
- GTDT_GLOBAL_FLAGS, // UINT32 GlobalFlags\r
- FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV\r
- GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags\r
- FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV\r
- GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags\r
- FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV\r
- GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags\r
- FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV\r
- GTDT_GTIMER_FLAGS // UINT32 NonSecurePL2TimerFlags\r
- };\r
-#else\r
- #pragma pack (1)\r
-\r
- typedef struct {\r
- EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;\r
- EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[JUNO_WATCHDOG_COUNT];\r
- } EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES;\r
-\r
- #pragma pack ()\r
-\r
- EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {\r
- {\r
- ARM_ACPI_HEADER(\r
- EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,\r
- EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE,\r
- EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION\r
- ),\r
- SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress\r
- 0, // UINT32 Reserved\r
- FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV\r
- GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags\r
- FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV\r
- GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags\r
- FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV\r
- GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags\r
- FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV\r
- GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags\r
- 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress\r
- JUNO_WATCHDOG_COUNT, // UINT32 PlatformTimerCount\r
- sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset\r
- },\r
- {\r
- EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(\r
- FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0),\r
- EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(\r
- FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER)\r
- }\r
- };\r
-#endif\r
-\r
-//\r
-// Reference the table being generated to prevent the optimizer from removing the\r
-// data structure from the executable\r
-//\r
-VOID* CONST ReferenceAcpiTable = &Gtdt;\r
+++ /dev/null
-/** @file\r
-* Multiple APIC Description Table (MADT)\r
-*\r
-* Copyright (c) 2012 - 2015, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include "ArmPlatform.h"\r
-#include <Library/AcpiLib.h>\r
-#include <Library/ArmLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <IndustryStandard/Acpi.h>\r
-\r
-//\r
-// Multiple APIC Description Table\r
-//\r
-#ifdef ARM_JUNO_ACPI_5_0\r
- #pragma pack (1)\r
-\r
- typedef struct {\r
- EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;\r
- EFI_ACPI_5_0_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)];\r
- EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;\r
- } EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE;\r
-\r
- #pragma pack ()\r
-\r
- EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {\r
- {\r
- ARM_ACPI_HEADER (\r
- EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,\r
- EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE,\r
- EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION\r
- ),\r
- //\r
- // MADT specific fields\r
- //\r
- 0, // LocalApicAddress\r
- 0, // Flags\r
- },\r
- {\r
- // Format: EFI_ACPI_5_0_GIC_STRUCTURE_INIT(GicId, AcpiCpuId, Flags, PmuIrq, GicBase)\r
- // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GIC Structure of\r
- // ACPI v5.0).\r
- // On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the\r
- // Trusted Firmware. When supported, we will need to code to dynamically change the ordering.\r
- // For now we leave CPU2 (A53-0) at the first position.\r
- // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses\r
- // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.\r
- EFI_ACPI_5_0_GIC_STRUCTURE_INIT(2, 0, EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-0\r
- EFI_ACPI_5_0_GIC_STRUCTURE_INIT(3, 1, EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-1\r
- EFI_ACPI_5_0_GIC_STRUCTURE_INIT(4, 2, EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-2\r
- EFI_ACPI_5_0_GIC_STRUCTURE_INIT(5, 3, EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-3\r
- EFI_ACPI_5_0_GIC_STRUCTURE_INIT(0, 4, EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A57-0\r
- EFI_ACPI_5_0_GIC_STRUCTURE_INIT(1, 5, EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase)) // A57-1\r
- },\r
- EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0)\r
- };\r
-#else\r
- #pragma pack (1)\r
-\r
- typedef struct {\r
- EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;\r
- EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)];\r
- EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;\r
- EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE MsiFrame;\r
- } EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE;\r
-\r
- #pragma pack ()\r
-\r
- EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {\r
- {\r
- ARM_ACPI_HEADER (\r
- EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,\r
- EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE,\r
- EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION\r
- ),\r
- //\r
- // MADT specific fields\r
- //\r
- 0, // LocalApicAddress\r
- 0, // Flags\r
- },\r
- {\r
- // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,\r
- // GsivId, GicRBase, Mpidr)\r
- // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of\r
- // ACPI v5.1).\r
- // On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the\r
- // Trusted Firmware. When supported, we will need to code to dynamically change the ordering.\r
- // For now we leave CPU2 (A53-0) at the first position.\r
- // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses\r
- // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.\r
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-0\r
- 2, 0, GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
- 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-1\r
- 3, 1, GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
- 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-2\r
- 4, 2, GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
- 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-3\r
- 5, 3, GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
- 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-0\r
- 0, 4, GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
- 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-1\r
- 1, 5, GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
- 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
- },\r
- EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0),\r
- // Format: EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(GicMsiFrameId, PhysicalBaseAddress, Flags, SPICount, SPIBase)\r
- EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, ARM_JUNO_GIV2M_MSI_SPI_COUNT, ARM_JUNO_GIV2M_MSI_SPI_BASE)\r
- };\r
-#endif\r
-\r
-//\r
-// Reference the table being generated to prevent the optimizer from removing the\r
-// data structure from the executable\r
-//\r
-VOID* CONST ReferenceAcpiTable = &Madt;\r
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