BaseTools: Add AArch64 ADR_PREL_LO21 and R_AARCH64_CONDBR19

 relocations

- ADR_PREL_LO21: support for loading a PC relative label offset.
- R_AARCH64_CONDBR19: support for conditional branch instruction (ELF64 code: 280).

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Yingke Liu <yingke.d.liu@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15745 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
index 606c7284f7378709ae8d6dd2a97e6de79943ea6a..3f9a11a4bcdf541121ab0010973c2edb0078157f 100644 (file)
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -1,7 +1,7 @@
 /** @file\r
 \r
 Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>\r
-Portions copyright (c) 2013, ARM Ltd. All rights reserved.<BR>\r
+Portions copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>\r
 \r
 This program and the accompanying materials are licensed and made available\r
 under the terms and conditions of the BSD License which accompanies this\r
@@ -690,6 +690,18 @@ WriteSections64 (
 \r
           switch (ELF_R_TYPE(Rel->r_info)) {\r
 \r
+          case R_AARCH64_ADR_PREL_LO21:\r
+            if  (Rel->r_addend != 0 ) { /* TODO */\r
+              Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_ADR_PREL_LO21 Need to fixup with addend!.");\r
+            }\r
+            break;\r
+\r
+          case R_AARCH64_CONDBR19:\r
+            if  (Rel->r_addend != 0 ) { /* TODO */\r
+              Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_CONDBR19 Need to fixup with addend!.");\r
+            }\r
+            break;\r
+\r
           case R_AARCH64_LD_PREL_LO19:\r
             if  (Rel->r_addend != 0 ) { /* TODO */\r
               Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_LD_PREL_LO19 Need to fixup with addend!.");\r
@@ -784,6 +796,12 @@ WriteRelocations64 (
           } else if (mEhdr->e_machine == EM_AARCH64) {\r
             // AArch64 GCC uses RELA relocation, so all relocations has to be fixed up. ARM32 uses REL.\r
             switch (ELF_R_TYPE(Rel->r_info)) {\r
+            case R_AARCH64_ADR_PREL_LO21:\r
+              break;\r
+\r
+            case R_AARCH64_CONDBR19:\r
+              break;\r
+\r
             case R_AARCH64_LD_PREL_LO19:\r
               break;\r
 \r