MdePkg/Include/IndustryStandard: Add PCI Express 4.0 header file

v3: LaneEqualizationControl is changed to be an array.

v2: The structure is updated to include all the fields defined
in the PCI-E specification.

The header includes Physical Layer PCI Express Extended Capability definitions
described in section 7.7.5 of PCI Express Base Specification rev. 4.0.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Felix Polyudov <felixp@ami.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>

diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h b/MdePkg/Include/IndustryStandard/PciExpress40.h
new file mode 100644 (file)
index 0000000..f806885
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/PciExpress40.h
@@ -0,0 +1,89 @@
+/** @file\r
+Support for the PCI Express 4.0 standard.\r
+\r
+This header file may not define all structures.  Please extend as required.\r
+\r
+Copyright (c) 2018, American Megatrends, Inc. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _PCIEXPRESS40_H_\r
+#define _PCIEXPRESS40_H_\r
+\r
+#include <IndustryStandard/PciExpress31.h>\r
+\r
+#pragma pack(1)\r
+\r
+/// The Physical Layer PCI Express Extended Capability definitions.\r
+///\r
+/// Based on section 7.7.5 of PCI Express Base Specification 4.0.\r
+///@{\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_ID    0x0026\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1  0x1\r
+\r
+// Register offsets from Physical Layer PCI-E Ext Cap Header\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET                         0x04\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET                              0x08\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET                               0x0C\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSET             0x10\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STATUS_OFFSET     0x14\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STATUS_OFFSET    0x18\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFSET            0x20\r
+\r
+typedef union {\r
+  struct {\r
+    UINT32 Reserved                  : 32; // Reserved bit 0:31\r
+  } Bits;\r
+  UINT32   Uint32;\r
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT32 Reserved                  : 32; // Reserved bit 0:31\r
+  } Bits;\r
+  UINT32   Uint32;\r
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT32 EqualizationComplete      : 1; // bit 0\r
+    UINT32 EqualizationPhase1Success : 1; // bit 1\r
+    UINT32 EqualizationPhase2Success : 1; // bit 2\r
+    UINT32 EqualizationPhase3Success : 1; // bit 3\r
+    UINT32 LinkEqualizationRequest   : 1; // bit 4\r
+    UINT32 Reserved                  : 27; // Reserved bit 5:31\r
+  } Bits;\r
+  UINT32   Uint32;\r
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3\r
+    UINT8 UpstreamPortTransmitterPreset   : 4; //bit 4..7\r
+  } Bits;\r
+  UINT8   Uint8;\r
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL;\r
+\r
+typedef struct {\r
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                      Header;\r
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES              Capablities;\r
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL                   Control;\r
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS                    Status;\r
+  UINT32                                                        LocalDataParityMismatchStatus;\r
+  UINT32                                                        FirstRetimerDataParityMismatchStatus;\r
+  UINT32                                                        SecondRetimerDataParityMismatchStatus;\r
+  UINT32                                                        Reserved;\r
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];\r
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;\r
+///@}\r
+\r
+#pragma pack()\r
+\r
+#endif\r