UefiCpuPkg/PiSmmCpu: Always set RW+P bit for page table by default

So that we can use write-protection for code later.

This is REPOST.
It includes the bug fix from "Paolo Bonzini" <pbonzini@redhat.com>:

  Title: fix generation of 32-bit PAE page tables

  "Bits 1 and 2 are reserved in 32-bit PAE Page Directory Pointer Table
  Entries (PDPTEs); see Table 4-8 in the SDM.  With VMX extended page
  tables, the processor notices and fails the VM entry as soon as CR0.PG
  is set to 1."

And thanks "Laszlo Ersek" <lersek@redhat.com> to validate the fix.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Signed-off-by: "Paolo Bonzini" <pbonzini@redhat.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Cc: "Fan, Jeff" <jeff.fan@intel.com>
Cc: "Kinney, Michael D" <michael.d.kinney@intel.com>
Cc: "Laszlo Ersek" <lersek@redhat.com>
Cc: "Paolo Bonzini" <pbonzini@redhat.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19067 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
index edebaabb47bd892eb0ca77e7c7982092b68daea6..5d299044c41b0083364035a41408b5811e7e41ed 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
@@ -60,7 +60,7 @@ SmmInitPageTable (
   if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r
     InitializeIDTSmmStackGuard ();\r
   }\r
-  return Gen4GPageTable (0);\r
+  return Gen4GPageTable (0, TRUE);\r
 }\r
 \r
 /**\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c
index 85756d0710cf19450c66062bbb6a9a0c4adf0475..767cb6908b391472fd7e839a70ca52dda78201c6 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c
@@ -24,7 +24,7 @@ InitSmmS3Cr3 (
   VOID\r
   )\r
 {\r
-  mSmmS3ResumeState->SmmS3Cr3 = Gen4GPageTable (0);\r
+  mSmmS3ResumeState->SmmS3Cr3 = Gen4GPageTable (0, TRUE);\r
 \r
   return ;\r
 }\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index 06ffc6dd86a830963eb9a431af1087d8bbd3acd1..620b0136c5cfc2447442674de2f42f9214d8faf2 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -732,12 +732,14 @@ APHandler (
   Create 4G PageTable in SMRAM.\r
 \r
   @param          ExtraPages       Additional page numbers besides for 4G memory\r
+  @param          Is32BitPageTable Whether the page table is 32-bit PAE\r
   @return         PageTable Address\r
 \r
 **/\r
 UINT32\r
 Gen4GPageTable (\r
-  IN      UINTN                     ExtraPages\r
+  IN      UINTN                     ExtraPages,\r
+  IN      BOOLEAN                   Is32BitPageTable\r
   )\r
 {\r
   VOID    *PageTable;\r
@@ -785,7 +787,7 @@ Gen4GPageTable (
   // Set Page Directory Pointers\r
   //\r
   for (Index = 0; Index < 4; Index++) {\r
-    Pte[Index] = (UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1) + IA32_PG_P;\r
+    Pte[Index] = (UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1) + (Is32BitPageTable ? IA32_PAE_PDPTE_ATTRIBUTE_BITS : PAGE_ATTRIBUTE_BITS);\r
   }\r
   Pte += EFI_PAGE_SIZE / sizeof (*Pte);\r
 \r
@@ -793,7 +795,7 @@ Gen4GPageTable (
   // Fill in Page Directory Entries\r
   //\r
   for (Index = 0; Index < EFI_PAGE_SIZE * 4 / sizeof (*Pte); Index++) {\r
-    Pte[Index] = (Index << 21) + IA32_PG_PS + IA32_PG_RW + IA32_PG_P;\r
+    Pte[Index] = (Index << 21) | IA32_PG_PS | PAGE_ATTRIBUTE_BITS;\r
   }\r
 \r
   if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r
@@ -802,7 +804,7 @@ Gen4GPageTable (
     Pdpte = (UINT64*)PageTable;\r
     for (PageIndex = Low2MBoundary; PageIndex <= High2MBoundary; PageIndex += SIZE_2MB) {\r
       Pte = (UINT64*)(UINTN)(Pdpte[BitFieldRead32 ((UINT32)PageIndex, 30, 31)] & ~(EFI_PAGE_SIZE - 1));\r
-      Pte[BitFieldRead32 ((UINT32)PageIndex, 21, 29)] = (UINT64)Pages + IA32_PG_RW + IA32_PG_P;\r
+      Pte[BitFieldRead32 ((UINT32)PageIndex, 21, 29)] = (UINT64)Pages | PAGE_ATTRIBUTE_BITS;\r
       //\r
       // Fill in Page Table Entries\r
       //\r
@@ -819,7 +821,7 @@ Gen4GPageTable (
             GuardPage = 0;\r
           }\r
         } else {\r
-          Pte[Index] = PageAddress + IA32_PG_RW + IA32_PG_P;\r
+          Pte[Index] = PageAddress | PAGE_ATTRIBUTE_BITS;\r
         }\r
         PageAddress+= EFI_PAGE_SIZE;\r
       }\r
@@ -886,7 +888,7 @@ SetCacheability (
       NewPageTable[Index] |= (UINT64)(Index << EFI_PAGE_SHIFT);\r
     }\r
 \r
-    PageTable[PTIndex] = ((UINTN)NewPageTableAddress & gPhyMask) | IA32_PG_P;\r
+    PageTable[PTIndex] = ((UINTN)NewPageTableAddress & gPhyMask) | PAGE_ATTRIBUTE_BITS;\r
   }\r
 \r
   ASSERT (PageTable[PTIndex] & IA32_PG_P);\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index f2a91655a33b85bdbf3c69b30252d172c877fe98..9920cd1d1e1a2738afe2cc07dc716b0cb800fe36 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -71,15 +71,24 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 ///\r
 #define IA32_PG_P                   BIT0\r
 #define IA32_PG_RW                  BIT1\r
+#define IA32_PG_U                   BIT2\r
 #define IA32_PG_WT                  BIT3\r
 #define IA32_PG_CD                  BIT4\r
 #define IA32_PG_A                   BIT5\r
+#define IA32_PG_D                   BIT6\r
 #define IA32_PG_PS                  BIT7\r
 #define IA32_PG_PAT_2M              BIT12\r
 #define IA32_PG_PAT_4K              IA32_PG_PS\r
 #define IA32_PG_PMNT                BIT62\r
 #define IA32_PG_NX                  BIT63\r
 \r
+#define PAGE_ATTRIBUTE_BITS         (IA32_PG_RW | IA32_PG_P)\r
+//\r
+// Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE\r
+// X64 PAE PDPTE does not have such restriction\r
+//\r
+#define IA32_PAE_PDPTE_ATTRIBUTE_BITS    (IA32_PG_P)\r
+\r
 //\r
 // Size of Task-State Segment defined in IA32 Manual\r
 //\r
@@ -364,12 +373,14 @@ extern IA32_DESCRIPTOR                     gcSmiInitGdtr;
   Create 4G PageTable in SMRAM.\r
 \r
   @param          ExtraPages       Additional page numbers besides for 4G memory\r
+  @param          Is32BitPageTable Whether the page table is 32-bit PAE\r
   @return         PageTable Address\r
 \r
 **/\r
 UINT32\r
 Gen4GPageTable (\r
-  IN      UINTN                     ExtraPages\r
+  IN      UINTN                     ExtraPages,\r
+  IN      BOOLEAN                   Is32BitPageTable\r
   );\r
 \r
 \r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
index ff4e28ec58e43572fcb0057e24d859ed102d0628..ec4ec9b067c5c6ace339731d7ba31d3299ab7fef 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
@@ -557,9 +557,9 @@ InitPaging (
 \r
           // Split it\r
           for (Level4 = 0; Level4 < SIZE_4KB / sizeof(*Pt); Level4++) {\r
-            Pt[Level4] = Address + ((Level4 << 12) | IA32_PG_RW | IA32_PG_P);\r
+            Pt[Level4] = Address + ((Level4 << 12) | PAGE_ATTRIBUTE_BITS);\r
           } // end for PT\r
-          *Pte = (UINTN)Pt | IA32_PG_RW | IA32_PG_P;\r
+          *Pte = (UINTN)Pt | PAGE_ATTRIBUTE_BITS;\r
         } // end if IsAddressSplit\r
       } // end for PTE\r
     } // end for PDE\r
@@ -608,7 +608,7 @@ InitPaging (
             //\r
             // Patch to remove Present flag and RW flag\r
             //\r
-            *Pte = *Pte & (INTN)(INT32)(~(IA32_PG_RW | IA32_PG_P));\r
+            *Pte = *Pte & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r
           }\r
           if (Nx && mXdSupported) {\r
             *Pte = *Pte | IA32_PG_NX;\r
@@ -621,7 +621,7 @@ InitPaging (
           }\r
           for (Level4 = 0; Level4 < SIZE_4KB / sizeof(*Pt); Level4++, Pt++) {\r
             if (!IsAddressValid (Address, &Nx)) {\r
-              *Pt = *Pt & (INTN)(INT32)(~(IA32_PG_RW | IA32_PG_P));\r
+              *Pt = *Pt & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r
             }\r
             if (Nx && mXdSupported) {\r
               *Pt = *Pt | IA32_PG_NX;\r
@@ -1244,7 +1244,7 @@ RestorePageTableBelow4G (
     //\r
     PageTable[PTIndex] = (PFAddress & ~((1ull << 21) - 1));\r
     PageTable[PTIndex] |= (UINT64)IA32_PG_PS;\r
-    PageTable[PTIndex] |= (UINT64)(IA32_PG_RW | IA32_PG_P);\r
+    PageTable[PTIndex] |= (UINT64)PAGE_ATTRIBUTE_BITS;\r
     if ((ErrorCode & IA32_PF_EC_ID) != 0) {\r
       PageTable[PTIndex] &= ~IA32_PG_NX;\r
     }\r
@@ -1277,7 +1277,7 @@ RestorePageTableBelow4G (
     // Set new entry\r
     //\r
     PageTable[PTIndex] = (PFAddress & ~((1ull << 12) - 1));\r
-    PageTable[PTIndex] |= (UINT64)(IA32_PG_RW | IA32_PG_P);\r
+    PageTable[PTIndex] |= (UINT64)PAGE_ATTRIBUTE_BITS;\r
     if ((ErrorCode & IA32_PF_EC_ID) != 0) {\r
       PageTable[PTIndex] &= ~IA32_PG_NX;\r
     }\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
index a7d790fd8aa044662ac40608c2b293a54fd95c05..5b11e5eb48a836a19c47512db0af4ddf6696a244 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
@@ -113,7 +113,7 @@ SmmInitPageTable (
   //\r
   // Generate PAE page table for the first 4GB memory space\r
   //\r
-  Pages = Gen4GPageTable (PAGE_TABLE_PAGES + 1);\r
+  Pages = Gen4GPageTable (PAGE_TABLE_PAGES + 1, FALSE);\r
 \r
   //\r
   // Set IA32_PG_PMNT bit to mask this entry\r
@@ -127,7 +127,7 @@ SmmInitPageTable (
   // Fill Page-Table-Level4 (PML4) entry\r
   //\r
   PTEntry = (UINT64*)(UINTN)(Pages - EFI_PAGES_TO_SIZE (PAGE_TABLE_PAGES + 1));\r
-  *PTEntry = Pages + IA32_PG_P;\r
+  *PTEntry = Pages + PAGE_ATTRIBUTE_BITS;\r
   ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry));\r
   //\r
   // Set sub-entries number\r
@@ -591,7 +591,7 @@ SmiDefaultPFHandler (
         //\r
         // If the entry is not present, allocate one page from page pool for it\r
         //\r
-        PageTable[PTIndex] = AllocPage () | IA32_PG_RW | IA32_PG_P;\r
+        PageTable[PTIndex] = AllocPage () | PAGE_ATTRIBUTE_BITS;\r
       } else {\r
         //\r
         // Save the upper entry address\r
@@ -621,7 +621,7 @@ SmiDefaultPFHandler (
     // Fill the new entry\r
     //\r
     PageTable[PTIndex] = (PFAddress & gPhyMask & ~((1ull << EndBit) - 1)) |\r
-                         PageAttribute | IA32_PG_A | IA32_PG_RW | IA32_PG_P;\r
+                         PageAttribute | IA32_PG_A | PAGE_ATTRIBUTE_BITS;\r
     if (UpperEntry != NULL) {\r
       SetSubEntriesNum (UpperEntry, GetSubEntriesNum (UpperEntry) + 1);\r
     }\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
index c4ec12debb1c444555564dde20b63ab077afa54b..79e23ef6476ea0a9e3bcb9713e8d7d04a499d397 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
@@ -45,13 +45,13 @@ InitSmmS3Cr3 (
   //\r
   // Generate PAE page table for the first 4GB memory space\r
   //\r
-  Pages = Gen4GPageTable (1);\r
+  Pages = Gen4GPageTable (1, FALSE);\r
 \r
   //\r
   // Fill Page-Table-Level4 (PML4) entry\r
   //\r
   PTEntry = (UINT64*)(UINTN)(Pages - EFI_PAGES_TO_SIZE (1));\r
-  *PTEntry = Pages + IA32_PG_P;\r
+  *PTEntry = Pages | PAGE_ATTRIBUTE_BITS;\r
   ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry));\r
 \r
   //\r
@@ -117,7 +117,7 @@ AcquirePage (
   //\r
   // Link & Record the current uplink\r
   //\r
-  *Uplink = Address | IA32_PG_P | IA32_PG_RW;\r
+  *Uplink = Address | PAGE_ATTRIBUTE_BITS;\r
   mPFPageUplink[mPFPageIndex] = Uplink;\r
 \r
   mPFPageIndex = (mPFPageIndex + 1) % MAX_PF_PAGE_COUNT;\r
@@ -242,9 +242,9 @@ RestorePageTableAbove4G (
       // PTE\r
       PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r
       for (Index = 0; Index < 512; Index++) {\r
-        PageTable[Index] = Address | IA32_PG_RW | IA32_PG_P;\r
+        PageTable[Index] = Address | PAGE_ATTRIBUTE_BITS;\r
         if (!IsAddressValid (Address, &Nx)) {\r
-          PageTable[Index] = PageTable[Index] & (INTN)(INT32)(~(IA32_PG_RW | IA32_PG_P));\r
+          PageTable[Index] = PageTable[Index] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r
         }\r
         if (Nx && mXdSupported) {\r
           PageTable[Index] = PageTable[Index] | IA32_PG_NX;\r
@@ -262,7 +262,7 @@ RestorePageTableAbove4G (
         //\r
         // Patch to remove present flag and rw flag.\r
         //\r
-        PageTable[PTIndex] = PageTable[PTIndex] & (INTN)(INT32)(~(IA32_PG_RW | IA32_PG_P));\r
+        PageTable[PTIndex] = PageTable[PTIndex] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r
       }\r
       //\r
       // Set XD bit to 1\r
@@ -289,7 +289,7 @@ RestorePageTableAbove4G (
   //\r
   // Add present flag or clear XD flag to make page fault handler succeed.\r
   //\r
-  PageTable[PTIndex] |= (UINT64)(IA32_PG_RW | IA32_PG_P);\r
+  PageTable[PTIndex] |= (UINT64)(PAGE_ATTRIBUTE_BITS);\r
   if ((ErrorCode & IA32_PF_EC_ID) != 0) {\r
     //\r
     // If page fault is caused by instruction fetch, clear XD bit in the entry.\r