MdeModulePkg/Universal/CapsulePei: Add support for PCD PcdPteMemoryEncryptionAddressO...

This PCD holds the address mask for page table entries when memory
encryption is enabled on AMD processors supporting the Secure Encrypted
Virtualization (SEV) feature.

The mask is applied when 4GB tables are created (UefiCapsule.c), and when
the tables are expanded on-demand by page-faults above 4GB's (X64Entry.c).

Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>

diff --git a/MdeModulePkg/Universal/CapsulePei/CapsulePei.inf b/MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
index d2ca0d06912c35103c5586d76f60153023a64a82..c54bc21a95a8ff9f6df909ea75d7d72aedbb2fcb 100644 (file)
--- a/MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
+++ b/MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
@@ -7,6 +7,7 @@
 #  buffer overflow, integer overflow.\r
 #\r
 # Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
 #  buffer overflow, integer overflow.\r
 #\r
 # Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r

+# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r

 #\r
 # This program and the accompanying materials\r
 # are licensed and made available under the terms and conditions\r
 #\r
 # This program and the accompanying materials\r
 # are licensed and made available under the terms and conditions\r


@@ -76,6 +77,7 @@
 [Pcd.IA32]\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleCoalesceFile     ## SOMETIMES_CONSUMES\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable          ## SOMETIMES_CONSUMES\r
 [Pcd.IA32]\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleCoalesceFile     ## SOMETIMES_CONSUMES\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable          ## SOMETIMES_CONSUMES\r

+  gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask    ## CONSUMES\r

 \r
 [FeaturePcd.IA32]\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode  ## CONSUMES\r
 \r
 [FeaturePcd.IA32]\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode  ## CONSUMES\r

diff --git a/MdeModulePkg/Universal/CapsulePei/Common/CommonHeader.h b/MdeModulePkg/Universal/CapsulePei/Common/CommonHeader.h
index 7298874f9e629e92d89aca56d3d4d45ed4f847a5..cac444204b6e4f4c1fcabd67826acb9f097a98b4 100644 (file)
--- a/MdeModulePkg/Universal/CapsulePei/Common/CommonHeader.h
+++ b/MdeModulePkg/Universal/CapsulePei/Common/CommonHeader.h
@@ -2,6 +2,8 @@
   Common header file.\r
 \r
 Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.<BR>\r
   Common header file.\r
 \r
 Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.<BR>\r

+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+\r

 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r


@@ -20,6 +22,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 //\r
 #define EXTRA_PAGE_TABLE_PAGES      8\r
 \r
 //\r
 #define EXTRA_PAGE_TABLE_PAGES      8\r
 \r

+#define PAGING_1G_ADDRESS_MASK_64   0x000FFFFFC0000000ull\r
+\r

 //\r
 // This capsule PEIM puts its private data at the start of the\r
 // coalesced capsule. Here's the structure definition.\r
 //\r
 // This capsule PEIM puts its private data at the start of the\r
 // coalesced capsule. Here's the structure definition.\r


@@ -60,6 +64,7 @@ typedef struct {
   EFI_PHYSICAL_ADDRESS  MemoryBase64Ptr;\r
   EFI_PHYSICAL_ADDRESS  MemorySize64Ptr;\r
   BOOLEAN               Page1GSupport;\r
   EFI_PHYSICAL_ADDRESS  MemoryBase64Ptr;\r
   EFI_PHYSICAL_ADDRESS  MemorySize64Ptr;\r
   BOOLEAN               Page1GSupport;\r

+  UINT64                AddressEncMask;\r

 } SWITCH_32_TO_64_CONTEXT;\r
 \r
 typedef struct {\r
 } SWITCH_32_TO_64_CONTEXT;\r
 \r
 typedef struct {\r

diff --git a/MdeModulePkg/Universal/CapsulePei/UefiCapsule.c b/MdeModulePkg/Universal/CapsulePei/UefiCapsule.c
index 9ac9d228d13cc27b5459711d9803dfa240c63bee..34b095ad184671a32e38929b870870d92d0ed8d0 100644 (file)
--- a/MdeModulePkg/Universal/CapsulePei/UefiCapsule.c
+++ b/MdeModulePkg/Universal/CapsulePei/UefiCapsule.c
@@ -2,6 +2,7 @@
   Capsule update PEIM for UEFI2.0\r
 \r
 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
   Capsule update PEIM for UEFI2.0\r
 \r
 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r

+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r

 \r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions\r
 \r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions\r


@@ -41,6 +42,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR mGdt = {
   (UINTN) mGdtEntries\r
   };\r
 \r
   (UINTN) mGdtEntries\r
   };\r
 \r

+\r

 /**\r
   The function will check if 1G page is supported.\r
 \r
 /**\r
   The function will check if 1G page is supported.\r
 \r


@@ -145,6 +147,12 @@ Create4GPageTables (
   PAGE_TABLE_ENTRY                              *PageDirectoryEntry;\r
   UINTN                                         BigPageAddress;\r
   PAGE_TABLE_1G_ENTRY                           *PageDirectory1GEntry;\r
   PAGE_TABLE_ENTRY                              *PageDirectoryEntry;\r
   UINTN                                         BigPageAddress;\r
   PAGE_TABLE_1G_ENTRY                           *PageDirectory1GEntry;\r

+  UINT64                                        AddressEncMask;\r
+\r
+  //\r
+  // Make sure AddressEncMask is contained to smallest supported address field.\r
+  //\r
+  AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r

 \r
   //\r
   // Create 4G page table by default,\r
 \r
   //\r
   // Create 4G page table by default,\r


@@ -187,7 +195,7 @@ Create4GPageTables (
     //\r
     // Make a PML4 Entry\r
     //\r
     //\r
     // Make a PML4 Entry\r
     //\r

-    PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry;\r
+    PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry | AddressEncMask;\r

     PageMapLevel4Entry->Bits.ReadWrite = 1;\r
     PageMapLevel4Entry->Bits.Present = 1;\r
 \r
     PageMapLevel4Entry->Bits.ReadWrite = 1;\r
     PageMapLevel4Entry->Bits.Present = 1;\r
 \r


@@ -198,7 +206,7 @@ Create4GPageTables (
         //\r
         // Fill in the Page Directory entries\r
         //\r
         //\r
         // Fill in the Page Directory entries\r
         //\r

-        PageDirectory1GEntry->Uint64 = (UINT64)PageAddress;\r
+        PageDirectory1GEntry->Uint64 = (UINT64)PageAddress | AddressEncMask;\r

         PageDirectory1GEntry->Bits.ReadWrite = 1;\r
         PageDirectory1GEntry->Bits.Present = 1;\r
         PageDirectory1GEntry->Bits.MustBe1 = 1;\r
         PageDirectory1GEntry->Bits.ReadWrite = 1;\r
         PageDirectory1GEntry->Bits.Present = 1;\r
         PageDirectory1GEntry->Bits.MustBe1 = 1;\r


@@ -215,7 +223,7 @@ Create4GPageTables (
         //\r
         // Fill in a Page Directory Pointer Entries\r
         //\r
         //\r
         // Fill in a Page Directory Pointer Entries\r
         //\r

-        PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry;\r
+        PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry | AddressEncMask;\r

         PageDirectoryPointerEntry->Bits.ReadWrite = 1;\r
         PageDirectoryPointerEntry->Bits.Present = 1;\r
 \r
         PageDirectoryPointerEntry->Bits.ReadWrite = 1;\r
         PageDirectoryPointerEntry->Bits.Present = 1;\r
 \r


@@ -223,7 +231,7 @@ Create4GPageTables (
           //\r
           // Fill in the Page Directory entries\r
           //\r
           //\r
           // Fill in the Page Directory entries\r
           //\r

-          PageDirectoryEntry->Uint64 = (UINT64)PageAddress;\r
+          PageDirectoryEntry->Uint64 = (UINT64)PageAddress | AddressEncMask;\r

           PageDirectoryEntry->Bits.ReadWrite = 1;\r
           PageDirectoryEntry->Bits.Present = 1;\r
           PageDirectoryEntry->Bits.MustBe1 = 1;\r
           PageDirectoryEntry->Bits.ReadWrite = 1;\r
           PageDirectoryEntry->Bits.Present = 1;\r
           PageDirectoryEntry->Bits.MustBe1 = 1;\r


@@ -443,6 +451,7 @@ ModeSwitch (
   Context.MemoryBase64Ptr       = (EFI_PHYSICAL_ADDRESS)(UINTN)&MemoryBase64;\r
   Context.MemorySize64Ptr       = (EFI_PHYSICAL_ADDRESS)(UINTN)&MemorySize64;\r
   Context.Page1GSupport         = Page1GSupport;\r
   Context.MemoryBase64Ptr       = (EFI_PHYSICAL_ADDRESS)(UINTN)&MemoryBase64;\r
   Context.MemorySize64Ptr       = (EFI_PHYSICAL_ADDRESS)(UINTN)&MemorySize64;\r
   Context.Page1GSupport         = Page1GSupport;\r

+  Context.AddressEncMask        = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r

 \r
   //\r
   // Prepare data for return back\r
 \r
   //\r
   // Prepare data for return back\r

diff --git a/MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c b/MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c
index 5ad95d215176bbe0acc027bd80bab165ebe0cc78..e1871c3c2ad585f89924f0471fccefcf0fec7d37 100644 (file)
--- a/MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c
+++ b/MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c
@@ -2,6 +2,8 @@
   The X64 entrypoint is used to process capsule in long mode.\r
 \r
 Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.<BR>\r
   The X64 entrypoint is used to process capsule in long mode.\r
 \r
 Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.<BR>\r

+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+\r

 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r


@@ -29,6 +31,7 @@ typedef struct _PAGE_FAULT_CONTEXT {
   UINT64                        PhyMask;\r
   UINTN                         PageFaultBuffer;\r
   UINTN                         PageFaultIndex;\r
   UINT64                        PhyMask;\r
   UINTN                         PageFaultBuffer;\r
   UINTN                         PageFaultIndex;\r

+  UINT64                        AddressEncMask;\r

   //\r
   // Store the uplink information for each page being used.\r
   //\r
   //\r
   // Store the uplink information for each page being used.\r
   //\r


@@ -114,21 +117,25 @@ AcquirePage (
   )\r
 {\r
   UINTN             Address;\r
   )\r
 {\r
   UINTN             Address;\r

+  UINT64            AddressEncMask;\r

 \r
   Address = PageFaultContext->PageFaultBuffer + EFI_PAGES_TO_SIZE (PageFaultContext->PageFaultIndex);\r
   ZeroMem ((VOID *) Address, EFI_PAGES_TO_SIZE (1));\r
 \r
 \r
   Address = PageFaultContext->PageFaultBuffer + EFI_PAGES_TO_SIZE (PageFaultContext->PageFaultIndex);\r
   ZeroMem ((VOID *) Address, EFI_PAGES_TO_SIZE (1));\r
 \r

+  AddressEncMask = PageFaultContext->AddressEncMask;\r
+\r

   //\r
   // Cut the previous uplink if it exists and wasn't overwritten.\r
   //\r
   //\r
   // Cut the previous uplink if it exists and wasn't overwritten.\r
   //\r

-  if ((PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] != NULL) && ((*PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] & PageFaultContext->PhyMask) == Address)) {\r
+  if ((PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] != NULL) &&\r
+     ((*PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] & ~AddressEncMask & PageFaultContext->PhyMask) == Address)) {\r

     *PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] = 0;\r
   }\r
 \r
   //\r
   // Link & Record the current uplink.\r
   //\r
     *PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] = 0;\r
   }\r
 \r
   //\r
   // Link & Record the current uplink.\r
   //\r

-  *Uplink = Address | IA32_PG_P | IA32_PG_RW;\r
+  *Uplink = Address | AddressEncMask | IA32_PG_P | IA32_PG_RW;\r

   PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] = Uplink;\r
 \r
   PageFaultContext->PageFaultIndex = (PageFaultContext->PageFaultIndex + 1) % EXTRA_PAGE_TABLE_PAGES;\r
   PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] = Uplink;\r
 \r
   PageFaultContext->PageFaultIndex = (PageFaultContext->PageFaultIndex + 1) % EXTRA_PAGE_TABLE_PAGES;\r


@@ -153,6 +160,7 @@ PageFaultHandler (
   UINT64                    *PageTable;\r
   UINT64                    PFAddress;\r
   UINTN                     PTIndex;\r
   UINT64                    *PageTable;\r
   UINT64                    PFAddress;\r
   UINTN                     PTIndex;\r

+  UINT64                    AddressEncMask;\r

 \r
   //\r
   // Get the IDT Descriptor.\r
 \r
   //\r
   // Get the IDT Descriptor.\r


@@ -163,6 +171,7 @@ PageFaultHandler (
   //\r
   PageFaultContext = (PAGE_FAULT_CONTEXT *) (UINTN) (Idtr.Base - sizeof (PAGE_FAULT_CONTEXT));\r
   PhyMask = PageFaultContext->PhyMask;\r
   //\r
   PageFaultContext = (PAGE_FAULT_CONTEXT *) (UINTN) (Idtr.Base - sizeof (PAGE_FAULT_CONTEXT));\r
   PhyMask = PageFaultContext->PhyMask;\r

+  AddressEncMask = PageFaultContext->AddressEncMask;\r

 \r
   PFAddress = AsmReadCr2 ();\r
   DEBUG ((EFI_D_ERROR, "CapsuleX64 - PageFaultHandler: Cr2 - %lx\n", PFAddress));\r
 \r
   PFAddress = AsmReadCr2 ();\r
   DEBUG ((EFI_D_ERROR, "CapsuleX64 - PageFaultHandler: Cr2 - %lx\n", PFAddress));\r


@@ -179,19 +188,19 @@ PageFaultHandler (
   if ((PageTable[PTIndex] & IA32_PG_P) == 0) {\r
     AcquirePage (PageFaultContext, &PageTable[PTIndex]);\r
   }\r
   if ((PageTable[PTIndex] & IA32_PG_P) == 0) {\r
     AcquirePage (PageFaultContext, &PageTable[PTIndex]);\r
   }\r

-  PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PhyMask);\r
+  PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~AddressEncMask & PhyMask);\r

   PTIndex = BitFieldRead64 (PFAddress, 30, 38);\r
   // PDPTE\r
   if (PageFaultContext->Page1GSupport) {\r
   PTIndex = BitFieldRead64 (PFAddress, 30, 38);\r
   // PDPTE\r
   if (PageFaultContext->Page1GSupport) {\r

-    PageTable[PTIndex] = (PFAddress & ~((1ull << 30) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;\r
+    PageTable[PTIndex] = ((PFAddress | AddressEncMask) & ~((1ull << 30) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;\r

   } else {\r
     if ((PageTable[PTIndex] & IA32_PG_P) == 0) {\r
       AcquirePage (PageFaultContext, &PageTable[PTIndex]);\r
     }\r
   } else {\r
     if ((PageTable[PTIndex] & IA32_PG_P) == 0) {\r
       AcquirePage (PageFaultContext, &PageTable[PTIndex]);\r
     }\r

-    PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PhyMask);\r
+    PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~AddressEncMask & PhyMask);\r

     PTIndex = BitFieldRead64 (PFAddress, 21, 29);\r
     // PD\r
     PTIndex = BitFieldRead64 (PFAddress, 21, 29);\r
     // PD\r

-    PageTable[PTIndex] = (PFAddress & ~((1ull << 21) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;\r
+    PageTable[PTIndex] = ((PFAddress | AddressEncMask) & ~((1ull << 21) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;\r

   }\r
 \r
   return NULL;\r
   }\r
 \r
   return NULL;\r


@@ -244,6 +253,7 @@ _ModuleEntryPoint (
   // Hook page fault handler to handle >4G request.\r
   //\r
   PageFaultIdtTable.PageFaultContext.Page1GSupport = EntrypointContext->Page1GSupport;\r
   // Hook page fault handler to handle >4G request.\r
   //\r
   PageFaultIdtTable.PageFaultContext.Page1GSupport = EntrypointContext->Page1GSupport;\r

+  PageFaultIdtTable.PageFaultContext.AddressEncMask = EntrypointContext->AddressEncMask;\r

   IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) (X64Idtr.Base + (14 * sizeof (IA32_IDT_GATE_DESCRIPTOR)));\r
   HookPageFaultHandler (IdtEntry, &(PageFaultIdtTable.PageFaultContext));\r
 \r
   IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) (X64Idtr.Base + (14 * sizeof (IA32_IDT_GATE_DESCRIPTOR)));\r
   HookPageFaultHandler (IdtEntry, &(PageFaultIdtTable.PageFaultContext));\r
 \r


@@ -298,4 +308,4 @@ _ModuleEntryPoint (
   //\r
   ASSERT (FALSE);\r
   return EFI_SUCCESS;\r
   //\r
   ASSERT (FALSE);\r
   return EFI_SUCCESS;\r

-}
\ No newline at end of file
+}\r