CorebootModulePkg/PciHostBridgeLib: Fix PCI 64bit memory BAR size issue
authorMaurice Ma <maurice.ma@intel.com>
Thu, 26 May 2016 22:13:23 +0000 (15:13 -0700)
committerMaurice Ma <maurice.ma@intel.com>
Fri, 27 May 2016 21:28:37 +0000 (14:28 -0700)
The current PCI 64bit memory BAR size calculation in PciHostBridgeLib
assumes all 32 bits in the upper BAR are fully writable. However,
platform might only support partial address programming, such as 40bit
PCI BAR address. In this case the complement cannot be used for size
calculation.  Instead, the lowest non-zero bit should be used for BAR
size calculation.

Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c

index a95ffca..0f1c8cb 100644 (file)
@@ -193,6 +193,7 @@ PcatPciRootBridgeParseBars (
   UINT32                            UpperValue;\r
   UINT64                            Mask;\r
   UINTN                             Offset;\r
+  UINTN                             LowBit;\r
   UINT64                            Base;\r
   UINT64                            Length;\r
   UINT64                            Limit;\r
@@ -262,7 +263,10 @@ PcatPciRootBridgeParseBars (
 \r
           Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32);\r
           Length = Length | LShiftU64 ((UINT64) UpperValue, 32);\r
-          Length = (~Length) + 1;\r
+          if (Length != 0) {\r
+            LowBit = LowBitSet64 (Length);\r
+            Length = LShiftU64 (1ULL, LowBit);\r
+          }\r
 \r
           if ((Value & BIT3) == BIT3) {\r
             MemAperture = PMemAbove4G;\r