MdePkg/Register: Add register definition header files for RISC-V

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Add register definitions and access routines for RISC-V. These
headers are leveraged from opensbi repo.

Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>

diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
new file mode 100644 (file)
index 0000000..5c2989b
--- /dev/null
+++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
@@ -0,0 +1,119 @@
+/** @file\r
+  RISC-V CSR encodings\r
+\r
+  Copyright (c) 2019, Western Digital Corporation or its affiliates. All rights reserved.<BR>\r
+  Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#ifndef RISCV_ENCODING_H_\r
+#define RISCV_ENCODING_H_\r
+\r
+#define MSTATUS_SIE         0x00000002UL\r
+#define MSTATUS_MIE         0x00000008UL\r
+#define MSTATUS_SPIE_SHIFT  5\r
+#define MSTATUS_SPIE        (1UL << MSTATUS_SPIE_SHIFT)\r
+#define MSTATUS_UBE         0x00000040UL\r
+#define MSTATUS_MPIE        0x00000080UL\r
+#define MSTATUS_SPP_SHIFT   8\r
+#define MSTATUS_SPP         (1UL << MSTATUS_SPP_SHIFT)\r
+#define MSTATUS_MPP_SHIFT   11\r
+#define MSTATUS_MPP         (3UL << MSTATUS_MPP_SHIFT)\r
+\r
+#define SSTATUS_SIE         MSTATUS_SIE\r
+#define SSTATUS_SPIE_SHIFT  MSTATUS_SPIE_SHIFT\r
+#define SSTATUS_SPIE        MSTATUS_SPIE\r
+#define SSTATUS_SPP_SHIFT   MSTATUS_SPP_SHIFT\r
+#define SSTATUS_SPP         MSTATUS_SPP\r
+\r
+#define IRQ_S_SOFT    1\r
+#define IRQ_VS_SOFT   2\r
+#define IRQ_M_SOFT    3\r
+#define IRQ_S_TIMER   5\r
+#define IRQ_VS_TIMER  6\r
+#define IRQ_M_TIMER   7\r
+#define IRQ_S_EXT     9\r
+#define IRQ_VS_EXT    10\r
+#define IRQ_M_EXT     11\r
+#define IRQ_S_GEXT    12\r
+#define IRQ_PMU_OVF   13\r
+\r
+#define MIP_SSIP    (1UL << IRQ_S_SOFT)\r
+#define MIP_VSSIP   (1UL << IRQ_VS_SOFT)\r
+#define MIP_MSIP    (1UL << IRQ_M_SOFT)\r
+#define MIP_STIP    (1UL << IRQ_S_TIMER)\r
+#define MIP_VSTIP   (1UL << IRQ_VS_TIMER)\r
+#define MIP_MTIP    (1UL << IRQ_M_TIMER)\r
+#define MIP_SEIP    (1UL << IRQ_S_EXT)\r
+#define MIP_VSEIP   (1UL << IRQ_VS_EXT)\r
+#define MIP_MEIP    (1UL << IRQ_M_EXT)\r
+#define MIP_SGEIP   (1UL << IRQ_S_GEXT)\r
+#define MIP_LCOFIP  (1UL << IRQ_PMU_OVF)\r
+\r
+#define SIP_SSIP  MIP_SSIP\r
+#define SIP_STIP  MIP_STIP\r
+\r
+#define PRV_U  0UL\r
+#define PRV_S  1UL\r
+#define PRV_M  3UL\r
+\r
+#define SATP64_MODE  0xF000000000000000ULL\r
+#define SATP64_ASID  0x0FFFF00000000000ULL\r
+#define SATP64_PPN   0x00000FFFFFFFFFFFULL\r
+\r
+#define SATP_MODE_OFF   0UL\r
+#define SATP_MODE_SV32  1UL\r
+#define SATP_MODE_SV39  8UL\r
+#define SATP_MODE_SV48  9UL\r
+#define SATP_MODE_SV57  10UL\r
+#define SATP_MODE_SV64  11UL\r
+\r
+#define SATP_MODE  SATP64_MODE\r
+\r
+/* User Counters/Timers */\r
+#define CSR_CYCLE  0xc00\r
+#define CSR_TIME   0xc01\r
+\r
+/* Supervisor Trap Setup */\r
+#define CSR_SSTATUS  0x100\r
+#define CSR_SEDELEG  0x102\r
+#define CSR_SIDELEG  0x103\r
+#define CSR_SIE      0x104\r
+#define CSR_STVEC    0x105\r
+\r
+/* Supervisor Configuration */\r
+#define CSR_SENVCFG  0x10a\r
+\r
+/* Supervisor Trap Handling */\r
+#define CSR_SSCRATCH  0x140\r
+#define CSR_SEPC      0x141\r
+#define CSR_SCAUSE    0x142\r
+#define CSR_STVAL     0x143\r
+#define CSR_SIP       0x144\r
+\r
+/* Supervisor Protection and Translation */\r
+#define CSR_SATP  0x180\r
+\r
+/* Trap/Exception Causes */\r
+#define CAUSE_MISALIGNED_FETCH          0x0\r
+#define CAUSE_FETCH_ACCESS              0x1\r
+#define CAUSE_ILLEGAL_INSTRUCTION       0x2\r
+#define CAUSE_BREAKPOINT                0x3\r
+#define CAUSE_MISALIGNED_LOAD           0x4\r
+#define CAUSE_LOAD_ACCESS               0x5\r
+#define CAUSE_MISALIGNED_STORE          0x6\r
+#define CAUSE_STORE_ACCESS              0x7\r
+#define CAUSE_USER_ECALL                0x8\r
+#define CAUSE_SUPERVISOR_ECALL          0x9\r
+#define CAUSE_VIRTUAL_SUPERVISOR_ECALL  0xa\r
+#define CAUSE_MACHINE_ECALL             0xb\r
+#define CAUSE_FETCH_PAGE_FAULT          0xc\r
+#define CAUSE_LOAD_PAGE_FAULT           0xd\r
+#define CAUSE_STORE_PAGE_FAULT          0xf\r
+#define CAUSE_FETCH_GUEST_PAGE_FAULT    0x14\r
+#define CAUSE_LOAD_GUEST_PAGE_FAULT     0x15\r
+#define CAUSE_VIRTUAL_INST_FAULT        0x16\r
+#define CAUSE_STORE_GUEST_PAGE_FAULT    0x17\r
+\r
+#endif\r

diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
new file mode 100644 (file)
index 0000000..ee5c2ba
--- /dev/null
+++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
@@ -0,0 +1,25 @@
+/** @file\r
+  RISC-V package definitions.\r
+\r
+  Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
+\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#ifndef RISCV_IMPL_H_\r
+#define RISCV_IMPL_H_\r
+\r
+#include <Register/RiscV64/RiscVEncoding.h>\r
+\r
+#define _ASM_FUNC(Name, Section)    \\r
+  .global   Name                  ; \\r
+  .section  #Section, "ax"        ; \\r
+  .type     Name, %function       ; \\r
+  .p2align  2                     ; \\r
+  Name:\r
+\r
+#define ASM_FUNC(Name)  _ASM_FUNC(ASM_PFX(Name), .text. ## Name)\r
+#define RISCV_TIMER_COMPARE_BITS  32\r
+\r
+#endif\r