Msr = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE);\r
AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE is defined as IA32_MONITOR_FILTER_LINE_SIZE in SDM.\r
**/\r
#define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x00000006\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON);\r
AsmWriteMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON, Msr.Uint64);\r
@endcode\r
+ @note MSR_PENTIUM_4_EBC_HARD_POWERON is defined as MSR_EBC_HARD_POWERON in SDM.\r
**/\r
#define MSR_PENTIUM_4_EBC_HARD_POWERON 0x0000002A\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON);\r
AsmWriteMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON, Msr.Uint64);\r
@endcode\r
+ @note MSR_PENTIUM_4_EBC_SOFT_POWERON is defined as MSR_EBC_SOFT_POWERON in SDM.\r
**/\r
#define MSR_PENTIUM_4_EBC_SOFT_POWERON 0x0000002B\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID);\r
@endcode\r
+ @note MSR_PENTIUM_4_EBC_FREQUENCY_ID is defined as MSR_EBC_FREQUENCY_ID in SDM.\r
**/\r
#define MSR_PENTIUM_4_EBC_FREQUENCY_ID 0x0000002C\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID_1);\r
@endcode\r
+ @note MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 is defined as MSR_EBC_FREQUENCY_ID_1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 0x0000002C\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RAX);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RAX, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MCG_RAX is defined as MSR_MCG_RAX in SDM.\r
**/\r
#define MSR_PENTIUM_4_MCG_RAX 0x00000180\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBX);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBX, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MCG_RBX is defined as MSR_MCG_RBX in SDM.\r
**/\r
#define MSR_PENTIUM_4_MCG_RBX 0x00000181\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RCX);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RCX, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MCG_RCX is defined as MSR_MCG_RCX in SDM.\r
**/\r
#define MSR_PENTIUM_4_MCG_RCX 0x00000182\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDX);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDX, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MCG_RDX is defined as MSR_MCG_RDX in SDM.\r
**/\r
#define MSR_PENTIUM_4_MCG_RDX 0x00000183\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSI);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSI, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MCG_RSI is defined as MSR_MCG_RSI in SDM.\r
**/\r
#define MSR_PENTIUM_4_MCG_RSI 0x00000184\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDI);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDI, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MCG_RDI is defined as MSR_MCG_RDI in SDM.\r
**/\r
#define MSR_PENTIUM_4_MCG_RDI 0x00000185\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBP);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBP, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MCG_RBP is defined as MSR_MCG_RBP in SDM.\r
**/\r
#define MSR_PENTIUM_4_MCG_RBP 0x00000186\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSP);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSP, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MCG_RSP is defined as MSR_MCG_RSP in SDM.\r
**/\r
#define MSR_PENTIUM_4_MCG_RSP 0x00000187\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RFLAGS);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RFLAGS, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MCG_RFLAGS is defined as MSR_MCG_RFLAGS in SDM.\r
**/\r
#define MSR_PENTIUM_4_MCG_RFLAGS 0x00000188\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RIP);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RIP, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MCG_RIP is defined as MSR_MCG_RIP in SDM.\r
**/\r
#define MSR_PENTIUM_4_MCG_RIP 0x00000189\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_MCG_MISC);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_MISC, Msr.Uint64);\r
@endcode\r
+ @note MSR_PENTIUM_4_MCG_MISC is defined as MSR_MCG_MISC in SDM.\r
**/\r
#define MSR_PENTIUM_4_MCG_MISC 0x0000018A\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R8);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R8, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MCG_R8 is defined as MSR_MCG_R8 in SDM.\r
**/\r
#define MSR_PENTIUM_4_MCG_R8 0x00000190\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R9);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R9, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MCG_R9 is defined as MSR_MCG_R9 in SDM.\r
**/\r
#define MSR_PENTIUM_4_MCG_R9 0x00000191\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R10);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R10, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MCG_R10 is defined as MSR_MCG_R10 in SDM.\r
**/\r
#define MSR_PENTIUM_4_MCG_R10 0x00000192\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R11);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R11, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MCG_R11 is defined as MSR_MCG_R11 in SDM.\r
**/\r
#define MSR_PENTIUM_4_MCG_R11 0x00000193\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R12);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R12, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MCG_R12 is defined as MSR_MCG_R12 in SDM.\r
**/\r
#define MSR_PENTIUM_4_MCG_R12 0x00000194\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R13);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R13, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MCG_R13 is defined as MSR_MCG_R13 in SDM.\r
**/\r
#define MSR_PENTIUM_4_MCG_R13 0x00000195\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R14);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R14, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MCG_R14 is defined as MSR_MCG_R14 in SDM.\r
**/\r
#define MSR_PENTIUM_4_MCG_R14 0x00000196\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R15);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R15, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MCG_R15 is defined as MSR_MCG_R15 in SDM.\r
**/\r
#define MSR_PENTIUM_4_MCG_R15 0x00000197\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_THERM2_CTL);\r
AsmWriteMsr64 (MSR_PENTIUM_4_THERM2_CTL, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
**/\r
#define MSR_PENTIUM_4_THERM2_CTL 0x0000019D\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE);\r
AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE, Msr.Uint64);\r
@endcode\r
+ @note MSR_PENTIUM_4_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
#define MSR_PENTIUM_4_IA32_MISC_ENABLE 0x000001A0\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PLATFORM_BRV);\r
@endcode\r
+ @note MSR_PENTIUM_4_PLATFORM_BRV is defined as MSR_PLATFORM_BRV in SDM.\r
**/\r
#define MSR_PENTIUM_4_PLATFORM_BRV 0x000001A1\r
\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_FROM_LIP);\r
@endcode\r
+ @note MSR_PENTIUM_4_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
#define MSR_PENTIUM_4_LER_FROM_LIP 0x000001D7\r
\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_TO_LIP);\r
@endcode\r
+ @note MSR_PENTIUM_4_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
#define MSR_PENTIUM_4_LER_TO_LIP 0x000001D8\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_DEBUGCTLA);\r
AsmWriteMsr64 (MSR_PENTIUM_4_DEBUGCTLA, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_DEBUGCTLA is defined as MSR_DEBUGCTLA in SDM.\r
**/\r
#define MSR_PENTIUM_4_DEBUGCTLA 0x000001D9\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS);\r
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
#define MSR_PENTIUM_4_LASTBRANCH_TOS 0x000001DA\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.\r
@{\r
**/\r
#define MSR_PENTIUM_4_LASTBRANCH_0 0x000001DB\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_COUNTER0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_BPU_COUNTER0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_BPU_COUNTER0 is defined as MSR_BPU_COUNTER0 in SDM.\r
+ MSR_PENTIUM_4_BPU_COUNTER1 is defined as MSR_BPU_COUNTER1 in SDM.\r
+ MSR_PENTIUM_4_BPU_COUNTER2 is defined as MSR_BPU_COUNTER2 in SDM.\r
+ MSR_PENTIUM_4_BPU_COUNTER3 is defined as MSR_BPU_COUNTER3 in SDM.\r
@{\r
**/\r
#define MSR_PENTIUM_4_BPU_COUNTER0 0x00000300\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_COUNTER0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MS_COUNTER0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MS_COUNTER0 is defined as MSR_MS_COUNTER0 in SDM.\r
+ MSR_PENTIUM_4_MS_COUNTER1 is defined as MSR_MS_COUNTER1 in SDM.\r
+ MSR_PENTIUM_4_MS_COUNTER2 is defined as MSR_MS_COUNTER2 in SDM.\r
+ MSR_PENTIUM_4_MS_COUNTER3 is defined as MSR_MS_COUNTER3 in SDM.\r
@{\r
**/\r
#define MSR_PENTIUM_4_MS_COUNTER0 0x00000304\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_FLAME_COUNTER0 is defined as MSR_FLAME_COUNTER0 in SDM.\r
+ MSR_PENTIUM_4_FLAME_COUNTER1 is defined as MSR_FLAME_COUNTER1 in SDM.\r
+ MSR_PENTIUM_4_FLAME_COUNTER2 is defined as MSR_FLAME_COUNTER2 in SDM.\r
+ MSR_PENTIUM_4_FLAME_COUNTER3 is defined as MSR_FLAME_COUNTER3 in SDM.\r
@{\r
**/\r
#define MSR_PENTIUM_4_FLAME_COUNTER0 0x00000308\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_COUNTER0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_IQ_COUNTER0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_IQ_COUNTER0 is defined as MSR_IQ_COUNTER0 in SDM.\r
+ MSR_PENTIUM_4_IQ_COUNTER1 is defined as MSR_IQ_COUNTER1 in SDM.\r
+ MSR_PENTIUM_4_IQ_COUNTER2 is defined as MSR_IQ_COUNTER2 in SDM.\r
+ MSR_PENTIUM_4_IQ_COUNTER3 is defined as MSR_IQ_COUNTER3 in SDM.\r
+ MSR_PENTIUM_4_IQ_COUNTER4 is defined as MSR_IQ_COUNTER4 in SDM.\r
+ MSR_PENTIUM_4_IQ_COUNTER5 is defined as MSR_IQ_COUNTER5 in SDM.\r
@{\r
**/\r
#define MSR_PENTIUM_4_IQ_COUNTER0 0x0000030C\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_CCCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_BPU_CCCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_BPU_CCCR0 is defined as MSR_BPU_CCCR0 in SDM.\r
+ MSR_PENTIUM_4_BPU_CCCR1 is defined as MSR_BPU_CCCR1 in SDM.\r
+ MSR_PENTIUM_4_BPU_CCCR2 is defined as MSR_BPU_CCCR2 in SDM.\r
+ MSR_PENTIUM_4_BPU_CCCR3 is defined as MSR_BPU_CCCR3 in SDM.\r
@{\r
**/\r
#define MSR_PENTIUM_4_BPU_CCCR0 0x00000360\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_CCCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MS_CCCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MS_CCCR0 is defined as MSR_MS_CCCR0 in SDM.\r
+ MSR_PENTIUM_4_MS_CCCR1 is defined as MSR_MS_CCCR1 in SDM.\r
+ MSR_PENTIUM_4_MS_CCCR2 is defined as MSR_MS_CCCR2 in SDM.\r
+ MSR_PENTIUM_4_MS_CCCR3 is defined as MSR_MS_CCCR3 in SDM.\r
@{\r
**/\r
#define MSR_PENTIUM_4_MS_CCCR0 0x00000364\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_CCCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_CCCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_FLAME_CCCR0 is defined as MSR_FLAME_CCCR0 in SDM.\r
+ MSR_PENTIUM_4_FLAME_CCCR1 is defined as MSR_FLAME_CCCR1 in SDM.\r
+ MSR_PENTIUM_4_FLAME_CCCR2 is defined as MSR_FLAME_CCCR2 in SDM.\r
+ MSR_PENTIUM_4_FLAME_CCCR3 is defined as MSR_FLAME_CCCR3 in SDM.\r
@{\r
**/\r
#define MSR_PENTIUM_4_FLAME_CCCR0 0x00000368\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_CCCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_IQ_CCCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_IQ_CCCR0 is defined as MSR_IQ_CCCR0 in SDM.\r
+ MSR_PENTIUM_4_IQ_CCCR1 is defined as MSR_IQ_CCCR1 in SDM.\r
+ MSR_PENTIUM_4_IQ_CCCR2 is defined as MSR_IQ_CCCR2 in SDM.\r
+ MSR_PENTIUM_4_IQ_CCCR3 is defined as MSR_IQ_CCCR3 in SDM.\r
+ MSR_PENTIUM_4_IQ_CCCR4 is defined as MSR_IQ_CCCR4 in SDM.\r
+ MSR_PENTIUM_4_IQ_CCCR5 is defined as MSR_IQ_CCCR5 in SDM.\r
@{\r
**/\r
#define MSR_PENTIUM_4_IQ_CCCR0 0x0000036C\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_BSU_ESCR0 is defined as MSR_BSU_ESCR0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_BSU_ESCR0 0x000003A0\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_BSU_ESCR1 is defined as MSR_BSU_ESCR1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_BSU_ESCR1 0x000003A1\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_FSB_ESCR0 is defined as MSR_FSB_ESCR0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_FSB_ESCR0 0x000003A2\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_FSB_ESCR1 is defined as MSR_FSB_ESCR1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_FSB_ESCR1 0x000003A3\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_FIRM_ESCR0 is defined as MSR_FIRM_ESCR0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_FIRM_ESCR0 0x000003A4\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_FIRM_ESCR1 is defined as MSR_FIRM_ESCR1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_FIRM_ESCR1 0x000003A5\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_FLAME_ESCR0 is defined as MSR_FLAME_ESCR0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_FLAME_ESCR0 0x000003A6\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_FLAME_ESCR1 is defined as MSR_FLAME_ESCR1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_FLAME_ESCR1 0x000003A7\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_DAC_ESCR0 is defined as MSR_DAC_ESCR0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_DAC_ESCR0 0x000003A8\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_DAC_ESCR1 is defined as MSR_DAC_ESCR1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_DAC_ESCR1 0x000003A9\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MOB_ESCR0 is defined as MSR_MOB_ESCR0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_MOB_ESCR0 0x000003AA\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MOB_ESCR1 is defined as MSR_MOB_ESCR1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_MOB_ESCR1 0x000003AB\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_PMH_ESCR0 is defined as MSR_PMH_ESCR0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_PMH_ESCR0 0x000003AC\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_PMH_ESCR1 is defined as MSR_PMH_ESCR1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_PMH_ESCR1 0x000003AD\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_SAAT_ESCR0 is defined as MSR_SAAT_ESCR0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_SAAT_ESCR0 0x000003AE\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_SAAT_ESCR1 is defined as MSR_SAAT_ESCR1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_SAAT_ESCR1 0x000003AF\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_U2L_ESCR0 is defined as MSR_U2L_ESCR0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_U2L_ESCR0 0x000003B0\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_U2L_ESCR1 is defined as MSR_U2L_ESCR1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_U2L_ESCR1 0x000003B1\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_BPU_ESCR0 is defined as MSR_BPU_ESCR0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_BPU_ESCR0 0x000003B2\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_BPU_ESCR1 is defined as MSR_BPU_ESCR1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_BPU_ESCR1 0x000003B3\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_IS_ESCR0 is defined as MSR_IS_ESCR0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_IS_ESCR0 0x000003B4\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_IS_ESCR1 is defined as MSR_IS_ESCR1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_IS_ESCR1 0x000003B5\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_ITLB_ESCR0 is defined as MSR_ITLB_ESCR0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_ITLB_ESCR0 0x000003B6\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_ITLB_ESCR1 is defined as MSR_ITLB_ESCR1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_ITLB_ESCR1 0x000003B7\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_CRU_ESCR0 is defined as MSR_CRU_ESCR0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_CRU_ESCR0 0x000003B8\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_CRU_ESCR1 is defined as MSR_CRU_ESCR1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_CRU_ESCR1 0x000003B9\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_IQ_ESCR0 is defined as MSR_IQ_ESCR0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_IQ_ESCR0 0x000003BA\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_IQ_ESCR1 is defined as MSR_IQ_ESCR1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_IQ_ESCR1 0x000003BB\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_RAT_ESCR0 is defined as MSR_RAT_ESCR0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_RAT_ESCR0 0x000003BC\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_RAT_ESCR1 is defined as MSR_RAT_ESCR1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_RAT_ESCR1 0x000003BD\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_SSU_ESCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_SSU_ESCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_SSU_ESCR0 is defined as MSR_SSU_ESCR0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_SSU_ESCR0 0x000003BE\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MS_ESCR0 is defined as MSR_MS_ESCR0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_MS_ESCR0 0x000003C0\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_MS_ESCR1 is defined as MSR_MS_ESCR1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_MS_ESCR1 0x000003C1\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_TBPU_ESCR0 is defined as MSR_TBPU_ESCR0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_TBPU_ESCR0 0x000003C2\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_TBPU_ESCR1 is defined as MSR_TBPU_ESCR1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_TBPU_ESCR1 0x000003C3\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_TC_ESCR0 is defined as MSR_TC_ESCR0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_TC_ESCR0 0x000003C4\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_TC_ESCR1 is defined as MSR_TC_ESCR1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_TC_ESCR1 0x000003C5\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_IX_ESCR0 is defined as MSR_IX_ESCR0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_IX_ESCR0 0x000003C8\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_IX_ESCR1 is defined as MSR_IX_ESCR1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_IX_ESCR1 0x000003C9\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_ALF_ESCR0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_ALF_ESCR0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_ALF_ESCR0 is defined as MSR_ALF_ESCR0 in SDM.\r
+ MSR_PENTIUM_4_ALF_ESCR1 is defined as MSR_ALF_ESCR1 in SDM.\r
+ MSR_PENTIUM_4_CRU_ESCR2 is defined as MSR_CRU_ESCR2 in SDM.\r
+ MSR_PENTIUM_4_CRU_ESCR3 is defined as MSR_CRU_ESCR3 in SDM.\r
+ MSR_PENTIUM_4_CRU_ESCR4 is defined as MSR_CRU_ESCR4 in SDM.\r
+ MSR_PENTIUM_4_CRU_ESCR5 is defined as MSR_CRU_ESCR5 in SDM.\r
@{\r
**/\r
#define MSR_PENTIUM_4_ALF_ESCR0 0x000003CA\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT);\r
AsmWriteMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_TC_PRECISE_EVENT is defined as MSR_TC_PRECISE_EVENT in SDM.\r
**/\r
#define MSR_PENTIUM_4_TC_PRECISE_EVENT 0x000003F0\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_ENABLE);\r
AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_ENABLE, Msr.Uint64);\r
@endcode\r
+ @note MSR_PENTIUM_4_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
#define MSR_PENTIUM_4_PEBS_ENABLE 0x000003F1\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT);\r
AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_PEBS_MATRIX_VERT is defined as MSR_PEBS_MATRIX_VERT in SDM.\r
**/\r
#define MSR_PENTIUM_4_PEBS_MATRIX_VERT 0x000003F2\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);\r
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.\r
@{\r
**/\r
#define MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP 0x00000680\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);\r
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.\r
@{\r
**/\r
#define MSR_PENTIUM_4_LASTBRANCH_0_TO_IP 0x000006C0\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_IFSB_BUSQ0 is defined as MSR_IFSB_BUSQ0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_IFSB_BUSQ0 0x000107CC\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_IFSB_BUSQ1 is defined as MSR_IFSB_BUSQ1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_IFSB_BUSQ1 0x000107CD\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_IFSB_SNPQ0 is defined as MSR_IFSB_SNPQ0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_IFSB_SNPQ0 0x000107CE\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_IFSB_SNPQ1 is defined as MSR_IFSB_SNPQ1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_IFSB_SNPQ1 0x000107CF\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_EFSB_DRDY0 is defined as MSR_EFSB_DRDY0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_EFSB_DRDY0 0x000107D0\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_EFSB_DRDY1 is defined as MSR_EFSB_DRDY1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_EFSB_DRDY1 0x000107D1\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CTL6);\r
AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CTL6, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_IFSB_CTL6 is defined as MSR_IFSB_CTL6 in SDM.\r
**/\r
#define MSR_PENTIUM_4_IFSB_CTL6 0x000107D2\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CNTR7);\r
AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CNTR7, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_IFSB_CNTR7 is defined as MSR_IFSB_CNTR7 in SDM.\r
**/\r
#define MSR_PENTIUM_4_IFSB_CNTR7 0x000107D3\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0);\r
AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.\r
**/\r
#define MSR_PENTIUM_4_EMON_L3_CTR_CTL0 0x000107CC\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1);\r
AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.\r
**/\r
#define MSR_PENTIUM_4_EMON_L3_CTR_CTL1 0x000107CD\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2);\r
AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.\r
**/\r
#define MSR_PENTIUM_4_EMON_L3_CTR_CTL2 0x000107CE\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3);\r
AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.\r
**/\r
#define MSR_PENTIUM_4_EMON_L3_CTR_CTL3 0x000107CF\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4);\r
AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.\r
**/\r
#define MSR_PENTIUM_4_EMON_L3_CTR_CTL4 0x000107D0\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5);\r
AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.\r
**/\r
#define MSR_PENTIUM_4_EMON_L3_CTR_CTL5 0x000107D1\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6);\r
AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.\r
**/\r
#define MSR_PENTIUM_4_EMON_L3_CTR_CTL6 0x000107D2\r
\r
Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7);\r
AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7, Msr);\r
@endcode\r
+ @note MSR_PENTIUM_4_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.\r
**/\r
#define MSR_PENTIUM_4_EMON_L3_CTR_CTL7 0x000107D3\r
\r