ArmPkg: split off ArmGicArchLib from ArmGicLib

The current implementation of ArmGicGetSupportedArchRevision ()
that is used by all ARM platforms is entirely stateless (in order
to support being executed from flash) so it needs to interrogate
the hardware for the supported GIC revision upon each invocation.

However, this statelessness is only needed for SEC type modules;
in all other cases, we could easily determine the GIC revision once,
and store the result in a global variable.

In preparation of having separate early and normal versions, this patch
introduces the ArmGicArchLib library class and default implementation,
and moves the existing ArmGicGetSupportedArchRevision () into it.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18098 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index da0c8a9f27a7da372e6c34b74aa461a93707dba5..46e9894d3f56316fead02067f8489b01c7769817 100644 (file)
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -38,6 +38,7 @@
   UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h\r
   DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h\r
   ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h\r
+  ArmGicArchLib|Include/Library/ArmGicArchLib.h\r
 \r
 [Guids.common]\r
   gArmTokenSpaceGuid       = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r

diff --git a/ArmPkg/ArmPkg.dsc b/ArmPkg/ArmPkg.dsc
index 1f69799dc24b9fee7db9d2af297d48b9557f7f86..10e8a1a83d46110263dcf36a450a050b9c4bf89f 100644 (file)
--- a/ArmPkg/ArmPkg.dsc
+++ b/ArmPkg/ArmPkg.dsc
@@ -66,6 +66,7 @@
 \r
   CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf\r
   ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf\r
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf\r
   ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf\r
   ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf\r
   ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf\r

diff --git a/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c b/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c
deleted file mode 100644 (file)
index 0e0fa3b..0000000
--- a/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/** @file\r
-*\r
-*  Copyright (c) 2014, ARM Limited. All rights reserved.\r
-*\r
-*  This program and the accompanying materials are licensed and made available\r
-*  under the terms and conditions of the BSD License which accompanies this\r
-*  distribution.  The full text of the license may be found at\r
-*  http://opensource.org/licenses/bsd-license.php\r
-*\r
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Library/ArmLib.h>\r
-#include <Library/ArmGicLib.h>\r
-\r
-ARM_GIC_ARCH_REVISION\r
-EFIAPI\r
-ArmGicGetSupportedArchRevision (\r
-  VOID\r
-  )\r
-{\r
-  UINT32    IccSre;\r
-\r
-  // Ideally we would like to use the GICC IIDR Architecture version here, but\r
-  // this does not seem to be very reliable as the implementation could easily\r
-  // get it wrong. It is more reliable to check if the GICv3 System Register\r
-  // feature is implemented on the CPU. This is also convenient as our GICv3\r
-  // driver requires SRE. If only Memory mapped access is available we try to\r
-  // drive the GIC as a v2.\r
-  if (ArmReadIdPfr0 () & AARCH64_PFR0_GIC) {\r
-    // Make sure System Register access is enabled (SRE). This depends on the\r
-    // higher privilege level giving us permission, otherwise we will either\r
-    // cause an exception here, or the write doesn't stick in which case we need\r
-    // to fall back to the GICv2 MMIO interface.\r
-    // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started\r
-    // at the same exception level.\r
-    // It is the OS responsibility to set this bit.\r
-    IccSre = ArmGicV3GetControlSystemRegisterEnable ();\r
-    if (!(IccSre & ICC_SRE_EL2_SRE)) {\r
-      ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);\r
-      IccSre = ArmGicV3GetControlSystemRegisterEnable ();\r
-    }\r
-    if (IccSre & ICC_SRE_EL2_SRE) {\r
-      return ARM_GIC_ARCH_REVISION_3;\r
-    }\r
-  }\r
-\r
-  return ARM_GIC_ARCH_REVISION_2;\r
-}\r

diff --git a/ArmPkg/Drivers/ArmGic/Arm/ArmGicArchLib.c b/ArmPkg/Drivers/ArmGic/Arm/ArmGicArchLib.c
deleted file mode 100644 (file)
index f256de7..0000000
--- a/ArmPkg/Drivers/ArmGic/Arm/ArmGicArchLib.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/** @file\r
-*\r
-*  Copyright (c) 2014, ARM Limited. All rights reserved.\r
-*\r
-*  This program and the accompanying materials are licensed and made available\r
-*  under the terms and conditions of the BSD License which accompanies this\r
-*  distribution.  The full text of the license may be found at\r
-*  http://opensource.org/licenses/bsd-license.php\r
-*\r
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Library/ArmLib.h>\r
-#include <Library/ArmGicLib.h>\r
-\r
-ARM_GIC_ARCH_REVISION\r
-EFIAPI\r
-ArmGicGetSupportedArchRevision (\r
-  VOID\r
-  )\r
-{\r
-  UINT32    IccSre;\r
-\r
-  // Ideally we would like to use the GICC IIDR Architecture version here, but\r
-  // this does not seem to be very reliable as the implementation could easily\r
-  // get it wrong. It is more reliable to check if the GICv3 System Register\r
-  // feature is implemented on the CPU. This is also convenient as our GICv3\r
-  // driver requires SRE. If only Memory mapped access is available we try to\r
-  // drive the GIC as a v2.\r
-  if (ArmReadIdPfr1 () & ARM_PFR1_GIC) {\r
-    // Make sure System Register access is enabled (SRE). This depends on the\r
-    // higher privilege level giving us permission, otherwise we will either\r
-    // cause an exception here, or the write doesn't stick in which case we need\r
-    // to fall back to the GICv2 MMIO interface.\r
-    // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started\r
-    // at the same exception level.\r
-    // It is the OS responsibility to set this bit.\r
-    IccSre = ArmGicV3GetControlSystemRegisterEnable ();\r
-    if (!(IccSre & ICC_SRE_EL2_SRE)) {\r
-      ArmGicV3SetControlSystemRegisterEnable (IccSre| ICC_SRE_EL2_SRE);\r
-      IccSre = ArmGicV3GetControlSystemRegisterEnable ();\r
-    }\r
-    if (IccSre & ICC_SRE_EL2_SRE) {\r
-      return ARM_GIC_ARCH_REVISION_3;\r
-    }\r
-  }\r
-\r
-  return ARM_GIC_ARCH_REVISION_2;\r
-}\r

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
index 2ae3fd31e8927b8995238f2a0b60cabe26f6b95a..047adac85ff40ee4f6bd63d9fc7c17283b44c7e0 100644 (file)
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
@@ -27,18 +27,17 @@
   GicV2/ArmGicV2NonSecLib.c\r
 \r
 [Sources.ARM]\r
-  Arm/ArmGicArchLib.c\r
   GicV3/Arm/ArmGicV3.S     | GCC\r
   GicV3/Arm/ArmGicV3.asm   | RVCT\r
 \r
 [Sources.AARCH64]\r
-  AArch64/ArmGicArchLib.c\r
   GicV3/AArch64/ArmGicV3.S\r
 \r
 [LibraryClasses]\r
   ArmLib\r
   DebugLib\r
   IoLib\r
+  ArmGicArchLib\r
 \r
 [Packages]\r
   ArmPkg/ArmPkg.dec\r

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
index 7d4e49e4b96fc094c647823b75097f1bbd9dac59..fc2e1bc01efedcde89750989c14b2c9ebcb92714 100644 (file)
--- a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
+++ b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
@@ -27,12 +27,10 @@
   GicV2/ArmGicV2SecLib.c\r
 \r
 [Sources.ARM]\r
-  Arm/ArmGicArchLib.c\r
   GicV3/Arm/ArmGicV3.S     | GCC\r
   GicV3/Arm/ArmGicV3.asm   | RVCT\r
 \r
 [Sources.AARCH64]\r
-  AArch64/ArmGicArchLib.c\r
   GicV3/AArch64/ArmGicV3.S\r
 \r
 [Packages]\r
@@ -45,6 +43,7 @@
   ArmLib\r
   DebugLib\r
   IoLib\r
+  ArmGicArchLib\r
 \r
 [Pcd]\r
   gArmPlatformTokenSpaceGuid.PcdCoreCount\r

diff --git a/ArmPkg/Include/Library/ArmGicArchLib.h b/ArmPkg/Include/Library/ArmGicArchLib.h
new file mode 100644 (file)
index 0000000..e6964a2
--- /dev/null
+++ b/ArmPkg/Include/Library/ArmGicArchLib.h
@@ -0,0 +1,33 @@
+/** @file\r
+*\r
+*  Copyright (c) 2015, Linaro Ltd. All rights reserved.\r
+*\r
+*  This program and the accompanying materials are licensed and made available\r
+*  under the terms and conditions of the BSD License which accompanies this\r
+*  distribution.  The full text of the license may be found at\r
+*  http://opensource.org/licenses/bsd-license.php\r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#ifndef __ARM_GIC_ARCH_LIB_H__\r
+#define __ARM_GIC_ARCH_LIB_H__\r
+\r
+//\r
+// GIC definitions\r
+//\r
+typedef enum {\r
+  ARM_GIC_ARCH_REVISION_2,\r
+  ARM_GIC_ARCH_REVISION_3\r
+} ARM_GIC_ARCH_REVISION;\r
+\r
+\r
+ARM_GIC_ARCH_REVISION\r
+EFIAPI\r
+ArmGicGetSupportedArchRevision (\r
+  VOID\r
+  );\r
+\r
+#endif\r

diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h
index e3db9c0d250f4b3a348bae630e20cc5e6863c885..10c4a9d72eb2f3d8612899851fbf34faf410d999 100644 (file)
--- a/ArmPkg/Include/Library/ArmGicLib.h
+++ b/ArmPkg/Include/Library/ArmGicLib.h
@@ -15,13 +15,7 @@
 #ifndef __ARMGIC_H\r
 #define __ARMGIC_H\r
 \r
-//\r
-// GIC definitions\r
-//\r
-typedef enum {\r
-  ARM_GIC_ARCH_REVISION_2,\r
-  ARM_GIC_ARCH_REVISION_3\r
-} ARM_GIC_ARCH_REVISION;\r
+#include <Library/ArmGicArchLib.h>\r
 \r
 //\r
 // GIC Distributor\r
@@ -103,12 +97,6 @@ typedef enum {
 // Bit Mask for\r
 #define ARM_GIC_ICCIAR_ACKINTID                 0x3FF\r
 \r
-ARM_GIC_ARCH_REVISION\r
-EFIAPI\r
-ArmGicGetSupportedArchRevision (\r
-  VOID\r
-  );\r
-\r
 UINTN\r
 EFIAPI\r
 ArmGicGetInterfaceIdentification (\r

diff --git a/ArmPkg/Library/ArmGicArchLib/AArch64/ArmGicArchLib.c b/ArmPkg/Library/ArmGicArchLib/AArch64/ArmGicArchLib.c
new file mode 100644 (file)
index 0000000..0e0fa3b
--- /dev/null
+++ b/ArmPkg/Library/ArmGicArchLib/AArch64/ArmGicArchLib.c
@@ -0,0 +1,51 @@
+/** @file\r
+*\r
+*  Copyright (c) 2014, ARM Limited. All rights reserved.\r
+*\r
+*  This program and the accompanying materials are licensed and made available\r
+*  under the terms and conditions of the BSD License which accompanies this\r
+*  distribution.  The full text of the license may be found at\r
+*  http://opensource.org/licenses/bsd-license.php\r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Library/ArmLib.h>\r
+#include <Library/ArmGicLib.h>\r
+\r
+ARM_GIC_ARCH_REVISION\r
+EFIAPI\r
+ArmGicGetSupportedArchRevision (\r
+  VOID\r
+  )\r
+{\r
+  UINT32    IccSre;\r
+\r
+  // Ideally we would like to use the GICC IIDR Architecture version here, but\r
+  // this does not seem to be very reliable as the implementation could easily\r
+  // get it wrong. It is more reliable to check if the GICv3 System Register\r
+  // feature is implemented on the CPU. This is also convenient as our GICv3\r
+  // driver requires SRE. If only Memory mapped access is available we try to\r
+  // drive the GIC as a v2.\r
+  if (ArmReadIdPfr0 () & AARCH64_PFR0_GIC) {\r
+    // Make sure System Register access is enabled (SRE). This depends on the\r
+    // higher privilege level giving us permission, otherwise we will either\r
+    // cause an exception here, or the write doesn't stick in which case we need\r
+    // to fall back to the GICv2 MMIO interface.\r
+    // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started\r
+    // at the same exception level.\r
+    // It is the OS responsibility to set this bit.\r
+    IccSre = ArmGicV3GetControlSystemRegisterEnable ();\r
+    if (!(IccSre & ICC_SRE_EL2_SRE)) {\r
+      ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);\r
+      IccSre = ArmGicV3GetControlSystemRegisterEnable ();\r
+    }\r
+    if (IccSre & ICC_SRE_EL2_SRE) {\r
+      return ARM_GIC_ARCH_REVISION_3;\r
+    }\r
+  }\r
+\r
+  return ARM_GIC_ARCH_REVISION_2;\r
+}\r

diff --git a/ArmPkg/Library/ArmGicArchLib/Arm/ArmGicArchLib.c b/ArmPkg/Library/ArmGicArchLib/Arm/ArmGicArchLib.c
new file mode 100644 (file)
index 0000000..f256de7
--- /dev/null
+++ b/ArmPkg/Library/ArmGicArchLib/Arm/ArmGicArchLib.c
@@ -0,0 +1,51 @@
+/** @file\r
+*\r
+*  Copyright (c) 2014, ARM Limited. All rights reserved.\r
+*\r
+*  This program and the accompanying materials are licensed and made available\r
+*  under the terms and conditions of the BSD License which accompanies this\r
+*  distribution.  The full text of the license may be found at\r
+*  http://opensource.org/licenses/bsd-license.php\r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Library/ArmLib.h>\r
+#include <Library/ArmGicLib.h>\r
+\r
+ARM_GIC_ARCH_REVISION\r
+EFIAPI\r
+ArmGicGetSupportedArchRevision (\r
+  VOID\r
+  )\r
+{\r
+  UINT32    IccSre;\r
+\r
+  // Ideally we would like to use the GICC IIDR Architecture version here, but\r
+  // this does not seem to be very reliable as the implementation could easily\r
+  // get it wrong. It is more reliable to check if the GICv3 System Register\r
+  // feature is implemented on the CPU. This is also convenient as our GICv3\r
+  // driver requires SRE. If only Memory mapped access is available we try to\r
+  // drive the GIC as a v2.\r
+  if (ArmReadIdPfr1 () & ARM_PFR1_GIC) {\r
+    // Make sure System Register access is enabled (SRE). This depends on the\r
+    // higher privilege level giving us permission, otherwise we will either\r
+    // cause an exception here, or the write doesn't stick in which case we need\r
+    // to fall back to the GICv2 MMIO interface.\r
+    // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started\r
+    // at the same exception level.\r
+    // It is the OS responsibility to set this bit.\r
+    IccSre = ArmGicV3GetControlSystemRegisterEnable ();\r
+    if (!(IccSre & ICC_SRE_EL2_SRE)) {\r
+      ArmGicV3SetControlSystemRegisterEnable (IccSre| ICC_SRE_EL2_SRE);\r
+      IccSre = ArmGicV3GetControlSystemRegisterEnable ();\r
+    }\r
+    if (IccSre & ICC_SRE_EL2_SRE) {\r
+      return ARM_GIC_ARCH_REVISION_3;\r
+    }\r
+  }\r
+\r
+  return ARM_GIC_ARCH_REVISION_2;\r
+}\r

diff --git a/ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf b/ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
new file mode 100644 (file)
index 0000000..d71b2ad
--- /dev/null
+++ b/ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
@@ -0,0 +1,33 @@
+#/* @file\r
+#  Copyright (c) 2015, Linaro Ltd. All rights reserved.\r
+#\r
+#  This program and the accompanying materials\r
+#  are licensed and made available under the terms and conditions of the BSD License\r
+#  which accompanies this distribution.  The full text of the license may be found at\r
+#  http://opensource.org/licenses/bsd-license.php\r
+#\r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#*/\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = ArmGicArchLib\r
+  FILE_GUID                      = cd67f41a-26e9-4482-90c9-a9aff803382a\r
+  MODULE_TYPE                    = BASE\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = ArmGicArchLib\r
+\r
+[Sources.ARM]\r
+  Arm/ArmGicArchLib.c\r
+\r
+[Sources.AARCH64]\r
+  AArch64/ArmGicArchLib.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  ArmPkg/ArmPkg.dec\r
+\r
+[LibraryClasses]\r
+  ArmGicLib\r

diff --git a/ArmPlatformPkg/ArmPlatformPkg-2ndstage.dsc b/ArmPlatformPkg/ArmPlatformPkg-2ndstage.dsc
index 76415fec586e7a4d2789faa2c812df111acc6ea4..e50fcb095953a826f11d386fb30419b5d33e40a6 100644 (file)
--- a/ArmPlatformPkg/ArmPlatformPkg-2ndstage.dsc
+++ b/ArmPlatformPkg/ArmPlatformPkg-2ndstage.dsc
@@ -78,6 +78,7 @@
   ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf\r
   DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf\r
   ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf\r
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf\r
   ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf\r
   ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf\r
 \r

diff --git a/ArmPlatformPkg/ArmPlatformPkg.dsc b/ArmPlatformPkg/ArmPlatformPkg.dsc
index 014714632221e175fdf716393e7fca99b21e5ec7..0f59fec113f11231f1a7195646b226224d8dcb44 100644 (file)
--- a/ArmPlatformPkg/ArmPlatformPkg.dsc
+++ b/ArmPlatformPkg/ArmPlatformPkg.dsc
@@ -78,6 +78,7 @@
   ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf\r
   DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf\r
   ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf\r
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf\r
   ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf\r
 \r
   SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf\r

diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb.dsc.inc b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb.dsc.inc
index 9445ce2710abf7c059731e56f677738917ed0884..4d0ecfa713d363b9860766f86503395463eb81b0 100644 (file)
--- a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb.dsc.inc
+++ b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb.dsc.inc
@@ -62,6 +62,7 @@
   ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf\r
   DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf\r
   ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf\r
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf\r
   ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf\r
   ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf\r
 \r

diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc
index a488218300e4ea4985d946677890a3e8150d0427..3c7be4e64ab68fe2ca3f775277e5711ff0f40906 100644 (file)
--- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc
+++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc
@@ -71,6 +71,7 @@
   ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf\r
   DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf\r
   ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf\r
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf\r
   ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf\r
   ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf\r
   ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf\r

diff --git a/ArmVirtPkg/ArmVirt.dsc.inc b/ArmVirtPkg/ArmVirt.dsc.inc
index d3f401b1dc194d7be90a4900eec1886072fc38ce..eaafe51a7dab8c8d19a376da40b9965c4e432bdc 100644 (file)
--- a/ArmVirtPkg/ArmVirt.dsc.inc
+++ b/ArmVirtPkg/ArmVirt.dsc.inc
@@ -76,6 +76,7 @@
   ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf\r
   DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf\r
   ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf\r
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf\r
   ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf\r
   ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf\r
   ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf\r