Always set WP in CR0.

Always set RW+P bit for page table by default.

So that we can use write-protection for code later.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18960 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
index fbaa0725f0bc8baf3633fc2bc2e36ac6be66f9ee..ec5b9a0b04231affd66d7a04c661625199048343 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
@@ -123,7 +123,7 @@ L11:
 L12:                                       # as cr4.PGE is not set here, refresh cr3\r
     movl    %eax, %cr4                     # in PreModifyMtrrs() to flush TLB.\r
     movl    %cr0, %ebx\r
 L12:                                       # as cr4.PGE is not set here, refresh cr3\r
     movl    %eax, %cr4                     # in PreModifyMtrrs() to flush TLB.\r
     movl    %cr0, %ebx\r

-    orl     $0x080000000, %ebx             # enable paging\r
+    orl     $0x080010000, %ebx             # enable paging + WP\r

     movl    %ebx, %cr0\r
     leal    DSC_OFFSET(%edi),%ebx\r
     movw    DSC_DS(%ebx),%ax\r
     movl    %ebx, %cr0\r
     leal    DSC_OFFSET(%edi),%ebx\r
     movw    DSC_DS(%ebx),%ax\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
index 8a12927300ca21e57cff0b08bca114b96c429fa5..ac1a9b48ddd0d89569a10417b3753bdf9725c5f2 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
@@ -129,7 +129,7 @@ gSmiCr3     DD      ?
 @@:                                     ; as cr4.PGE is not set here, refresh cr3\r
     mov     cr4, eax                    ; in PreModifyMtrrs() to flush TLB.\r
     mov     ebx, cr0\r
 @@:                                     ; as cr4.PGE is not set here, refresh cr3\r
     mov     cr4, eax                    ; in PreModifyMtrrs() to flush TLB.\r
     mov     ebx, cr0\r

-    or      ebx, 080000000h             ; enable paging\r
+    or      ebx, 080010000h             ; enable paging + WP\r

     mov     cr0, ebx\r
     lea     ebx, [edi + DSC_OFFSET]\r
     mov     ax, [ebx + DSC_DS]\r
     mov     cr0, ebx\r
     lea     ebx, [edi + DSC_OFFSET]\r
     mov     ax, [ebx + DSC_DS]\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index 06ffc6dd86a830963eb9a431af1087d8bbd3acd1..99d03c4b854ba0ca5b427950a3919ab3814bc91c 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -785,7 +785,7 @@ Gen4GPageTable (
   // Set Page Directory Pointers\r
   //\r
   for (Index = 0; Index < 4; Index++) {\r
   // Set Page Directory Pointers\r
   //\r
   for (Index = 0; Index < 4; Index++) {\r

-    Pte[Index] = (UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1) + IA32_PG_P;\r
+    Pte[Index] = (UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1) + PAGE_ATTRIBUTE_BITS;\r

   }\r
   Pte += EFI_PAGE_SIZE / sizeof (*Pte);\r
 \r
   }\r
   Pte += EFI_PAGE_SIZE / sizeof (*Pte);\r
 \r


@@ -793,7 +793,7 @@ Gen4GPageTable (
   // Fill in Page Directory Entries\r
   //\r
   for (Index = 0; Index < EFI_PAGE_SIZE * 4 / sizeof (*Pte); Index++) {\r
   // Fill in Page Directory Entries\r
   //\r
   for (Index = 0; Index < EFI_PAGE_SIZE * 4 / sizeof (*Pte); Index++) {\r

-    Pte[Index] = (Index << 21) + IA32_PG_PS + IA32_PG_RW + IA32_PG_P;\r
+    Pte[Index] = (Index << 21) | IA32_PG_PS | PAGE_ATTRIBUTE_BITS;\r

   }\r
 \r
   if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r
   }\r
 \r
   if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r


@@ -802,7 +802,7 @@ Gen4GPageTable (
     Pdpte = (UINT64*)PageTable;\r
     for (PageIndex = Low2MBoundary; PageIndex <= High2MBoundary; PageIndex += SIZE_2MB) {\r
       Pte = (UINT64*)(UINTN)(Pdpte[BitFieldRead32 ((UINT32)PageIndex, 30, 31)] & ~(EFI_PAGE_SIZE - 1));\r
     Pdpte = (UINT64*)PageTable;\r
     for (PageIndex = Low2MBoundary; PageIndex <= High2MBoundary; PageIndex += SIZE_2MB) {\r
       Pte = (UINT64*)(UINTN)(Pdpte[BitFieldRead32 ((UINT32)PageIndex, 30, 31)] & ~(EFI_PAGE_SIZE - 1));\r

-      Pte[BitFieldRead32 ((UINT32)PageIndex, 21, 29)] = (UINT64)Pages + IA32_PG_RW + IA32_PG_P;\r
+      Pte[BitFieldRead32 ((UINT32)PageIndex, 21, 29)] = (UINT64)Pages | PAGE_ATTRIBUTE_BITS;\r

       //\r
       // Fill in Page Table Entries\r
       //\r
       //\r
       // Fill in Page Table Entries\r
       //\r


@@ -819,7 +819,7 @@ Gen4GPageTable (
             GuardPage = 0;\r
           }\r
         } else {\r
             GuardPage = 0;\r
           }\r
         } else {\r

-          Pte[Index] = PageAddress + IA32_PG_RW + IA32_PG_P;\r
+          Pte[Index] = PageAddress | PAGE_ATTRIBUTE_BITS;\r

         }\r
         PageAddress+= EFI_PAGE_SIZE;\r
       }\r
         }\r
         PageAddress+= EFI_PAGE_SIZE;\r
       }\r


@@ -886,7 +886,7 @@ SetCacheability (
       NewPageTable[Index] |= (UINT64)(Index << EFI_PAGE_SHIFT);\r
     }\r
 \r
       NewPageTable[Index] |= (UINT64)(Index << EFI_PAGE_SHIFT);\r
     }\r
 \r

-    PageTable[PTIndex] = ((UINTN)NewPageTableAddress & gPhyMask) | IA32_PG_P;\r
+    PageTable[PTIndex] = ((UINTN)NewPageTableAddress & gPhyMask) | PAGE_ATTRIBUTE_BITS;\r

   }\r
 \r
   ASSERT (PageTable[PTIndex] & IA32_PG_P);\r
   }\r
 \r
   ASSERT (PageTable[PTIndex] & IA32_PG_P);\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index f2a91655a33b85bdbf3c69b30252d172c877fe98..133165db13214de8fe921f340810de783a740aaa 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -71,15 +71,19 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 ///\r
 #define IA32_PG_P                   BIT0\r
 #define IA32_PG_RW                  BIT1\r
 ///\r
 #define IA32_PG_P                   BIT0\r
 #define IA32_PG_RW                  BIT1\r

+#define IA32_PG_U                   BIT2\r

 #define IA32_PG_WT                  BIT3\r
 #define IA32_PG_CD                  BIT4\r
 #define IA32_PG_A                   BIT5\r
 #define IA32_PG_WT                  BIT3\r
 #define IA32_PG_CD                  BIT4\r
 #define IA32_PG_A                   BIT5\r

+#define IA32_PG_D                   BIT6\r

 #define IA32_PG_PS                  BIT7\r
 #define IA32_PG_PAT_2M              BIT12\r
 #define IA32_PG_PAT_4K              IA32_PG_PS\r
 #define IA32_PG_PMNT                BIT62\r
 #define IA32_PG_NX                  BIT63\r
 \r
 #define IA32_PG_PS                  BIT7\r
 #define IA32_PG_PAT_2M              BIT12\r
 #define IA32_PG_PAT_4K              IA32_PG_PS\r
 #define IA32_PG_PMNT                BIT62\r
 #define IA32_PG_NX                  BIT63\r
 \r

+#define PAGE_ATTRIBUTE_BITS         (IA32_PG_RW | IA32_PG_P)\r
+\r

 //\r
 // Size of Task-State Segment defined in IA32 Manual\r
 //\r
 //\r
 // Size of Task-State Segment defined in IA32 Manual\r
 //\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
index ff4e28ec58e43572fcb0057e24d859ed102d0628..ec4ec9b067c5c6ace339731d7ba31d3299ab7fef 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
@@ -557,9 +557,9 @@ InitPaging (
 \r
           // Split it\r
           for (Level4 = 0; Level4 < SIZE_4KB / sizeof(*Pt); Level4++) {\r
 \r
           // Split it\r
           for (Level4 = 0; Level4 < SIZE_4KB / sizeof(*Pt); Level4++) {\r

-            Pt[Level4] = Address + ((Level4 << 12) | IA32_PG_RW | IA32_PG_P);\r
+            Pt[Level4] = Address + ((Level4 << 12) | PAGE_ATTRIBUTE_BITS);\r

           } // end for PT\r
           } // end for PT\r

-          *Pte = (UINTN)Pt | IA32_PG_RW | IA32_PG_P;\r
+          *Pte = (UINTN)Pt | PAGE_ATTRIBUTE_BITS;\r

         } // end if IsAddressSplit\r
       } // end for PTE\r
     } // end for PDE\r
         } // end if IsAddressSplit\r
       } // end for PTE\r
     } // end for PDE\r


@@ -608,7 +608,7 @@ InitPaging (
             //\r
             // Patch to remove Present flag and RW flag\r
             //\r
             //\r
             // Patch to remove Present flag and RW flag\r
             //\r

-            *Pte = *Pte & (INTN)(INT32)(~(IA32_PG_RW | IA32_PG_P));\r
+            *Pte = *Pte & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r

           }\r
           if (Nx && mXdSupported) {\r
             *Pte = *Pte | IA32_PG_NX;\r
           }\r
           if (Nx && mXdSupported) {\r
             *Pte = *Pte | IA32_PG_NX;\r


@@ -621,7 +621,7 @@ InitPaging (
           }\r
           for (Level4 = 0; Level4 < SIZE_4KB / sizeof(*Pt); Level4++, Pt++) {\r
             if (!IsAddressValid (Address, &Nx)) {\r
           }\r
           for (Level4 = 0; Level4 < SIZE_4KB / sizeof(*Pt); Level4++, Pt++) {\r
             if (!IsAddressValid (Address, &Nx)) {\r

-              *Pt = *Pt & (INTN)(INT32)(~(IA32_PG_RW | IA32_PG_P));\r
+              *Pt = *Pt & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r

             }\r
             if (Nx && mXdSupported) {\r
               *Pt = *Pt | IA32_PG_NX;\r
             }\r
             if (Nx && mXdSupported) {\r
               *Pt = *Pt | IA32_PG_NX;\r


@@ -1244,7 +1244,7 @@ RestorePageTableBelow4G (
     //\r
     PageTable[PTIndex] = (PFAddress & ~((1ull << 21) - 1));\r
     PageTable[PTIndex] |= (UINT64)IA32_PG_PS;\r
     //\r
     PageTable[PTIndex] = (PFAddress & ~((1ull << 21) - 1));\r
     PageTable[PTIndex] |= (UINT64)IA32_PG_PS;\r

-    PageTable[PTIndex] |= (UINT64)(IA32_PG_RW | IA32_PG_P);\r
+    PageTable[PTIndex] |= (UINT64)PAGE_ATTRIBUTE_BITS;\r

     if ((ErrorCode & IA32_PF_EC_ID) != 0) {\r
       PageTable[PTIndex] &= ~IA32_PG_NX;\r
     }\r
     if ((ErrorCode & IA32_PF_EC_ID) != 0) {\r
       PageTable[PTIndex] &= ~IA32_PG_NX;\r
     }\r


@@ -1277,7 +1277,7 @@ RestorePageTableBelow4G (
     // Set new entry\r
     //\r
     PageTable[PTIndex] = (PFAddress & ~((1ull << 12) - 1));\r
     // Set new entry\r
     //\r
     PageTable[PTIndex] = (PFAddress & ~((1ull << 12) - 1));\r

-    PageTable[PTIndex] |= (UINT64)(IA32_PG_RW | IA32_PG_P);\r
+    PageTable[PTIndex] |= (UINT64)PAGE_ATTRIBUTE_BITS;\r

     if ((ErrorCode & IA32_PF_EC_ID) != 0) {\r
       PageTable[PTIndex] &= ~IA32_PG_NX;\r
     }\r
     if ((ErrorCode & IA32_PF_EC_ID) != 0) {\r
       PageTable[PTIndex] &= ~IA32_PG_NX;\r
     }\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
index a7d790fd8aa044662ac40608c2b293a54fd95c05..d242e06a5e02c469b6ff427457e4357ab8454145 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
@@ -127,7 +127,7 @@ SmmInitPageTable (
   // Fill Page-Table-Level4 (PML4) entry\r
   //\r
   PTEntry = (UINT64*)(UINTN)(Pages - EFI_PAGES_TO_SIZE (PAGE_TABLE_PAGES + 1));\r
   // Fill Page-Table-Level4 (PML4) entry\r
   //\r
   PTEntry = (UINT64*)(UINTN)(Pages - EFI_PAGES_TO_SIZE (PAGE_TABLE_PAGES + 1));\r

-  *PTEntry = Pages + IA32_PG_P;\r
+  *PTEntry = Pages + PAGE_ATTRIBUTE_BITS;\r

   ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry));\r
   //\r
   // Set sub-entries number\r
   ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry));\r
   //\r
   // Set sub-entries number\r


@@ -591,7 +591,7 @@ SmiDefaultPFHandler (
         //\r
         // If the entry is not present, allocate one page from page pool for it\r
         //\r
         //\r
         // If the entry is not present, allocate one page from page pool for it\r
         //\r

-        PageTable[PTIndex] = AllocPage () | IA32_PG_RW | IA32_PG_P;\r
+        PageTable[PTIndex] = AllocPage () | PAGE_ATTRIBUTE_BITS;\r

       } else {\r
         //\r
         // Save the upper entry address\r
       } else {\r
         //\r
         // Save the upper entry address\r


@@ -621,7 +621,7 @@ SmiDefaultPFHandler (
     // Fill the new entry\r
     //\r
     PageTable[PTIndex] = (PFAddress & gPhyMask & ~((1ull << EndBit) - 1)) |\r
     // Fill the new entry\r
     //\r
     PageTable[PTIndex] = (PFAddress & gPhyMask & ~((1ull << EndBit) - 1)) |\r

-                         PageAttribute | IA32_PG_A | IA32_PG_RW | IA32_PG_P;\r
+                         PageAttribute | IA32_PG_A | PAGE_ATTRIBUTE_BITS;\r

     if (UpperEntry != NULL) {\r
       SetSubEntriesNum (UpperEntry, GetSubEntriesNum (UpperEntry) + 1);\r
     }\r
     if (UpperEntry != NULL) {\r
       SetSubEntriesNum (UpperEntry, GetSubEntriesNum (UpperEntry) + 1);\r
     }\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
index b488b74b70756af9d9f675fe9fb578e814a0d695..7e9ac58cb2c96f33b554654b40e23c624522a72c 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
@@ -144,7 +144,7 @@ Base:
     orb     $1,%ah\r
     wrmsr\r
     movq    %cr0, %rbx\r
     orb     $1,%ah\r
     wrmsr\r
     movq    %cr0, %rbx\r

-    btsl    $31, %ebx\r
+    orl     $0x080010000, %ebx          # enable paging + WP\r

     movq    %rbx, %cr0\r
     retf\r
 LongMode:                               # long mode (64-bit code) starts here\r
     movq    %rbx, %cr0\r
     retf\r
 LongMode:                               # long mode (64-bit code) starts here\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
index 4f5c03c5cf5fe87a71b25d33be66d9e12531a163..094cf2c3da330820ef9056c57ff78aaf0cbfa6f4 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
@@ -140,7 +140,7 @@ Base:
     or      ah, 1\r
     wrmsr\r
     mov     rbx, cr0\r
     or      ah, 1\r
     wrmsr\r
     mov     rbx, cr0\r

-    bts     ebx, 31\r
+    or      ebx, 080010000h            ; enable paging + WP\r

     mov     cr0, rbx\r
     retf\r
 @LongMode:                              ; long mode (64-bit code) starts here\r
     mov     cr0, rbx\r
     retf\r
 @LongMode:                              ; long mode (64-bit code) starts here\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
index c4ec12debb1c444555564dde20b63ab077afa54b..b3cd629f5576e3633f7b80d56fbbb649d843773c 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
@@ -51,7 +51,7 @@ InitSmmS3Cr3 (
   // Fill Page-Table-Level4 (PML4) entry\r
   //\r
   PTEntry = (UINT64*)(UINTN)(Pages - EFI_PAGES_TO_SIZE (1));\r
   // Fill Page-Table-Level4 (PML4) entry\r
   //\r
   PTEntry = (UINT64*)(UINTN)(Pages - EFI_PAGES_TO_SIZE (1));\r

-  *PTEntry = Pages + IA32_PG_P;\r
+  *PTEntry = Pages | PAGE_ATTRIBUTE_BITS;\r

   ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry));\r
 \r
   //\r
   ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry));\r
 \r
   //\r


@@ -117,7 +117,7 @@ AcquirePage (
   //\r
   // Link & Record the current uplink\r
   //\r
   //\r
   // Link & Record the current uplink\r
   //\r

-  *Uplink = Address | IA32_PG_P | IA32_PG_RW;\r
+  *Uplink = Address | PAGE_ATTRIBUTE_BITS;\r

   mPFPageUplink[mPFPageIndex] = Uplink;\r
 \r
   mPFPageIndex = (mPFPageIndex + 1) % MAX_PF_PAGE_COUNT;\r
   mPFPageUplink[mPFPageIndex] = Uplink;\r
 \r
   mPFPageIndex = (mPFPageIndex + 1) % MAX_PF_PAGE_COUNT;\r


@@ -242,9 +242,9 @@ RestorePageTableAbove4G (
       // PTE\r
       PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r
       for (Index = 0; Index < 512; Index++) {\r
       // PTE\r
       PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r
       for (Index = 0; Index < 512; Index++) {\r

-        PageTable[Index] = Address | IA32_PG_RW | IA32_PG_P;\r
+        PageTable[Index] = Address | PAGE_ATTRIBUTE_BITS;\r

         if (!IsAddressValid (Address, &Nx)) {\r
         if (!IsAddressValid (Address, &Nx)) {\r

-          PageTable[Index] = PageTable[Index] & (INTN)(INT32)(~(IA32_PG_RW | IA32_PG_P));\r
+          PageTable[Index] = PageTable[Index] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r

         }\r
         if (Nx && mXdSupported) {\r
           PageTable[Index] = PageTable[Index] | IA32_PG_NX;\r
         }\r
         if (Nx && mXdSupported) {\r
           PageTable[Index] = PageTable[Index] | IA32_PG_NX;\r


@@ -262,7 +262,7 @@ RestorePageTableAbove4G (
         //\r
         // Patch to remove present flag and rw flag.\r
         //\r
         //\r
         // Patch to remove present flag and rw flag.\r
         //\r

-        PageTable[PTIndex] = PageTable[PTIndex] & (INTN)(INT32)(~(IA32_PG_RW | IA32_PG_P));\r
+        PageTable[PTIndex] = PageTable[PTIndex] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r

       }\r
       //\r
       // Set XD bit to 1\r
       }\r
       //\r
       // Set XD bit to 1\r


@@ -289,7 +289,7 @@ RestorePageTableAbove4G (
   //\r
   // Add present flag or clear XD flag to make page fault handler succeed.\r
   //\r
   //\r
   // Add present flag or clear XD flag to make page fault handler succeed.\r
   //\r

-  PageTable[PTIndex] |= (UINT64)(IA32_PG_RW | IA32_PG_P);\r
+  PageTable[PTIndex] |= (UINT64)(PAGE_ATTRIBUTE_BITS);\r

   if ((ErrorCode & IA32_PF_EC_ID) != 0) {\r
     //\r
     // If page fault is caused by instruction fetch, clear XD bit in the entry.\r
   if ((ErrorCode & IA32_PF_EC_ID) != 0) {\r
     //\r
     // If page fault is caused by instruction fetch, clear XD bit in the entry.\r