--- /dev/null
+/** @file\r
+ MSR Definitions for P6 Family Processors.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
+ December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-19.\r
+\r
+**/\r
+\r
+#ifndef __P6_MSR_H__\r
+#define __P6_MSR_H__\r
+\r
+#include <Register/ArchitecturalMsr.h>\r
+\r
+/**\r
+ See Section 35.20, "MSRs in Pentium Processors.".\r
+\r
+ @param ECX MSR_P6_P5_MC_ADDR (0x00000000)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_P5_MC_ADDR);\r
+ AsmWriteMsr64 (MSR_P6_P5_MC_ADDR, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_P5_MC_ADDR 0x00000000\r
+\r
+\r
+/**\r
+ See Section 35.20, "MSRs in Pentium Processors.".\r
+\r
+ @param ECX MSR_P6_P5_MC_TYPE (0x00000001)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_P5_MC_TYPE);\r
+ AsmWriteMsr64 (MSR_P6_P5_MC_TYPE, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_P5_MC_TYPE 0x00000001\r
+\r
+\r
+/**\r
+ See Section 17.14, "Time-Stamp Counter.".\r
+\r
+ @param ECX MSR_P6_TSC (0x00000010)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_TSC);\r
+ AsmWriteMsr64 (MSR_P6_TSC, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_TSC 0x00000010\r
+\r
+\r
+/**\r
+ Platform ID (R) The operating system can use this MSR to determine "slot"\r
+ information for the processor and the proper microcode update to load.\r
+\r
+ @param ECX MSR_P6_IA32_PLATFORM_ID (0x00000017)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_IA32_PLATFORM_ID_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_IA32_PLATFORM_ID);\r
+ @endcode\r
+**/\r
+#define MSR_P6_IA32_PLATFORM_ID 0x00000017\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_P6_IA32_PLATFORM_ID\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:32;\r
+ UINT32 Reserved2:18;\r
+ ///\r
+ /// [Bits 52:50] Platform Id (R) Contains information concerning the\r
+ /// intended platform for the processor.\r
+ ///\r
+ /// 52 51 50\r
+ /// 0 0 0 Processor Flag 0.\r
+ /// 0 0 1 Processor Flag 1\r
+ /// 0 1 0 Processor Flag 2\r
+ /// 0 1 1 Processor Flag 3\r
+ /// 1 0 0 Processor Flag 4\r
+ /// 1 0 1 Processor Flag 5\r
+ /// 1 1 0 Processor Flag 6\r
+ /// 1 1 1 Processor Flag 7\r
+ ///\r
+ UINT32 PlatformId:3;\r
+ ///\r
+ /// [Bits 56:53] L2 Cache Latency Read.\r
+ ///\r
+ UINT32 L2CacheLatencyRead:4;\r
+ UINT32 Reserved3:3;\r
+ ///\r
+ /// [Bit 60] Clock Frequency Ratio Read.\r
+ ///\r
+ UINT32 ClockFrequencyRatioRead:1;\r
+ UINT32 Reserved4:3;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_IA32_PLATFORM_ID_REGISTER;\r
+\r
+\r
+/**\r
+ Section 10.4.4, "Local APIC Status and Location.".\r
+\r
+ @param ECX MSR_P6_APIC_BASE (0x0000001B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_APIC_BASE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_APIC_BASE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_APIC_BASE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_APIC_BASE);\r
+ AsmWriteMsr64 (MSR_P6_APIC_BASE, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_P6_APIC_BASE 0x0000001B\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_P6_APIC_BASE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bit 8] Boot Strap Processor indicator Bit 1 = BSP.\r
+ ///\r
+ UINT32 BSP:1;\r
+ UINT32 Reserved2:2;\r
+ ///\r
+ /// [Bit 11] APIC Global Enable Bit - Permanent till reset 1 = Enabled 0 =\r
+ /// Disabled.\r
+ ///\r
+ UINT32 EN:1;\r
+ ///\r
+ /// [Bits 31:12] APIC Base Address.\r
+ ///\r
+ UINT32 ApicBase:20;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_APIC_BASE_REGISTER;\r
+\r
+\r
+/**\r
+ Processor Hard Power-On Configuration (R/W) Enables and disables processor\r
+ features; (R) indicates current processor configuration.\r
+\r
+ @param ECX MSR_P6_EBL_CR_POWERON (0x0000002A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_EBL_CR_POWERON_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_EBL_CR_POWERON);\r
+ AsmWriteMsr64 (MSR_P6_EBL_CR_POWERON, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_P6_EBL_CR_POWERON 0x0000002A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_P6_EBL_CR_POWERON\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled 0 = Disabled.\r
+ ///\r
+ UINT32 DataErrorCheckingEnable:1;\r
+ ///\r
+ /// [Bit 2] Response Error Checking Enable FRCERR Observation Enable (R/W)\r
+ /// 1 = Enabled 0 = Disabled.\r
+ ///\r
+ UINT32 ResponseErrorCheckingEnable:1;\r
+ ///\r
+ /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled 0 = Disabled.\r
+ ///\r
+ UINT32 AERR_DriveEnable:1;\r
+ ///\r
+ /// [Bit 4] BERR# Enable for Initiator Bus Requests (R/W) 1 = Enabled 0 =\r
+ /// Disabled.\r
+ ///\r
+ UINT32 BERR_Enable:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 6] BERR# Driver Enable for Initiator Internal Errors (R/W) 1 =\r
+ /// Enabled 0 = Disabled.\r
+ ///\r
+ UINT32 BERR_DriverEnable:1;\r
+ ///\r
+ /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled 0 = Disabled.\r
+ ///\r
+ UINT32 BINIT_DriverEnable:1;\r
+ ///\r
+ /// [Bit 8] Output Tri-state Enabled (R) 1 = Enabled 0 = Disabled.\r
+ ///\r
+ UINT32 OutputTriStateEnable:1;\r
+ ///\r
+ /// [Bit 9] Execute BIST (R) 1 = Enabled 0 = Disabled.\r
+ ///\r
+ UINT32 ExecuteBIST:1;\r
+ ///\r
+ /// [Bit 10] AERR# Observation Enabled (R) 1 = Enabled 0 = Disabled.\r
+ ///\r
+ UINT32 AERR_ObservationEnabled:1;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 12] BINIT# Observation Enabled (R) 1 = Enabled 0 = Disabled.\r
+ ///\r
+ UINT32 BINIT_ObservationEnabled:1;\r
+ ///\r
+ /// [Bit 13] In Order Queue Depth (R) 1 = 1 0 = 8.\r
+ ///\r
+ UINT32 InOrderQueueDepth:1;\r
+ ///\r
+ /// [Bit 14] 1-MByte Power on Reset Vector (R) 1 = 1MByte 0 = 4GBytes.\r
+ ///\r
+ UINT32 ResetVector:1;\r
+ ///\r
+ /// [Bit 15] FRC Mode Enable (R) 1 = Enabled 0 = Disabled.\r
+ ///\r
+ UINT32 FRCModeEnable:1;\r
+ ///\r
+ /// [Bits 17:16] APIC Cluster ID (R).\r
+ ///\r
+ UINT32 APICClusterID:2;\r
+ ///\r
+ /// [Bits 19:18] System Bus Frequency (R) 00 = 66MHz 10 = 100Mhz 01 =\r
+ /// 133MHz 11 = Reserved.\r
+ ///\r
+ UINT32 SystemBusFrequency:2;\r
+ ///\r
+ /// [Bits 21:20] Symmetric Arbitration ID (R).\r
+ ///\r
+ UINT32 SymmetricArbitrationID:2;\r
+ ///\r
+ /// [Bits 25:22] Clock Frequency Ratio (R).\r
+ ///\r
+ UINT32 ClockFrequencyRatio:4;\r
+ ///\r
+ /// [Bit 26] Low Power Mode Enable (R/W).\r
+ ///\r
+ UINT32 LowPowerModeEnable:1;\r
+ ///\r
+ /// [Bit 27] Clock Frequency Ratio.\r
+ ///\r
+ UINT32 ClockFrequencyRatio1:1;\r
+ UINT32 Reserved4:4;\r
+ UINT32 Reserved5:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_EBL_CR_POWERON_REGISTER;\r
+\r
+\r
+/**\r
+ Test Control Register.\r
+\r
+ @param ECX MSR_P6_TEST_CTL (0x00000033)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_TEST_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_TEST_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_TEST_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_TEST_CTL);\r
+ AsmWriteMsr64 (MSR_P6_TEST_CTL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_P6_TEST_CTL 0x00000033\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_P6_TEST_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:30;\r
+ ///\r
+ /// [Bit 30] Streaming Buffer Disable.\r
+ ///\r
+ UINT32 StreamingBufferDisable:1;\r
+ ///\r
+ /// [Bit 31] Disable LOCK# Assertion for split locked access.\r
+ ///\r
+ UINT32 Disable_LOCK:1;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_TEST_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ BIOS Update Trigger Register.\r
+\r
+ @param ECX MSR_P6_BIOS_UPDT_TRIG (0x00000079)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_BIOS_UPDT_TRIG);\r
+ AsmWriteMsr64 (MSR_P6_BIOS_UPDT_TRIG, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_BIOS_UPDT_TRIG 0x00000079\r
+\r
+\r
+/**\r
+ Chunk n data register D[63:0]: used to write to and read from the L2.\r
+\r
+ @param ECX MSR_P6_BBL_CR_Dn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_BBL_CR_D0);\r
+ AsmWriteMsr64 (MSR_P6_BBL_CR_D0, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_P6_BBL_CR_D0 0x00000088\r
+#define MSR_P6_BBL_CR_D1 0x00000089\r
+#define MSR_P6_BBL_CR_D2 0x0000008A\r
+/// @}\r
+\r
+\r
+/**\r
+ BIOS Update Signature Register or Chunk 3 data register D[63:0] Used to\r
+ write to and read from the L2 depending on the usage model.\r
+\r
+ @param ECX MSR_P6_BIOS_SIGN (0x0000008B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_BIOS_SIGN);\r
+ AsmWriteMsr64 (MSR_P6_BIOS_SIGN, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_BIOS_SIGN 0x0000008B\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_PERFCTR0 (0x000000C1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_PERFCTR0);\r
+ AsmWriteMsr64 (MSR_P6_PERFCTR0, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_P6_PERFCTR0 0x000000C1\r
+#define MSR_P6_PERFCTR1 0x000000C2\r
+/// @}\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRCAP (0x000000FE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRCAP);\r
+ AsmWriteMsr64 (MSR_P6_MTRRCAP, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_MTRRCAP 0x000000FE\r
+\r
+\r
+/**\r
+ Address register: used to send specified address (A31-A3) to L2 during cache\r
+ initialization accesses.\r
+\r
+ @param ECX MSR_P6_BBL_CR_ADDR (0x00000116)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_BBL_CR_ADDR_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_ADDR);\r
+ AsmWriteMsr64 (MSR_P6_BBL_CR_ADDR, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_P6_BBL_CR_ADDR 0x00000116\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_P6_BBL_CR_ADDR\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:3;\r
+ ///\r
+ /// [Bits 31:3] Address bits\r
+ ///\r
+ UINT32 Address:29;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_BBL_CR_ADDR_REGISTER;\r
+\r
+\r
+/**\r
+ Data ECC register D[7:0]: used to write ECC and read ECC to/from L2.\r
+\r
+ @param ECX MSR_P6_BBL_CR_DECC (0x00000118)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_BBL_CR_DECC);\r
+ AsmWriteMsr64 (MSR_P6_BBL_CR_DECC, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_BBL_CR_DECC 0x00000118\r
+\r
+\r
+/**\r
+ Control register: used to program L2 commands to be issued via cache\r
+ configuration accesses mechanism. Also receives L2 lookup response.\r
+\r
+ @param ECX MSR_P6_BBL_CR_CTL (0x00000119)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_BBL_CR_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_BBL_CR_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_BBL_CR_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL);\r
+ AsmWriteMsr64 (MSR_P6_BBL_CR_CTL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_P6_BBL_CR_CTL 0x00000119\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_P6_BBL_CR_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 4:0] L2 Command\r
+ /// Data Read w/ LRU update (RLU)\r
+ /// Tag Read w/ Data Read (TRR)\r
+ /// Tag Inquire (TI)\r
+ /// L2 Control Register Read (CR)\r
+ /// L2 Control Register Write (CW)\r
+ /// Tag Write w/ Data Read (TWR)\r
+ /// Tag Write w/ Data Write (TWW)\r
+ /// Tag Write (TW).\r
+ ///\r
+ UINT32 L2Command:5;\r
+ ///\r
+ /// [Bits 6:5] State to L2\r
+ ///\r
+ UINT32 StateToL2:2;\r
+ UINT32 Reserved:1;\r
+ ///\r
+ /// [Bits 9:8] Way to L2.\r
+ ///\r
+ UINT32 WayToL2:2;\r
+ ///\r
+ /// [Bits 11:10] Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11.\r
+ ///\r
+ UINT32 Way:2;\r
+ ///\r
+ /// [Bits 13:12] Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00.\r
+ ///\r
+ UINT32 MESI:2;\r
+ ///\r
+ /// [Bits 15:14] State from L2.\r
+ ///\r
+ UINT32 StateFromL2:2;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 17] L2 Hit.\r
+ ///\r
+ UINT32 L2Hit:1;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bits 20:19] User supplied ECC.\r
+ ///\r
+ UINT32 UserEcc:2;\r
+ ///\r
+ /// [Bit 21] Processor number Disable = 1 Enable = 0 Reserved.\r
+ ///\r
+ UINT32 ProcessorNumber:1;\r
+ UINT32 Reserved4:10;\r
+ UINT32 Reserved5:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_BBL_CR_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Trigger register: used to initiate a cache configuration accesses access,\r
+ Write only with Data = 0.\r
+\r
+ @param ECX MSR_P6_BBL_CR_TRIG (0x0000011A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_BBL_CR_TRIG);\r
+ AsmWriteMsr64 (MSR_P6_BBL_CR_TRIG, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_BBL_CR_TRIG 0x0000011A\r
+\r
+\r
+/**\r
+ Busy register: indicates when a cache configuration accesses L2 command is\r
+ in progress. D[0] = 1 = BUSY.\r
+\r
+ @param ECX MSR_P6_BBL_CR_BUSY (0x0000011B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_BBL_CR_BUSY);\r
+ AsmWriteMsr64 (MSR_P6_BBL_CR_BUSY, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_BBL_CR_BUSY 0x0000011B\r
+\r
+\r
+/**\r
+ Control register 3: used to configure the L2 Cache.\r
+\r
+ @param ECX MSR_P6_BBL_CR_CTL3 (0x0000011E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_BBL_CR_CTL3_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL3);\r
+ AsmWriteMsr64 (MSR_P6_BBL_CR_CTL3, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_P6_BBL_CR_CTL3 0x0000011E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_P6_BBL_CR_CTL3\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] L2 Configured (read/write ).\r
+ ///\r
+ UINT32 L2Configured:1;\r
+ ///\r
+ /// [Bits 4:1] L2 Cache Latency (read/write).\r
+ ///\r
+ UINT32 L2CacheLatency:4;\r
+ ///\r
+ /// [Bit 5] ECC Check Enable (read/write).\r
+ ///\r
+ UINT32 ECCCheckEnable:1;\r
+ ///\r
+ /// [Bit 6] Address Parity Check Enable (read/write).\r
+ ///\r
+ UINT32 AddressParityCheckEnable:1;\r
+ ///\r
+ /// [Bit 7] CRTN Parity Check Enable (read/write).\r
+ ///\r
+ UINT32 CRTNParityCheckEnable:1;\r
+ ///\r
+ /// [Bit 8] L2 Enabled (read/write).\r
+ ///\r
+ UINT32 L2Enabled:1;\r
+ ///\r
+ /// [Bits 10:9] L2 Associativity (read only) Direct Mapped 2 Way 4 Way\r
+ /// Reserved.\r
+ ///\r
+ UINT32 L2Associativity:2;\r
+ ///\r
+ /// [Bits 12:11] Number of L2 banks (read only).\r
+ ///\r
+ UINT32 L2Banks:2;\r
+ ///\r
+ /// [Bits 17:13] Cache size per bank (read/write) 256KBytes 512KBytes\r
+ /// 1MByte 2MByte 4MBytes.\r
+ ///\r
+ UINT32 CacheSizePerBank:5;\r
+ ///\r
+ /// [Bit 18] Cache State error checking enable (read/write).\r
+ ///\r
+ UINT32 CacheStateErrorEnable:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bits 22:20] L2 Physical Address Range support 64GBytes 32GBytes\r
+ /// 16GBytes 8GBytes 4GBytes 2GBytes 1GBytes 512MBytes.\r
+ ///\r
+ UINT32 L2AddressRange:3;\r
+ ///\r
+ /// [Bit 23] L2 Hardware Disable (read only).\r
+ ///\r
+ UINT32 L2HardwareDisable:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 25] Cache bus fraction (read only).\r
+ ///\r
+ UINT32 CacheBusFraction:1;\r
+ UINT32 Reserved3:6;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_BBL_CR_CTL3_REGISTER;\r
+\r
+\r
+/**\r
+ CS register target for CPL 0 code.\r
+\r
+ @param ECX MSR_P6_SYSENTER_CS_MSR (0x00000174)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_SYSENTER_CS_MSR);\r
+ AsmWriteMsr64 (MSR_P6_SYSENTER_CS_MSR, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_SYSENTER_CS_MSR 0x00000174\r
+\r
+\r
+/**\r
+ Stack pointer for CPL 0 stack.\r
+\r
+ @param ECX MSR_P6_SYSENTER_ESP_MSR (0x00000175)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_SYSENTER_ESP_MSR);\r
+ AsmWriteMsr64 (MSR_P6_SYSENTER_ESP_MSR, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_SYSENTER_ESP_MSR 0x00000175\r
+\r
+\r
+/**\r
+ CPL 0 code entry point.\r
+\r
+ @param ECX MSR_P6_SYSENTER_EIP_MSR (0x00000176)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_SYSENTER_EIP_MSR);\r
+ AsmWriteMsr64 (MSR_P6_SYSENTER_EIP_MSR, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_SYSENTER_EIP_MSR 0x00000176\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MCG_CAP (0x00000179)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MCG_CAP);\r
+ AsmWriteMsr64 (MSR_P6_MCG_CAP, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_MCG_CAP 0x00000179\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MCG_STATUS (0x0000017A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MCG_STATUS);\r
+ AsmWriteMsr64 (MSR_P6_MCG_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_MCG_STATUS 0x0000017A\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MCG_CTL (0x0000017B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MCG_CTL);\r
+ AsmWriteMsr64 (MSR_P6_MCG_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_MCG_CTL 0x0000017B\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_PERFEVTSELn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_PERFEVTSEL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_PERFEVTSEL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_PERFEVTSEL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_PERFEVTSEL0);\r
+ AsmWriteMsr64 (MSR_P6_PERFEVTSEL0, Msr.Uint64);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_P6_PERFEVTSEL0 0x00000186\r
+#define MSR_P6_PERFEVTSEL1 0x00000187\r
+/// @}\r
+\r
+/**\r
+ MSR information returned for MSR indexes #MSR_P6_PERFEVTSEL0 and\r
+ #MSR_P6_PERFEVTSEL1.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Event Select Refer to Performance Counter section for a\r
+ /// list of event encodings.\r
+ ///\r
+ UINT32 EventSelect:8;\r
+ ///\r
+ /// [Bits 15:8] UMASK (Unit Mask) Unit mask register set to 0 to enable\r
+ /// all count options.\r
+ ///\r
+ UINT32 UMASK:8;\r
+ ///\r
+ /// [Bit 16] USER Controls the counting of events at Privilege levels of\r
+ /// 1, 2, and 3.\r
+ ///\r
+ UINT32 USR:1;\r
+ ///\r
+ /// [Bit 17] OS Controls the counting of events at Privilege level of 0.\r
+ ///\r
+ UINT32 OS:1;\r
+ ///\r
+ /// [Bit 18] E Occurrence/Duration Mode Select 1 = Occurrence 0 = Duration.\r
+ ///\r
+ UINT32 E:1;\r
+ ///\r
+ /// [Bit 19] PC Enabled the signaling of performance counter overflow via\r
+ /// BP0 pin.\r
+ ///\r
+ UINT32 PC:1;\r
+ ///\r
+ /// [Bit 20] INT Enables the signaling of counter overflow via input to\r
+ /// APIC 1 = Enable 0 = Disable.\r
+ ///\r
+ UINT32 INT:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 22] ENABLE Enables the counting of performance events in both\r
+ /// counters 1 = Enable 0 = Disable.\r
+ ///\r
+ UINT32 EN:1;\r
+ ///\r
+ /// [Bit 23] INV Inverts the result of the CMASK condition 1 = Inverted 0\r
+ /// = Non-Inverted.\r
+ ///\r
+ UINT32 INV:1;\r
+ ///\r
+ /// [Bits 31:24] CMASK (Counter Mask).\r
+ ///\r
+ UINT32 CMASK:8;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_PERFEVTSEL_REGISTER;\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_DEBUGCTLMSR (0x000001D9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_DEBUGCTLMSR_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_DEBUGCTLMSR);\r
+ AsmWriteMsr64 (MSR_P6_DEBUGCTLMSR, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_P6_DEBUGCTLMSR 0x000001D9\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_P6_DEBUGCTLMSR\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Enable/Disable Last Branch Records.\r
+ ///\r
+ UINT32 LBR:1;\r
+ ///\r
+ /// [Bit 1] Branch Trap Flag.\r
+ ///\r
+ UINT32 BTF:1;\r
+ ///\r
+ /// [Bit 2] Performance Monitoring/Break Point Pins.\r
+ ///\r
+ UINT32 PB0:1;\r
+ ///\r
+ /// [Bit 3] Performance Monitoring/Break Point Pins.\r
+ ///\r
+ UINT32 PB1:1;\r
+ ///\r
+ /// [Bit 4] Performance Monitoring/Break Point Pins.\r
+ ///\r
+ UINT32 PB2:1;\r
+ ///\r
+ /// [Bit 5] Performance Monitoring/Break Point Pins.\r
+ ///\r
+ UINT32 PB3:1;\r
+ ///\r
+ /// [Bit 6] Enable/Disable Execution Trace Messages.\r
+ ///\r
+ UINT32 TR:1;\r
+ UINT32 Reserved1:25;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_DEBUGCTLMSR_REGISTER;\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_LASTBRANCHFROMIP (0x000001DB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHFROMIP);\r
+ AsmWriteMsr64 (MSR_P6_LASTBRANCHFROMIP, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_LASTBRANCHFROMIP 0x000001DB\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_LASTBRANCHTOIP (0x000001DC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHTOIP);\r
+ AsmWriteMsr64 (MSR_P6_LASTBRANCHTOIP, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_LASTBRANCHTOIP 0x000001DC\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_LASTINTFROMIP (0x000001DD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_LASTINTFROMIP);\r
+ AsmWriteMsr64 (MSR_P6_LASTINTFROMIP, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_LASTINTFROMIP 0x000001DD\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_LASTINTTOIP (0x000001DE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_LASTINTTOIP);\r
+ AsmWriteMsr64 (MSR_P6_LASTINTTOIP, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_LASTINTTOIP 0x000001DE\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_ROB_CR_BKUPTMPDR6 (0x000001E0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_ROB_CR_BKUPTMPDR6);\r
+ AsmWriteMsr64 (MSR_P6_ROB_CR_BKUPTMPDR6, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_P6_ROB_CR_BKUPTMPDR6 0x000001E0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_P6_ROB_CR_BKUPTMPDR6\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 2] Fast Strings Enable bit. Default is enabled.\r
+ ///\r
+ UINT32 FastStrings:1;\r
+ UINT32 Reserved2:29;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER;\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRPHYSBASEn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0);\r
+ AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_P6_MTRRPHYSBASE0 0x00000200\r
+#define MSR_P6_MTRRPHYSBASE1 0x00000202\r
+#define MSR_P6_MTRRPHYSBASE2 0x00000204\r
+#define MSR_P6_MTRRPHYSBASE3 0x00000206\r
+#define MSR_P6_MTRRPHYSBASE4 0x00000208\r
+#define MSR_P6_MTRRPHYSBASE5 0x0000020A\r
+#define MSR_P6_MTRRPHYSBASE6 0x0000020C\r
+#define MSR_P6_MTRRPHYSBASE7 0x0000020E\r
+/// @}\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRPHYSMASKn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0);\r
+ AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_P6_MTRRPHYSMASK0 0x00000201\r
+#define MSR_P6_MTRRPHYSMASK1 0x00000203\r
+#define MSR_P6_MTRRPHYSMASK2 0x00000205\r
+#define MSR_P6_MTRRPHYSMASK3 0x00000207\r
+#define MSR_P6_MTRRPHYSMASK4 0x00000209\r
+#define MSR_P6_MTRRPHYSMASK5 0x0000020B\r
+#define MSR_P6_MTRRPHYSMASK6 0x0000020D\r
+#define MSR_P6_MTRRPHYSMASK7 0x0000020F\r
+/// @}\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRFIX64K_00000 (0x00000250)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRFIX64K_00000);\r
+ AsmWriteMsr64 (MSR_P6_MTRRFIX64K_00000, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_MTRRFIX64K_00000 0x00000250\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRFIX16K_80000 (0x00000258)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_80000);\r
+ AsmWriteMsr64 (MSR_P6_MTRRFIX16K_80000, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_MTRRFIX16K_80000 0x00000258\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRFIX16K_A0000 (0x00000259)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_A0000);\r
+ AsmWriteMsr64 (MSR_P6_MTRRFIX16K_A0000, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_MTRRFIX16K_A0000 0x00000259\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRFIX4K_C0000 (0x00000268)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C0000);\r
+ AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C0000, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_MTRRFIX4K_C0000 0x00000268\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRFIX4K_C8000 (0x00000269)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C8000);\r
+ AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C8000, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_MTRRFIX4K_C8000 0x00000269\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRFIX4K_D0000 (0x0000026A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D0000);\r
+ AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D0000, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_MTRRFIX4K_D0000 0x0000026A\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRFIX4K_D8000 (0x0000026B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D8000);\r
+ AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D8000, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_MTRRFIX4K_D8000 0x0000026B\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRFIX4K_E0000 (0x0000026C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E0000);\r
+ AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E0000, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_MTRRFIX4K_E0000 0x0000026C\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRFIX4K_E8000 (0x0000026D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E8000);\r
+ AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E8000, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_MTRRFIX4K_E8000 0x0000026D\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRFIX4K_F0000 (0x0000026E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F0000);\r
+ AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F0000, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_MTRRFIX4K_F0000 0x0000026E\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRFIX4K_F8000 (0x0000026F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F8000);\r
+ AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F8000, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_P6_MTRRFIX4K_F8000 0x0000026F\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRDEFTYPE (0x000002FF)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_MTRRDEFTYPE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_MTRRDEFTYPE);\r
+ AsmWriteMsr64 (MSR_P6_MTRRDEFTYPE, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_P6_MTRRDEFTYPE 0x000002FF\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_P6_MTRRDEFTYPE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] Default memory type.\r
+ ///\r
+ UINT32 Type:3;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bit 10] Fixed MTRR enable.\r
+ ///\r
+ UINT32 FE:1;\r
+ ///\r
+ /// [Bit 11] MTRR Enable.\r
+ ///\r
+ UINT32 E:1;\r
+ UINT32 Reserved2:20;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_MTRRDEFTYPE_REGISTER;\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MC0_CTL (0x00000400)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MC0_CTL);\r
+ AsmWriteMsr64 (MSR_P6_MC0_CTL, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_P6_MC0_CTL 0x00000400\r
+#define MSR_P6_MC1_CTL 0x00000404\r
+#define MSR_P6_MC2_CTL 0x00000408\r
+#define MSR_P6_MC3_CTL 0x00000410\r
+#define MSR_P6_MC4_CTL 0x0000040C\r
+/// @}\r
+\r
+\r
+/**\r
+\r
+ Bit definitions for MSR_P6_MC4_STATUS are the same as MSR_P6_MC0_STATUS,\r
+ except bits 0, 4, 57, and 61 are hardcoded to 1.\r
+\r
+ @param ECX MSR_P6_MCn_STATUS\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_MC_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_MC_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_MC_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_MC0_STATUS);\r
+ AsmWriteMsr64 (MSR_P6_MC0_STATUS, Msr.Uint64);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_P6_MC0_STATUS 0x00000401\r
+#define MSR_P6_MC1_STATUS 0x00000405\r
+#define MSR_P6_MC2_STATUS 0x00000409\r
+#define MSR_P6_MC3_STATUS 0x00000411\r
+#define MSR_P6_MC4_STATUS 0x0000040D\r
+/// @}\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_P6_MC0_STATUS to\r
+ #MSR_P6_MC4_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] MC_STATUS_MCACOD.\r
+ ///\r
+ UINT32 MC_STATUS_MCACOD:16;\r
+ ///\r
+ /// [Bits 31:16] MC_STATUS_MSCOD.\r
+ ///\r
+ UINT32 MC_STATUS_MSCOD:16;\r
+ UINT32 Reserved:25;\r
+ ///\r
+ /// [Bit 57] MC_STATUS_DAM.\r
+ ///\r
+ UINT32 MC_STATUS_DAM:1;\r
+ ///\r
+ /// [Bit 58] MC_STATUS_ADDRV.\r
+ ///\r
+ UINT32 MC_STATUS_ADDRV:1;\r
+ ///\r
+ /// [Bit 59] MC_STATUS_MISCV.\r
+ ///\r
+ UINT32 MC_STATUS_MISCV:1;\r
+ ///\r
+ /// [Bit 60] MC_STATUS_EN. (Note: For MC0_STATUS only, this bit is\r
+ /// hardcoded to 1.).\r
+ ///\r
+ UINT32 MC_STATUS_EN:1;\r
+ ///\r
+ /// [Bit 61] MC_STATUS_UC.\r
+ ///\r
+ UINT32 MC_STATUS_UC:1;\r
+ ///\r
+ /// [Bit 62] MC_STATUS_O.\r
+ ///\r
+ UINT32 MC_STATUS_O:1;\r
+ ///\r
+ /// [Bit 63] MC_STATUS_V.\r
+ ///\r
+ UINT32 MC_STATUS_V:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_MC_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+\r
+ MSR_P6_MC4_ADDR is defined in MCA architecture but not implemented in P6 Family processors.\r
+\r
+ @param ECX MSR_P6_MC0_ADDR (0x00000402)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MC0_ADDR);\r
+ AsmWriteMsr64 (MSR_P6_MC0_ADDR, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_P6_MC0_ADDR 0x00000402\r
+#define MSR_P6_MC1_ADDR 0x00000406\r
+#define MSR_P6_MC2_ADDR 0x0000040A\r
+#define MSR_P6_MC3_ADDR 0x00000412\r
+#define MSR_P6_MC4_ADDR 0x0000040E\r
+/// @}\r
+\r
+\r
+/**\r
+ Defined in MCA architecture but not implemented in the P6 family processors.\r
+\r
+ @param ECX MSR_P6_MC0_MISC (0x00000403)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MC0_MISC);\r
+ AsmWriteMsr64 (MSR_P6_MC0_MISC, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_P6_MC0_MISC 0x00000403\r
+#define MSR_P6_MC1_MISC 0x00000407\r
+#define MSR_P6_MC2_MISC 0x0000040B\r
+#define MSR_P6_MC3_MISC 0x00000413\r
+#define MSR_P6_MC4_MISC 0x0000040F\r
+/// @}\r
+\r
+#endif\r
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