/** @file\r
+ EFI Component Name functions implementation for PCI Bus module.\r
\r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
/** @file\r
+ EFI Component Name functions declaration for PCI Bus module.\r
\r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
/** @file\r
Driver Binding functions for PCI Bus module.\r
- \r
-Copyright (c) 2006 - 2009, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+ Single PCI bus driver instance will manager all PCI Root Bridges in one EFI based firmware,\r
+ since all PCI Root Bridges' resources need to be managed together.\r
+ Supported() function will try to get PCI Root Bridge IO Protocol.\r
+ Start() function will get PCI Host Bridge Resource Allocation Protocol to manage all\r
+ PCI Root Bridges. So it means platform needs install PCI Root Bridge IO protocol for each\r
+ PCI Root Bus and install PCI Host Bridge Resource Allocation Protocol.\r
+\r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
@param[in] SystemTable A pointer to the EFI System Table.\r
\r
@retval EFI_SUCCESS The entry point is executed successfully.\r
- @retval other Some error occurs when executing this entry point.\r
+ @retval other Some error occurred when executing this entry point.\r
\r
**/\r
EFI_STATUS\r
{\r
EFI_STATUS Status;\r
EFI_HANDLE Handle;\r
- \r
+\r
//\r
// Initializes PCI devices pool\r
//\r
ASSERT_EFI_ERROR (Status);\r
\r
if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
- // \r
+ //\r
// If Hot Plug is supported, install EFI PCI Hot Plug Request protocol.\r
//\r
Handle = NULL;\r
Controller\r
);\r
\r
+ //\r
+ // Check if Pci Root Bridge IO protocol is installed by platform\r
+ //\r
Status = gBS->OpenProtocol (\r
Controller,\r
&gEfiPciRootBridgeIoProtocolGuid,\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
- \r
+\r
//\r
// Start all the devices under the entire host bridge.\r
//\r
UINT8 Offset;\r
};\r
\r
+//\r
+// defined in PCI Card Specification, 8.0\r
+//\r
+#define PCI_CARD_MEMORY_BASE_0 0x1C\r
+#define PCI_CARD_MEMORY_LIMIT_0 0x20\r
+#define PCI_CARD_MEMORY_BASE_1 0x24\r
+#define PCI_CARD_MEMORY_LIMIT_1 0x28\r
+#define PCI_CARD_IO_BASE_0_LOWER 0x2C\r
+#define PCI_CARD_IO_BASE_0_UPPER 0x2E\r
+#define PCI_CARD_IO_LIMIT_0_LOWER 0x30\r
+#define PCI_CARD_IO_LIMIT_0_UPPER 0x32\r
+#define PCI_CARD_IO_BASE_1_LOWER 0x34\r
+#define PCI_CARD_IO_BASE_1_UPPER 0x36\r
+#define PCI_CARD_IO_LIMIT_1_LOWER 0x38\r
+#define PCI_CARD_IO_LIMIT_1_UPPER 0x3A\r
+#define PCI_CARD_BRIDGE_CONTROL 0x3E\r
+\r
+#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8\r
+#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9\r
+\r
#define PPB_BAR_0 0\r
#define PPB_BAR_1 1\r
#define PPB_IO_RANGE 2\r
extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;\r
\r
\r
-/** \r
+/**\r
Macro that checks whether device is a GFX device.\r
\r
@param _p Specified device.\r
[Protocols]\r
gEfiPciHotPlugRequestProtocolGuid ## BY_START\r
gEfiPciIoProtocolGuid ## BY_START\r
- gEfiDevicePathProtocolGuid ## BY_START \r
- gEfiBusSpecificDriverOverrideProtocolGuid ## CONSUMED\r
+ gEfiDevicePathProtocolGuid ## BY_START\r
+ gEfiBusSpecificDriverOverrideProtocolGuid ## BY_START\r
gEfiLoadedImageProtocolGuid ## CONSUMED\r
gEfiDecompressProtocolGuid ## CONSUMED\r
gEfiPciHotPlugInitProtocolGuid ## CONSUMED\r
[Pcd.common]\r
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciIncompatibleDeviceSupportMask\r
\r
-\r
+# [Event]\r
+# ##\r
+# # Notify event set by CreateEventForHpc () for PCI Hot Plug controller.\r
+# #\r
+# EVT_NOTIFY_SIGNAL ## PRODUCES\r
+#\r
+#\r
/** @file\r
- This module implement Pci register operation interface for \r
- Pci device.\r
- \r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+ PCI command register operations supporting functions implementation for PCI Bus module.\r
\r
-**/\r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
+**/\r
\r
#include "PciBus.h"\r
\r
/**\r
Operate the PCI register via PciIo function interface.\r
- \r
- @param PciIoDevice Pointer to instance of PCI_IO_DEVICE\r
- @param Command Operator command\r
+\r
+ @param PciIoDevice Pointer to instance of PCI_IO_DEVICE.\r
+ @param Command Operator command.\r
@param Offset The address within the PCI configuration space for the PCI controller.\r
- @param Operation Type of Operation\r
- @param PtrCommand Return buffer holding old PCI command, if operation is not EFI_SET_REGISTER\r
- \r
- @return status of PciIo operation\r
+ @param Operation Type of Operation.\r
+ @param PtrCommand Return buffer holding old PCI command, if operation is not EFI_SET_REGISTER.\r
+\r
+ @return Status of PciIo operation.\r
+\r
**/\r
EFI_STATUS\r
PciOperateRegister (\r
}\r
\r
/**\r
- check the cpability of this device supports\r
- \r
- @param PciIoDevice Pointer to instance of PCI_IO_DEVICE\r
- \r
- @retval TRUE Support\r
- @retval FALSE Not support.\r
+ Check the cpability supporting by given device.\r
+\r
+ @param PciIoDevice Pointer to instance of PCI_IO_DEVICE.\r
+\r
+ @retval TRUE Cpability supportted.\r
+ @retval FALSE Cpability not supportted.\r
+\r
**/\r
BOOLEAN\r
PciCapabilitySupport (\r
IN PCI_IO_DEVICE *PciIoDevice\r
)\r
{\r
-\r
if ((PciIoDevice->Pci.Hdr.Status & EFI_PCI_STATUS_CAPABILITY) != 0) {\r
return TRUE;\r
}\r
}\r
\r
/**\r
- Locate cap reg.\r
- \r
- @param PciIoDevice - A pointer to the PCI_IO_DEVICE.\r
- @param CapId - The cap ID.\r
- @param Offset - A pointer to the offset.\r
- @param NextRegBlock - A pointer to the next block.\r
- \r
- @retval EFI_UNSUPPORTED Pci device does not support\r
+ Locate capability register block per capability ID.\r
+\r
+ @param PciIoDevice A pointer to the PCI_IO_DEVICE.\r
+ @param CapId The capability ID.\r
+ @param Offset A pointer to the offset returned.\r
+ @param NextRegBlock A pointer to the next block returned.\r
+\r
+ @retval EFI_SUCCESS Successfuly located capability register block.\r
+ @retval EFI_UNSUPPORTED Pci device does not support capability.\r
@retval EFI_NOT_FOUND Pci device support but can not find register block.\r
- @retval EFI_SUCCESS Success to locate capability register block\r
+\r
**/\r
EFI_STATUS\r
LocateCapabilityRegBlock (\r
if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {\r
\r
PciIoRead (\r
- &PciIoDevice->PciIo,\r
- EfiPciIoWidthUint8,\r
- EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,\r
- 1,\r
- &CapabilityPtr\r
- );\r
+ &PciIoDevice->PciIo,\r
+ EfiPciIoWidthUint8,\r
+ EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,\r
+ 1,\r
+ &CapabilityPtr\r
+ );\r
} else {\r
\r
PciIoRead (\r
- &PciIoDevice->PciIo,\r
- EfiPciIoWidthUint8,\r
- PCI_CAPBILITY_POINTER_OFFSET,\r
- 1,\r
- &CapabilityPtr\r
- );\r
+ &PciIoDevice->PciIo,\r
+ EfiPciIoWidthUint8,\r
+ PCI_CAPBILITY_POINTER_OFFSET,\r
+ 1,\r
+ &CapabilityPtr\r
+ );\r
}\r
}\r
\r
while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r
PciIoRead (\r
- &PciIoDevice->PciIo,\r
- EfiPciIoWidthUint16,\r
- CapabilityPtr,\r
- 1,\r
- &CapabilityEntry\r
- );\r
+ &PciIoDevice->PciIo,\r
+ EfiPciIoWidthUint16,\r
+ CapabilityPtr,\r
+ 1,\r
+ &CapabilityEntry\r
+ );\r
\r
CapabilityID = (UINT8) CapabilityEntry;\r
\r
/** @file\r
+ PCI command register operations supporting functions declaration for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2009, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
\r
//\r
// The PCI Bridge Control register bits owned by PCI Bus driver.\r
-// \r
+//\r
// They should be cleared at the beginning. The other registers\r
// are owned by chipset, we should not touch them.\r
//\r
\r
//\r
// The PCCard Bridge Control register bits owned by PCI Bus driver.\r
-// \r
+//\r
// They should be cleared at the beginning. The other registers\r
// are owned by chipset, we should not touch them.\r
//\r
\r
/**\r
Operate the PCI register via PciIo function interface.\r
- \r
- @param PciIoDevice Pointer to instance of PCI_IO_DEVICE\r
- @param Command Operator command\r
+\r
+ @param PciIoDevice Pointer to instance of PCI_IO_DEVICE.\r
+ @param Command Operator command.\r
@param Offset The address within the PCI configuration space for the PCI controller.\r
- @param Operation Type of Operation\r
- @param PtrCommand Return buffer holding old PCI command, if operation is not EFI_SET_REGISTER\r
- \r
- @return status of PciIo operation\r
+ @param Operation Type of Operation.\r
+ @param PtrCommand Return buffer holding old PCI command, if operation is not EFI_SET_REGISTER.\r
+\r
+ @return Status of PciIo operation.\r
+\r
**/\r
EFI_STATUS\r
PciOperateRegister (\r
);\r
\r
/**\r
- check the cpability of this device supports\r
- \r
- @param PciIoDevice Pointer to instance of PCI_IO_DEVICE\r
- \r
- @retval TRUE Support\r
- @retval FALSE Not support.\r
+ Check the cpability supporting by given device.\r
+\r
+ @param PciIoDevice Pointer to instance of PCI_IO_DEVICE.\r
+\r
+ @retval TRUE Cpability supportted.\r
+ @retval FALSE Cpability not supportted.\r
+\r
**/\r
BOOLEAN\r
PciCapabilitySupport (\r
);\r
\r
/**\r
- Locate cap reg.\r
- \r
- @param PciIoDevice - A pointer to the PCI_IO_DEVICE.\r
- @param CapId - The cap ID.\r
- @param Offset - A pointer to the offset.\r
- @param NextRegBlock - A pointer to the next block.\r
- \r
- @retval EFI_UNSUPPORTED Pci device does not support\r
+ Locate capability register block per capability ID.\r
+\r
+ @param PciIoDevice A pointer to the PCI_IO_DEVICE.\r
+ @param CapId The capability ID.\r
+ @param Offset A pointer to the offset returned.\r
+ @param NextRegBlock A pointer to the next block returned.\r
+\r
+ @retval EFI_SUCCESS Successfuly located capability register block.\r
+ @retval EFI_UNSUPPORTED Pci device does not support capability.\r
@retval EFI_NOT_FOUND Pci device support but can not find register block.\r
- @retval EFI_SUCCESS Success to locate capability register block\r
+\r
**/\r
EFI_STATUS\r
LocateCapabilityRegBlock (\r
OUT UINT8 *NextRegBlock OPTIONAL\r
);\r
\r
-/** \r
+/**\r
Macro that reads command register.\r
\r
@param a[in] Pointer to instance of PCI_IO_DEVICE.\r
@param b[out] Pointer to the 16-bit value read from command register.\r
- \r
+\r
@return status of PciIo operation\r
\r
**/\r
#define PCI_READ_COMMAND_REGISTER(a,b) \\r
PciOperateRegister (a, 0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b)\r
\r
-/** \r
+/**\r
Macro that writes command register.\r
\r
@param a[in] Pointer to instance of PCI_IO_DEVICE.\r
@param b[in] The 16-bit value written into command register.\r
- \r
+\r
@return status of PciIo operation\r
\r
**/\r
#define PCI_SET_COMMAND_REGISTER(a,b) \\r
PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL)\r
\r
-/** \r
+/**\r
Macro that enables command register.\r
\r
@param a[in] Pointer to instance of PCI_IO_DEVICE.\r
@param b[in] The enabled value written into command register.\r
- \r
+\r
@return status of PciIo operation\r
\r
-**/ \r
+**/\r
#define PCI_ENABLE_COMMAND_REGISTER(a,b) \\r
PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)\r
\r
-/** \r
+/**\r
Macro that disalbes command register.\r
\r
@param a[in] Pointer to instance of PCI_IO_DEVICE.\r
@param b[in] The disabled value written into command register.\r
- \r
+\r
@return status of PciIo operation\r
\r
-**/ \r
+**/\r
#define PCI_DISABLE_COMMAND_REGISTER(a,b) \\r
PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL)\r
\r
-/** \r
+/**\r
Macro that reads PCI bridge control register.\r
\r
@param a[in] Pointer to instance of PCI_IO_DEVICE.\r
@param b[out] The 16-bit value read from control register.\r
- \r
+\r
@return status of PciIo operation\r
\r
**/\r
#define PCI_READ_BRIDGE_CONTROL_REGISTER(a,b) \\r
PciOperateRegister (a, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b)\r
\r
-/** \r
+/**\r
Macro that writes PCI bridge control register.\r
\r
@param a[in] Pointer to instance of PCI_IO_DEVICE.\r
@param b[in] The 16-bit value written into control register.\r
- \r
+\r
@return status of PciIo operation\r
\r
-**/ \r
+**/\r
#define PCI_SET_BRIDGE_CONTROL_REGISTER(a,b) \\r
PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL)\r
\r
-/** \r
+/**\r
Macro that enables PCI bridge control register.\r
\r
@param a[in] Pointer to instance of PCI_IO_DEVICE.\r
@param b[in] The enabled value written into command register.\r
- \r
+\r
@return status of PciIo operation\r
\r
**/\r
#define PCI_ENABLE_BRIDGE_CONTROL_REGISTER(a,b) \\r
PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)\r
\r
-/** \r
+/**\r
Macro that disalbes PCI bridge control register.\r
\r
@param a[in] Pointer to instance of PCI_IO_DEVICE.\r
@param b[in] The disabled value written into command register.\r
- \r
+\r
@return status of PciIo operation\r
\r
-**/ \r
+**/\r
#define PCI_DISABLE_BRIDGE_CONTROL_REGISTER(a,b) \\r
PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL)\r
\r
/** @file\r
Supporting functions implementaion for PCI devices management.\r
\r
-Copyright (c) 2006 - 2009, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
\r
/**\r
Destroy root bridge and remove it from deivce tree.\r
- \r
+\r
@param RootBridge The bridge want to be removed.\r
- \r
+\r
**/\r
VOID\r
DestroyRootBridge (\r
}\r
\r
/**\r
- This function registers the PCI IO device. \r
+ This function registers the PCI IO device.\r
\r
- It creates a handle for this PCI IO device (if the handle does not exist), attaches \r
- appropriate protocols onto the handle, does necessary initialization, and sets up \r
+ It creates a handle for this PCI IO device (if the handle does not exist), attaches\r
+ appropriate protocols onto the handle, does necessary initialization, and sets up\r
parent/child relationship with its bus controller.\r
\r
@param Controller An EFI handle for the PCI bus controller.\r
@param Handle A pointer to hold the returned EFI handle for the PCI IO device.\r
\r
@retval EFI_SUCCESS The PCI device is successfully registered.\r
- @retval Others An error occurred when registering the PCI device.\r
+ @retval other An error occurred when registering the PCI device.\r
\r
**/\r
EFI_STATUS\r
if (!EFI_ERROR (Status)) {\r
PciIoDevice->IsPciExp = TRUE;\r
}\r
- \r
+\r
//\r
// Force Interrupt line to "Unknown" or "No Connection"\r
//\r
\r
if (PciIoDevice->BusOverride) {\r
//\r
- // Install BusSpecificDriverOverride Protocol\r
+ // Install Bus Specific Driver Override Protocol\r
//\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&PciIoDevice->Handle,\r
@param Handle PCI device handle.\r
\r
@retval EFI_SUCCESS The PCI device is successfully de-registered.\r
- @retval Others An error occurred when de-registering the PCI device.\r
+ @retval other An error occurred when de-registering the PCI device.\r
\r
**/\r
EFI_STATUS\r
);\r
\r
//\r
- // Un-install the device path protocol and pci io protocol\r
+ // Un-install the Device Path protocol and PCI I/O protocol\r
+ // and Bus Specific Driver Override protocol if needed.\r
//\r
if (PciIoDevice->BusOverride) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
\r
@retval EFI_NOT_READY Device is not allocated.\r
@retval EFI_UNSUPPORTED Device only support PCI-PCI bridge.\r
- @retval EFI_NOT_FOUND Can not find the specific device\r
- @retval EFI_SUCCESS Success to start Pci device on bridge\r
+ @retval EFI_NOT_FOUND Can not find the specific device.\r
+ @retval EFI_SUCCESS Success to start Pci device on bridge.\r
\r
**/\r
EFI_STATUS\r
\r
Node.DevPath = RemainingDevicePath;\r
\r
- if (Node.Pci->Device != PciIoDevice->DeviceNumber || \r
+ if (Node.Pci->Device != PciIoDevice->DeviceNumber ||\r
Node.Pci->Function != PciIoDevice->FunctionNumber) {\r
CurrentLink = CurrentLink->ForwardLink;\r
continue;\r
if (!PciIoDevice->Allocated) {\r
return EFI_NOT_READY;\r
}\r
- \r
+\r
//\r
// Check if the current node has been registered before\r
// If it is not, register it\r
ChildHandleBuffer[*NumberOfChildren] = PciIoDevice->Handle;\r
(*NumberOfChildren)++;\r
}\r
- \r
+\r
//\r
// Get the next device path\r
//\r
}\r
\r
/**\r
- Start to manage all the PCI devices it found previously under \r
+ Start to manage all the PCI devices it found previously under\r
the entire host bridge.\r
\r
@param Controller The root bridge handle.\r
\r
+ @retval EFI_NOT_READY Device is not allocated.\r
+ @retval EFI_SUCCESS Success to start Pci device on host bridge.\r
+\r
**/\r
EFI_STATUS\r
StartPciDevices (\r
IN EFI_HANDLE Controller\r
)\r
-\r
{\r
+ EFI_STATUS Status;\r
PCI_IO_DEVICE *RootBridge;\r
EFI_HANDLE ThisHostBridge;\r
LIST_ENTRY *CurrentLink;\r
// Locate the right root bridge to start\r
//\r
if (RootBridge->PciRootBridgeIo->ParentHandle == ThisHostBridge) {\r
- StartPciDevicesOnBridge (\r
- RootBridge->Handle,\r
- RootBridge,\r
- NULL,\r
- NULL,\r
- NULL\r
- );\r
+ Status = StartPciDevicesOnBridge (\r
+ RootBridge->Handle,\r
+ RootBridge,\r
+ NULL,\r
+ NULL,\r
+ NULL\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
}\r
\r
CurrentLink = CurrentLink->ForwardLink;\r
\r
/**\r
Judege whether Pci device existed.\r
- \r
+\r
@param Bridge Parent bridege instance.\r
@param PciIoDevice Device instance.\r
- \r
+\r
@retval TRUE Pci device existed.\r
@retval FALSE Pci device did not exist.\r
\r
\r
/**\r
Get the active VGA device on the same segment.\r
- \r
+\r
@param VgaDevice PCI IO instance for the VGA device.\r
- \r
+\r
@return The active VGA device on the same segment.\r
\r
**/\r
\r
/**\r
Get the active VGA device on the root bridge.\r
- \r
+\r
@param RootBridge PCI IO instance for the root bridge.\r
- \r
+\r
@return The active VGA device.\r
\r
**/\r
@param RootBridge Root bridege Io instance.\r
@param RemainingDevicePath Given searching device path.\r
@param PciAddress Buffer holding searched result.\r
- \r
+\r
@retval EFI_SUCCESS PCI address was stored in PciAddress\r
@retval EFI_NOT_FOUND Can not find the specific device path.\r
- \r
+\r
**/\r
EFI_STATUS\r
GetHpcPciAddressFromRootBridge (\r
/** @file\r
Supporting functions declaration for PCI devices management.\r
\r
-Copyright (c) 2006 - 2009, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
\r
/**\r
Destroy root bridge and remove it from deivce tree.\r
- \r
+\r
@param RootBridge The bridge want to be removed.\r
- \r
+\r
**/\r
VOID\r
DestroyRootBridge (\r
);\r
\r
/**\r
- This function registers the PCI IO device. \r
+ This function registers the PCI IO device.\r
\r
- It creates a handle for this PCI IO device (if the handle does not exist), attaches \r
- appropriate protocols onto the handle, does necessary initialization, and sets up \r
+ It creates a handle for this PCI IO device (if the handle does not exist), attaches\r
+ appropriate protocols onto the handle, does necessary initialization, and sets up\r
parent/child relationship with its bus controller.\r
\r
@param Controller An EFI handle for the PCI bus controller.\r
@param Handle A pointer to hold the returned EFI handle for the PCI IO device.\r
\r
@retval EFI_SUCCESS The PCI device is successfully registered.\r
- @retval Others An error occurred when registering the PCI device.\r
+ @retval other An error occurred when registering the PCI device.\r
\r
**/\r
EFI_STATUS\r
@param Handle PCI device handle.\r
\r
@retval EFI_SUCCESS The PCI device is successfully de-registered.\r
- @retval Others An error occurred when de-registering the PCI device.\r
+ @retval other An error occurred when de-registering the PCI device.\r
\r
**/\r
EFI_STATUS\r
/**\r
Start to manage the PCI device on specified the root bridge or PCI-PCI Bridge\r
\r
- @param Controller An efi handle.\r
+ @param Controller The root bridge handle.\r
@param RootBridge A pointer to the PCI_IO_DEVICE.\r
@param RemainingDevicePath A pointer to the EFI_DEVICE_PATH_PROTOCOL.\r
@param NumberOfChildren Children number.\r
\r
@retval EFI_NOT_READY Device is not allocated.\r
@retval EFI_UNSUPPORTED Device only support PCI-PCI bridge.\r
- @retval EFI_NOT_FOUND Can not find the specific device\r
- @retval EFI_SUCCESS Success to start Pci device on bridge\r
+ @retval EFI_NOT_FOUND Can not find the specific device.\r
+ @retval EFI_SUCCESS Success to start Pci device on bridge.\r
\r
**/\r
EFI_STATUS\r
);\r
\r
/**\r
- Start to manage all the PCI devices it found previously under \r
+ Start to manage all the PCI devices it found previously under\r
the entire host bridge.\r
\r
- @param Controller - root bridge handle.\r
+ @param Controller The root bridge handle.\r
+\r
+ @retval EFI_NOT_READY Device is not allocated.\r
+ @retval EFI_SUCCESS Success to start Pci device on host bridge.\r
\r
**/\r
EFI_STATUS\r
\r
/**\r
Judege whether Pci device existed.\r
- \r
+\r
@param Bridge Parent bridege instance.\r
@param PciIoDevice Device instance.\r
- \r
+\r
@retval TRUE Pci device existed.\r
@retval FALSE Pci device did not exist.\r
\r
\r
/**\r
Get the active VGA device on the same segment.\r
- \r
+\r
@param VgaDevice PCI IO instance for the VGA device.\r
- \r
+\r
@return The active VGA device on the same segment.\r
\r
**/\r
\r
/**\r
Get the active VGA device on the root bridge.\r
- \r
+\r
@param RootBridge PCI IO instance for the root bridge.\r
- \r
+\r
@return The active VGA device.\r
\r
**/\r
@param RootBridge Root bridege Io instance.\r
@param RemainingDevicePath Given searching device path.\r
@param PciAddress Buffer holding searched result.\r
- \r
+\r
@retval EFI_SUCCESS PCI address was stored in PciAddress.\r
@retval EFI_NOT_FOUND Can not find the specific device path.\r
- \r
+\r
**/\r
EFI_STATUS\r
GetHpcPciAddressFromRootBridge (\r
/** @file\r
+ Functions implementation for Bus Specific Driver Override protoocl.\r
\r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
\r
-**/\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
+**/\r
\r
#include "PciBus.h"\r
\r
/**\r
Initializes a PCI Driver Override Instance.\r
\r
- @param PciIoDevice Device instance.\r
+ @param PciIoDevice PCI Device instance.\r
\r
**/\r
VOID\r
InitializePciDriverOverrideInstance (\r
- PCI_IO_DEVICE *PciIoDevice\r
+ IN OUT PCI_IO_DEVICE *PciIoDevice\r
)\r
{\r
PciIoDevice->PciDriverOverride.GetDriver = GetDriver;\r
}\r
\r
+\r
/**\r
- Get a overriding driver image.\r
- @param This Pointer to instance of EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL.\r
- @param DriverImageHandle Override driver image.\r
- \r
- @retval EFI_SUCCESS Success to get driver image handle.\r
- @retval EFI_NOT_FOUND can not find override driver image.\r
- @retval EFI_INVALID_PARAMETER Invalid parameter.\r
+ Uses a bus specific algorithm to retrieve a driver image handle for a controller.\r
+\r
+ @param This A pointer to the EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL instance.\r
+ @param DriverImageHandle On input, a pointer to the previous driver image handle returned\r
+ by GetDriver(). On output, a pointer to the next driver\r
+ image handle. Passing in a NULL, will return the first driver\r
+ image handle.\r
+\r
+ @retval EFI_SUCCESS A bus specific override driver is returned in DriverImageHandle.\r
+ @retval EFI_NOT_FOUND The end of the list of override drivers was reached.\r
+ A bus specific override driver is not returned in DriverImageHandle.\r
+ @retval EFI_INVALID_PARAMETER DriverImageHandle is not a handle that was returned on a\r
+ previous call to GetDriver().\r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
}\r
\r
/**\r
- Add an overriding driver image\r
- \r
+ Add an overriding driver image.\r
+\r
@param PciIoDevice Instance of PciIo device.\r
@param DriverImageHandle new added driver image.\r
- \r
- @retval EFI_OUT_OF_RESOURCES no memory resource for new driver instance.\r
- @retval EFI_SUCCESS Success add driver.\r
+\r
+ @retval EFI_SUCCESS Successfully added driver.\r
+ @retval EFI_OUT_OF_RESOURCES No memory resource for new driver instance.\r
+ @retval other Some error occurred when locating gEfiLoadedImageProtocolGuid.\r
+\r
**/\r
EFI_STATUS\r
AddDriver (\r
ImageContext.ImageRead = PeCoffLoaderImageReadFromMemory;\r
\r
//\r
- // Get information about the image \r
+ // Get information about the image\r
//\r
- Status = PeCoffLoaderGetImageInfo (&ImageContext);\r
- if (EFI_ERROR (Status)) {\r
- return EFI_SUCCESS;\r
- }\r
-\r
- if (ImageContext.Machine != EFI_IMAGE_MACHINE_EBC) {\r
- return EFI_SUCCESS;\r
- }\r
+ PeCoffLoaderGetImageInfo (&ImageContext);\r
\r
return EFI_SUCCESS;\r
}\r
/** @file\r
+ Functions declaration for Bus Specific Driver Override protoocl.\r
\r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
\r
#define DRIVER_OVERRIDE_SIGNATURE SIGNATURE_32 ('d', 'r', 'o', 'v')\r
\r
+//\r
+// PCI driver override driver image list\r
+//\r
typedef struct {\r
UINT32 Signature;\r
LIST_ENTRY Link;\r
/**\r
Initializes a PCI Driver Override Instance.\r
\r
- @param PciIoDevice Device instance.\r
+ @param PciIoDevice PCI Device instance.\r
\r
**/\r
VOID\r
InitializePciDriverOverrideInstance (\r
- PCI_IO_DEVICE *PciIoDevice\r
+ IN OUT PCI_IO_DEVICE *PciIoDevice\r
);\r
\r
/**\r
Add an overriding driver image.\r
- \r
+\r
@param PciIoDevice Instance of PciIo device.\r
@param DriverImageHandle new added driver image.\r
- \r
- @retval EFI_OUT_OF_RESOURCES no memory resource for new driver instance.\r
- @retval EFI_SUCCESS Success add driver.\r
+\r
+ @retval EFI_SUCCESS Successfully added driver.\r
+ @retval EFI_OUT_OF_RESOURCES No memory resource for new driver instance.\r
+ @retval other Some error occurred when locating gEfiLoadedImageProtocolGuid.\r
+\r
**/\r
EFI_STATUS\r
AddDriver (\r
\r
\r
/**\r
- Get a overriding driver image.\r
- @param This Pointer to instance of EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL.\r
- @param DriverImageHandle Override driver image.\r
- \r
- @retval EFI_SUCCESS Success to get driver image handle.\r
- @retval EFI_NOT_FOUND can not find override driver image.\r
- @retval EFI_INVALID_PARAMETER Invalid parameter.\r
+ Uses a bus specific algorithm to retrieve a driver image handle for a controller.\r
+\r
+ @param This A pointer to the EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL instance.\r
+ @param DriverImageHandle On input, a pointer to the previous driver image handle returned\r
+ by GetDriver(). On output, a pointer to the next driver\r
+ image handle. Passing in a NULL, will return the first driver\r
+ image handle.\r
+\r
+ @retval EFI_SUCCESS A bus specific override driver is returned in DriverImageHandle.\r
+ @retval EFI_NOT_FOUND The end of the list of override drivers was reached.\r
+ A bus specific override driver is not returned in DriverImageHandle.\r
+ @retval EFI_INVALID_PARAMETER DriverImageHandle is not a handle that was returned on a\r
+ previous call to GetDriver().\r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
/** @file\r
+ PCI eunmeration implementation on entire PCI bus system for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2009, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
\r
-**/\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
+**/\r
\r
#include "PciBus.h"\r
-#include "PciEnumerator.h"\r
-#include "PciOptionRomSupport.h"\r
\r
/**\r
This routine is used to enumerate entire pci bus system\r
in a given platform.\r
\r
@param Controller Parent controller handle.\r
- \r
- @return Status of enumerating.\r
+\r
+ @retval EFI_SUCCESS PCI enumeration finished successfully.\r
+ @retval other Some error occurred when enumerating the pci bus system.\r
+\r
**/\r
EFI_STATUS\r
PciEnumerator (\r
}\r
\r
/**\r
- Enumerate PCI root bridge\r
- \r
+ Enumerate PCI root bridge.\r
+\r
@param PciResAlloc Pointer to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
@param RootBridgeDev Instance of root bridge device.\r
- \r
- @retval EFI_SUCCESS Success to enumerate root bridge.\r
- @retval Others Fail to enumerate root bridge.\r
- \r
+\r
+ @retval EFI_SUCCESS Successfully enumerated root bridge.\r
+ @retval other Failed to enumerate root bridge.\r
+\r
**/\r
EFI_STATUS\r
PciRootBridgeEnumerator (\r
// Reset all assigned PCI bus number\r
//\r
ResetAllPpbBusNumber (\r
- RootBridgeDev, \r
+ RootBridgeDev,\r
StartBusNumber\r
);\r
\r
RootBridgeHandle,\r
Configuration\r
);\r
- \r
+\r
FreePool (Configuration);\r
- \r
+\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
}\r
\r
/**\r
- This routine is used to process option rom on a certain root bridge\r
- \r
- @param Bridge Given parent's root bridge\r
- @param RomBase Base address of ROM driver loaded from\r
- @param MaxLength Max rom size\r
- \r
- @retval EFI_SUCCESS Success to process option rom image.\r
+ This routine is used to process all PCI devices' Option Rom\r
+ on a certain root bridge.\r
+\r
+ @param Bridge Given parent's root bridge.\r
+ @param RomBase Base address of ROM driver loaded from.\r
+ @param MaxLength Maximum rom size.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
ProcessOptionRom (\r
IN PCI_IO_DEVICE *Bridge,\r
IN UINT64 RomBase,\r
\r
CurrentLink = CurrentLink->ForwardLink;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
This routine is used to assign bus number to the given PCI bus system\r
- \r
- @param Bridge Parent root bridge instance.\r
- @param StartBusNumber Number of beginning.\r
- @param SubBusNumber the number of sub bus.\r
- \r
- @retval EFI_SUCCESS Success to assign bus number.\r
+\r
+ @param Bridge Parent root bridge instance.\r
+ @param StartBusNumber Number of beginning.\r
+ @param SubBusNumber The number of sub bus.\r
+\r
+ @retval EFI_SUCCESS Successfully assigned bus number.\r
+ @retval EFI_DEVICE_ERROR Failed to assign bus number.\r
+\r
**/\r
EFI_STATUS\r
PciAssignBusNumber (\r
//\r
// Check to see whether a pci device is present\r
//\r
-\r
Status = PciDevicePresent (\r
PciRootBridgeIo,\r
&Pci,\r
//\r
// Set the current maximum bus number under the PPB\r
//\r
-\r
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
\r
Status = PciRootBridgeIoWrite (\r
//\r
// Skip sub functions, this is not a multi function device\r
//\r
-\r
Func = PCI_MAX_FUNC;\r
}\r
}\r
\r
@param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
@param RootBridgeDev Root bridge instance\r
- \r
- @retval EFI_SUCCESS Success to get root bridge's attribute\r
- @retval Others Fail to get attribute\r
+\r
+ @retval EFI_SUCCESS Successfully got root bridge's attribute.\r
+ @retval other Failed to get attribute.\r
+\r
**/\r
EFI_STATUS\r
DetermineRootBridgeAttributes (\r
// Here is the point where PCI bus driver calls HOST bridge allocation protocol\r
// Currently we hardcoded for ea815\r
//\r
-\r
if ((Attributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) {\r
RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED;\r
}\r
}\r
\r
/**\r
- Get Max Option Rom size on this bridge\r
- \r
- @param Bridge Bridge device instance.\r
- @return Max size of option rom.\r
+ Get Max Option Rom size on specified bridge.\r
+\r
+ @param Bridge Given bridge device instance.\r
+\r
+ @return Max size of option rom needed.\r
+\r
**/\r
UINT64\r
GetMaxOptionRomSize (\r
\r
/**\r
Process attributes of devices on this host bridge\r
- \r
+\r
@param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
- \r
+\r
+ @retval EFI_SUCCESS Successfully process attribute.\r
@retval EFI_NOT_FOUND Can not find the specific root bridge device.\r
- @retval EFI_SUCCESS Success Process attribute.\r
- @retval Others Can not determine the root bridge device's attribute.\r
+ @retval other Failed to determine the root bridge device's attribute.\r
+\r
**/\r
EFI_STATUS\r
PciHostBridgeDeviceAttribute (\r
}\r
\r
/**\r
- Get resource allocation status from the ACPI pointer\r
-\r
- @param AcpiConfig Point to Acpi configuration table\r
- @param IoResStatus Return the status of I/O resource\r
- @param Mem32ResStatus Return the status of 32-bit Memory resource\r
- @param PMem32ResStatus Return the status of 32-bit PMemory resource\r
- @param Mem64ResStatus Return the status of 64-bit Memory resource\r
- @param PMem64ResStatus Return the status of 64-bit PMemory resource\r
- \r
- @retval EFI_SUCCESS Success to get resource allocation status from ACPI configuration table.\r
+ Get resource allocation status from the ACPI resource descriptor.\r
+\r
+ @param AcpiConfig Point to Acpi configuration table.\r
+ @param IoResStatus Return the status of I/O resource.\r
+ @param Mem32ResStatus Return the status of 32-bit Memory resource.\r
+ @param PMem32ResStatus Return the status of 32-bit Prefetchable Memory resource.\r
+ @param Mem64ResStatus Return the status of 64-bit Memory resource.\r
+ @param PMem64ResStatus Return the status of 64-bit Prefetchable Memory resource.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
GetResourceAllocationStatus (\r
VOID *AcpiConfig,\r
OUT UINT64 *IoResStatus,\r
OUT UINT64 *PMem64ResStatus\r
)\r
{\r
-\r
UINT8 *Temp;\r
UINT64 ResStatus;\r
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ACPIAddressDesc;\r
\r
Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
- Remove a PCI device from device pool and mark its bar\r
- \r
+ Remove a PCI device from device pool and mark its bar.\r
+\r
@param PciDevice Instance of Pci device.\r
- \r
- @retval EFI_SUCCESS Success Operation.\r
- @retval EFI_ABORTED Pci device is a root bridge.\r
+\r
+ @retval EFI_SUCCESS Successfully remove the PCI device.\r
+ @retval EFI_ABORTED Pci device is a root bridge or a PCI-PCI bridge.\r
+\r
**/\r
EFI_STATUS\r
RejectPciDevice (\r
//\r
// Remove the padding resource from a bridge\r
//\r
- if ( IS_PCI_BRIDGE(&PciDevice->Pci) && \r
+ if ( IS_PCI_BRIDGE(&PciDevice->Pci) &&\r
PciDevice->ResourcePaddingDescriptors != NULL ) {\r
FreePool (PciDevice->ResourcePaddingDescriptors);\r
PciDevice->ResourcePaddingDescriptors = NULL;\r
\r
/**\r
Determine whethter a PCI device can be rejected.\r
- \r
- @param PciResNode Pointer to Pci resource node instance.\r
- \r
- @return whethter a PCI device can be rejected.\r
+\r
+ @param PciResNode Pointer to Pci resource node instance.\r
+\r
+ @retval TRUE The PCI device can be rejected.\r
+ @retval TRUE The PCI device cannot be rejected.\r
+\r
**/\r
BOOLEAN\r
IsRejectiveDevice (\r
}\r
\r
/**\r
- Compare two resource node and get the larger resource consumer\r
- \r
+ Compare two resource nodes and get the larger resource consumer.\r
+\r
@param PciResNode1 resource node 1 want to be compared\r
@param PciResNode2 resource node 2 want to be compared\r
- \r
- @return Larger resource consumer.\r
+\r
+ @return Larger resource node.\r
+\r
**/\r
PCI_RESOURCE_NODE *\r
GetLargerConsumerDevice (\r
}\r
\r
return PciResNode2;\r
-\r
}\r
\r
\r
/**\r
Get the max resource consumer in the host resource pool.\r
- \r
+\r
@param ResPool Pointer to resource pool node.\r
- \r
- @return the max resource consumer in the host resource pool.\r
+\r
+ @return The max resource consumer in the host resource pool.\r
+\r
**/\r
PCI_RESOURCE_NODE *\r
GetMaxResourceConsumerDevice (\r
\r
/**\r
Adjust host bridge allocation so as to reduce resource requirement\r
- \r
+\r
@param IoPool Pointer to instance of I/O resource Node.\r
@param Mem32Pool Pointer to instance of 32-bit memory resource Node.\r
- @param PMem32Pool Pointer to instance of 32-bit Pmemory resource node.\r
+ @param PMem32Pool Pointer to instance of 32-bit Prefetchable memory resource node.\r
@param Mem64Pool Pointer to instance of 64-bit memory resource node.\r
- @param PMem64Pool Pointer to instance of 64-bit Pmemory resource node.\r
+ @param PMem64Pool Pointer to instance of 64-bit Prefetchable memory resource node.\r
@param IoResStatus Status of I/O resource Node.\r
@param Mem32ResStatus Status of 32-bit memory resource Node.\r
- @param PMem32ResStatus Status of 32-bit Pmemory resource node.\r
+ @param PMem32ResStatus Status of 32-bit Prefetchable memory resource node.\r
@param Mem64ResStatus Status of 64-bit memory resource node.\r
- @param PMem64ResStatus Status of 64-bit Pmemory resource node.\r
+ @param PMem64ResStatus Status of 64-bit Prefetchable memory resource node.\r
+\r
+ @retval EFI_SUCCESS Successfully adjusted resoruce on host bridge.\r
+ @retval EFI_ABORTED Host bridge hasn't this resource type or no resource be adjusted.\r
+\r
**/\r
EFI_STATUS\r
PciHostBridgeAdjustAllocation (\r
\r
if (ResStatus[ResType] == EFI_RESOURCE_NOT_SATISFIED) {\r
//\r
- // Hostbridge hasn't this resource type\r
+ // Host bridge hasn't this resource type\r
//\r
return EFI_ABORTED;\r
}\r
/**\r
Summary requests for all resource type, and contruct ACPI resource\r
requestor instance.\r
- \r
+\r
@param Bridge detecting bridge\r
@param IoNode Pointer to instance of I/O resource Node\r
@param Mem32Node Pointer to instance of 32-bit memory resource Node\r
@param Mem64Node Pointer to instance of 64-bit memory resource node\r
@param PMem64Node Pointer to instance of 64-bit Pmemory resource node\r
@param Config Output buffer holding new constructed APCI resource requestor\r
+\r
+ @retval EFI_SUCCESS Successfully constructed ACPI resource.\r
+ @retval EFI_OUT_OF_RESOURCES No memory availabe.\r
+\r
**/\r
EFI_STATUS\r
ConstructAcpiResourceRequestor (\r
\r
/**\r
Get resource base from an acpi configuration descriptor.\r
- \r
- @param Config an acpi configuration descriptor.\r
- @param IoBase output of I/O resource base address.\r
- @param Mem32Base output of 32-bit memory base address.\r
- @param PMem32Base output of 32-bit pmemory base address.\r
- @param Mem64Base output of 64-bit memory base address.\r
- @param PMem64Base output of 64-bit pmemory base address.\r
- \r
- @return EFI_SUCCESS Get resource base address successfully.\r
+\r
+ @param Config An acpi configuration descriptor.\r
+ @param IoBase Output of I/O resource base address.\r
+ @param Mem32Base Output of 32-bit memory base address.\r
+ @param PMem32Base Output of 32-bit prefetchable memory base address.\r
+ @param Mem64Base Output of 64-bit memory base address.\r
+ @param PMem64Base Output of 64-bit prefetchable memory base address.\r
\r
**/\r
-EFI_STATUS\r
+VOID\r
GetResourceBase (\r
IN VOID *Config,\r
OUT UINT64 *IoBase,\r
//\r
Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
Enumerate pci bridge, allocate resource and determine attribute\r
- for devices on this bridge\r
- \r
- @param BridgeDev Pointer to instance of bridge device.\r
- \r
- @retval EFI_SUCCESS Success operation.\r
- @retval Others Fail to enumerate.\r
+ for devices on this bridge.\r
+\r
+ @param BridgeDev Pointer to instance of bridge device.\r
+\r
+ @retval EFI_SUCCESS Successfully enumerated PCI bridge.\r
+ @retval other Failed to enumerate.\r
+\r
**/\r
EFI_STATUS\r
PciBridgeEnumerator (\r
}\r
\r
/**\r
- Allocate all kinds of resource for bridge\r
- \r
- @param Bridge Pointer to bridge instance.\r
- \r
- @retval EFI_SUCCESS Success operation.\r
- @retval Others Fail to allocate resource for bridge.\r
+ Allocate all kinds of resource for PCI bridge.\r
+\r
+ @param Bridge Pointer to bridge instance.\r
+\r
+ @retval EFI_SUCCESS Successfully allocated resource for PCI bridge.\r
+ @retval other Failed to allocate resource for bridge.\r
+\r
**/\r
EFI_STATUS\r
PciBridgeResourceAllocator (\r
EFI_STATUS Status;\r
\r
IoBridge = CreateResourceNode (\r
- Bridge,\r
- 0,\r
- 0xFFF,\r
- 0,\r
- PciBarTypeIo16,\r
- PciResUsageTypical\r
- );\r
+ Bridge,\r
+ 0,\r
+ 0xFFF,\r
+ 0,\r
+ PciBarTypeIo16,\r
+ PciResUsageTypical\r
+ );\r
\r
Mem32Bridge = CreateResourceNode (\r
Bridge,\r
);\r
\r
PMem32Bridge = CreateResourceNode (\r
- Bridge,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypePMem32,\r
- PciResUsageTypical\r
- );\r
+ Bridge,\r
+ 0,\r
+ 0xFFFFF,\r
+ 0,\r
+ PciBarTypePMem32,\r
+ PciResUsageTypical\r
+ );\r
\r
Mem64Bridge = CreateResourceNode (\r
Bridge,\r
);\r
\r
PMem64Bridge = CreateResourceNode (\r
- Bridge,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypePMem64,\r
- PciResUsageTypical\r
- );\r
+ Bridge,\r
+ 0,\r
+ 0xFFFFF,\r
+ 0,\r
+ PciBarTypePMem64,\r
+ PciResUsageTypical\r
+ );\r
\r
//\r
// Create resourcemap by going through all the devices subject to this root bridge\r
//\r
- Status = CreateResourceMap (\r
- Bridge,\r
- IoBridge,\r
- Mem32Bridge,\r
- PMem32Bridge,\r
- Mem64Bridge,\r
- PMem64Bridge\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
+ CreateResourceMap (\r
+ Bridge,\r
+ IoBridge,\r
+ Mem32Bridge,\r
+ PMem32Bridge,\r
+ Mem64Bridge,\r
+ PMem64Bridge\r
+ );\r
\r
Status = GetResourceBaseFromBridge (\r
- Bridge,\r
- &IoBase,\r
- &Mem32Base,\r
- &PMem32Base,\r
- &Mem64Base,\r
- &PMem64Base\r
- );\r
+ Bridge,\r
+ &IoBase,\r
+ &Mem32Base,\r
+ &PMem32Base,\r
+ &Mem64Base,\r
+ &PMem64Base\r
+ );\r
\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
/**\r
- Get resource base address for a pci bridge device\r
- \r
- @param Bridge Given Pci driver instance.\r
- @param IoBase output for base address of I/O type resource.\r
- @param Mem32Base output for base address of 32-bit memory type resource.\r
- @param PMem32Base output for base address of 32-bit Pmemory type resource.\r
- @param Mem64Base output for base address of 64-bit memory type resource.\r
- @param PMem64Base output for base address of 64-bit Pmemory type resource.\r
- \r
- @retval EFI_SUCCESS Succes to get resource base address.\r
+ Get resource base address for a pci bridge device.\r
+\r
+ @param Bridge Given Pci driver instance.\r
+ @param IoBase Output for base address of I/O type resource.\r
+ @param Mem32Base Output for base address of 32-bit memory type resource.\r
+ @param PMem32Base Ooutput for base address of 32-bit Pmemory type resource.\r
+ @param Mem64Base Output for base address of 64-bit memory type resource.\r
+ @param PMem64Base Output for base address of 64-bit Pmemory type resource.\r
+\r
+ @retval EFI_SUCCESS Successfully got resource base address.\r
+ @retval EFI_OUT_OF_RESOURCES PCI bridge is not available.\r
+\r
**/\r
EFI_STATUS\r
GetResourceBaseFromBridge (\r
}\r
\r
/**\r
- These are the notifications from the PCI bus driver that it is about to enter a certain \r
+ These are the notifications from the PCI bus driver that it is about to enter a certain\r
phase of the PCI enumeration process.\r
\r
This member function can be used to notify the host bridge driver to perform specific actions,\r
including any chipset-specific initialization, so that the chipset is ready to enter the next phase.\r
Eight notification points are defined at this time. See belows:\r
- EfiPciHostBridgeBeginEnumeration - Resets the host bridge PCI apertures and internal data\r
+ EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data\r
structures. The PCI enumerator should issue this notification\r
before starting a fresh enumeration process. Enumeration cannot\r
be restarted after sending any other notification such as\r
EfiPciHostBridgeBeginBusAllocation.\r
- EfiPciHostBridgeBeginBusAllocation - The bus allocation phase is about to begin. No specific action is\r
+ EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is\r
required here. This notification can be used to perform any\r
chipset-specific programming.\r
- EfiPciHostBridgeEndBusAllocation - The bus allocation and bus programming phase is complete. No\r
+ EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No\r
specific action is required here. This notification can be used to\r
perform any chipset-specific programming.\r
- EfiPciHostBridgeBeginResourceAllocation - The resource allocation phase is about to begin. No specific\r
- action is required here. This notification can be used to perform\r
- any chipset-specific programming.\r
- EfiPciHostBridgeAllocateResources - Allocates resources per previously submitted requests for all the PCI\r
+ EfiPciHostBridgeBeginResourceAllocation\r
+ The resource allocation phase is about to begin. No specific\r
+ action is required here. This notification can be used to perform\r
+ any chipset-specific programming.\r
+ EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI\r
root bridges. These resource settings are returned on the next call to\r
GetProposedResources(). Before calling NotifyPhase() with a Phase of\r
- EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible for gathering I/O and memory requests for\r
+ EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible\r
+ for gathering I/O and memory requests for\r
all the PCI root bridges and submitting these requests using\r
SubmitResources(). This function pads the resource amount\r
to suit the root bridge hardware, takes care of dependencies between\r
the PCI root bridges, and calls the Global Coherency Domain (GCD)\r
with the allocation request. In the case of padding, the allocated range\r
could be bigger than what was requested.\r
- EfiPciHostBridgeSetResources - Programs the host bridge hardware to decode previously allocated\r
+ EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated\r
resources (proposed resources) for all the PCI root bridges. After the\r
hardware is programmed, reassigning resources will not be supported.\r
The bus settings are not affected.\r
- EfiPciHostBridgeFreeResources - Deallocates resources that were previously allocated for all the PCI\r
+ EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI\r
root bridges and resets the I/O and memory apertures to their initial\r
state. The bus settings are not affected. If the request to allocate\r
resources fails, the PCI enumerator can use this notification to\r
deallocate previous resources, adjust the requests, and retry\r
allocation.\r
- EfiPciHostBridgeEndResourceAllocation- The resource allocation phase is completed. No specific action is\r
+ EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is\r
required here. This notification can be used to perform any chipsetspecific\r
programming.\r
- \r
+\r
@param[in] PciResAlloc The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
@param[in] Phase The phase during enumeration\r
- \r
+\r
@retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error\r
is valid for a Phase of EfiPciHostBridgeAllocateResources if\r
SubmitResources() has not been called for one or more\r
}\r
\r
/**\r
- Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r
- stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r
- PCI controllers before enumeration.\r
-\r
- This function is called during the PCI enumeration process. No specific action is expected from this\r
- member function. It allows the host bridge driver to preinitialize individual PCI controllers before\r
- enumeration.\r
-\r
- @param Bridge Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
- @param Bus The bus number of the pci device. \r
- @param Device The device number of the pci device. \r
- @param Func The function number of the pci device. \r
- @param Phase The phase of the PCI device enumeration. \r
- \r
- @retval EFI_SUCCESS The requested parameters were returned.\r
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
- @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in\r
- EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should\r
- not enumerate this device, including its child devices if it is a PCI-to-PCI\r
- bridge.\r
+ Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r
+ stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r
+ PCI controllers before enumeration.\r
+\r
+ This function is called during the PCI enumeration process. No specific action is expected from this\r
+ member function. It allows the host bridge driver to preinitialize individual PCI controllers before\r
+ enumeration.\r
+\r
+ @param Bridge Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
+ @param Bus The bus number of the pci device.\r
+ @param Device The device number of the pci device.\r
+ @param Func The function number of the pci device.\r
+ @param Phase The phase of the PCI device enumeration.\r
+\r
+ @retval EFI_SUCCESS The requested parameters were returned.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in\r
+ EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should\r
+ not enumerate this device, including its child devices if it is a PCI-to-PCI\r
+ bridge.\r
\r
**/\r
EFI_STATUS\r
}\r
\r
/**\r
- Hot plug request notify.\r
- \r
- @param This - A pointer to the hot plug request protocol.\r
- @param Operation - The operation.\r
- @param Controller - A pointer to the controller.\r
- @param RemainingDevicePath - A pointer to the device path.\r
- @param NumberOfChildren - A the number of child handle in the ChildHandleBuffer.\r
- @param ChildHandleBuffer - A pointer to the array contain the child handle.\r
- \r
- @retval EFI_NOT_FOUND Can not find bridge according to controller handle.\r
- @retval EFI_SUCCESS Success operating.\r
+ This function allows the PCI bus driver to be notified to act as requested when a hot-plug event has\r
+ happened on the hot-plug controller. Currently, the operations include add operation and remove operation..\r
+\r
+ @param This A pointer to the hot plug request protocol.\r
+ @param Operation The operation the PCI bus driver is requested to make.\r
+ @param Controller The handle of the hot-plug controller.\r
+ @param RemainingDevicePath The remaining device path for the PCI-like hot-plug device.\r
+ @param NumberOfChildren The number of child handles.\r
+ For a add operation, it is an output parameter.\r
+ For a remove operation, it?¡¥s an input parameter.\r
+ @param ChildHandleBuffer The buffer which contains the child handles.\r
+\r
+ @retval EFI_INVALID_PARAMETER Operation is not a legal value.\r
+ Controller is NULL or not a valid handle.\r
+ NumberOfChildren is NULL.\r
+ ChildHandleBuffer is NULL while Operation is add.\r
+ @retval EFI_OUT_OF_RESOURCES There are no enough resources to start the devices.\r
+ @retval EFI_NOT_FOUND Can not find bridge according to controller handle.\r
+ @retval EFI_SUCCESS The handles for the specified device have been created or destroyed\r
+ as requested, and for an add operation, the new handles are\r
+ returned in ChildHandleBuffer.\r
**/\r
EFI_STATUS\r
EFIAPI\r
\r
/**\r
Search hostbridge according to given handle\r
- \r
- @param RootBridgeHandle - Host bridge handle.\r
\r
- @return TRUE Found.\r
- @return FALSE Not found.\r
+ @param RootBridgeHandle Host bridge handle.\r
+\r
+ @retval TRUE Found host bridge handle.\r
+ @retval FALSE Not found hot bridge handle.\r
+\r
**/\r
BOOLEAN\r
SearchHostBridgeHandle (\r
}\r
\r
/**\r
- Add host bridge handle to global variable for enumating.\r
- \r
- @param HostBridgeHandle host bridge handle.\r
+ Add host bridge handle to global variable for enumerating.\r
+\r
+ @param HostBridgeHandle Host bridge handle.\r
+\r
+ @retval EFI_SUCCESS Successfully added host bridge.\r
+ @retval EFI_ABORTED Host bridge is NULL, or given host bridge\r
+ has been in host bridge list.\r
+\r
**/\r
EFI_STATUS\r
AddHostBridgeEnumerator (\r
/** @file\r
- Header file declares all logic function for PCI bus enumeration.\r
- \r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+ PCI bus enumeration logic function declaration for PCI bus module.\r
\r
-**/\r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
+**/\r
\r
#ifndef _EFI_PCI_ENUMERATOR_H_\r
#define _EFI_PCI_ENUMERATOR_H_\r
\r
/**\r
This routine is used to enumerate entire pci bus system\r
- in a given platform\r
+ in a given platform.\r
\r
@param Controller Parent controller handle.\r
- \r
- @return Status of enumerating.\r
+\r
+ @retval EFI_SUCCESS PCI enumeration finished successfully.\r
+ @retval other Some error occurred when enumerating the pci bus system.\r
+\r
**/\r
EFI_STATUS\r
PciEnumerator (\r
);\r
\r
/**\r
- Enumerate PCI root bridge\r
- \r
- @param PciResAlloc Pointer to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ Enumerate PCI root bridge.\r
+\r
+ @param PciResAlloc Pointer to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
@param RootBridgeDev Instance of root bridge device.\r
- \r
- @retval EFI_SUCCESS Success to enumerate root bridge.\r
- @retval Others Fail to enumerate root bridge.\r
- \r
+\r
+ @retval EFI_SUCCESS Successfully enumerated root bridge.\r
+ @retval other Failed to enumerate root bridge.\r
+\r
**/\r
EFI_STATUS\r
PciRootBridgeEnumerator (\r
);\r
\r
/**\r
- This routine is used to process option rom on a certain root bridge\r
- \r
+ This routine is used to process all PCI devices' Option Rom\r
+ on a certain root bridge.\r
+\r
@param Bridge Given parent's root bridge.\r
@param RomBase Base address of ROM driver loaded from.\r
- @param MaxLength Max rom size.\r
- \r
- @retval EFI_SUCCESS Success to process option rom image.\r
+ @param MaxLength Maximum rom size.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
ProcessOptionRom (\r
IN PCI_IO_DEVICE *Bridge,\r
IN UINT64 RomBase,\r
\r
/**\r
This routine is used to assign bus number to the given PCI bus system\r
- \r
- @param Bridge Parent root bridge instance.\r
- @param StartBusNumber Number of beginning.\r
- @param SubBusNumber the number of sub bus.\r
- \r
- @retval EFI_SUCCESS Success to assign bus number.\r
+\r
+ @param Bridge Parent root bridge instance.\r
+ @param StartBusNumber Number of beginning.\r
+ @param SubBusNumber The number of sub bus.\r
+\r
+ @retval EFI_SUCCESS Successfully assigned bus number.\r
+ @retval EFI_DEVICE_ERROR Failed to assign bus number.\r
+\r
**/\r
EFI_STATUS\r
PciAssignBusNumber (\r
This routine is used to determine the root bridge attribute by interfacing\r
the host bridge resource allocation protocol.\r
\r
- @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
- @param RootBridgeDev Root bridge instance.\r
- \r
- @retval EFI_SUCCESS Success to get root bridge's attribute.\r
- @retval Others Fail to get attribute.\r
+ @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ @param RootBridgeDev Root bridge instance\r
+\r
+ @retval EFI_SUCCESS Successfully got root bridge's attribute.\r
+ @retval other Failed to get attribute.\r
+\r
**/\r
EFI_STATUS\r
DetermineRootBridgeAttributes (\r
);\r
\r
/**\r
- Get Max Option Rom size on this bridge\r
- \r
- @param Bridge Bridge device instance.\r
- @return Max size of option rom.\r
+ Get Max Option Rom size on specified bridge.\r
+\r
+ @param Bridge Given bridge device instance.\r
+\r
+ @return Max size of option rom needed.\r
+\r
**/\r
UINT64\r
GetMaxOptionRomSize (\r
\r
/**\r
Process attributes of devices on this host bridge\r
- \r
- @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
- \r
+\r
+ @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
+\r
+ @retval EFI_SUCCESS Successfully process attribute.\r
@retval EFI_NOT_FOUND Can not find the specific root bridge device.\r
- @retval EFI_SUCCESS Success Process attribute.\r
- @retval Others Can not determine the root bridge device's attribute.\r
+ @retval other Failed to determine the root bridge device's attribute.\r
+\r
**/\r
EFI_STATUS\r
PciHostBridgeDeviceAttribute (\r
);\r
\r
/**\r
- Get resource allocation status from the ACPI pointer\r
+ Get resource allocation status from the ACPI resource descriptor.\r
\r
@param AcpiConfig Point to Acpi configuration table.\r
@param IoResStatus Return the status of I/O resource.\r
@param Mem32ResStatus Return the status of 32-bit Memory resource.\r
- @param PMem32ResStatus Return the status of 32-bit PMemory resource.\r
+ @param PMem32ResStatus Return the status of 32-bit Prefetchable Memory resource.\r
@param Mem64ResStatus Return the status of 64-bit Memory resource.\r
- @param PMem64ResStatus Return the status of 64-bit PMemory resource.\r
- \r
- @retval EFI_SUCCESS Success to get resource allocation status from ACPI configuration table.\r
+ @param PMem64ResStatus Return the status of 64-bit Prefetchable Memory resource.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
GetResourceAllocationStatus (\r
VOID *AcpiConfig,\r
OUT UINT64 *IoResStatus,\r
);\r
\r
/**\r
- Remove a PCI device from device pool and mark its bar\r
- \r
+ Remove a PCI device from device pool and mark its bar.\r
+\r
@param PciDevice Instance of Pci device.\r
- \r
- @retval EFI_SUCCESS Success Operation.\r
- @retval EFI_ABORTED Pci device is a root bridge.\r
+\r
+ @retval EFI_SUCCESS Successfully remove the PCI device.\r
+ @retval EFI_ABORTED Pci device is a root bridge or a PCI-PCI bridge.\r
+\r
**/\r
EFI_STATUS\r
RejectPciDevice (\r
);\r
\r
/**\r
- Determine whethter a PCI device can be rejected\r
- \r
- @param PciResNode Pointer to Pci resource node instance.\r
- \r
- @return whethter a PCI device can be rejected.\r
+ Determine whethter a PCI device can be rejected.\r
+\r
+ @param PciResNode Pointer to Pci resource node instance.\r
+\r
+ @retval TRUE The PCI device can be rejected.\r
+ @retval TRUE The PCI device cannot be rejected.\r
+\r
**/\r
BOOLEAN\r
IsRejectiveDevice (\r
);\r
\r
/**\r
- Compare two resource node and get the larger resource consumer\r
- \r
- @param PciResNode1 resource node 1 want to be compared.\r
- @param PciResNode2 resource node 2 want to be compared.\r
- \r
- @return Larger resource consumer.\r
+ Compare two resource nodes and get the larger resource consumer.\r
+\r
+ @param PciResNode1 resource node 1 want to be compared\r
+ @param PciResNode2 resource node 2 want to be compared\r
+\r
+ @return Larger resource node.\r
+\r
**/\r
PCI_RESOURCE_NODE *\r
GetLargerConsumerDevice (\r
);\r
\r
/**\r
- Get the max resource consumer in the host resource pool\r
- \r
+ Get the max resource consumer in the host resource pool.\r
+\r
@param ResPool Pointer to resource pool node.\r
- \r
- @return the max resource consumer in the host resource pool.\r
+\r
+ @return The max resource consumer in the host resource pool.\r
+\r
**/\r
PCI_RESOURCE_NODE *\r
GetMaxResourceConsumerDevice (\r
\r
/**\r
Adjust host bridge allocation so as to reduce resource requirement\r
- \r
+\r
@param IoPool Pointer to instance of I/O resource Node.\r
@param Mem32Pool Pointer to instance of 32-bit memory resource Node.\r
- @param PMem32Pool Pointer to instance of 32-bit Pmemory resource node.\r
+ @param PMem32Pool Pointer to instance of 32-bit Prefetchable memory resource node.\r
@param Mem64Pool Pointer to instance of 64-bit memory resource node.\r
- @param PMem64Pool Pointer to instance of 64-bit Pmemory resource node.\r
+ @param PMem64Pool Pointer to instance of 64-bit Prefetchable memory resource node.\r
@param IoResStatus Status of I/O resource Node.\r
@param Mem32ResStatus Status of 32-bit memory resource Node.\r
- @param PMem32ResStatus Status of 32-bit Pmemory resource node.\r
+ @param PMem32ResStatus Status of 32-bit Prefetchable memory resource node.\r
@param Mem64ResStatus Status of 64-bit memory resource node.\r
- @param PMem64ResStatus Status of 64-bit Pmemory resource node.\r
+ @param PMem64ResStatus Status of 64-bit Prefetchable memory resource node.\r
+\r
+ @retval EFI_SUCCESS Successfully adjusted resoruce on host bridge.\r
+ @retval EFI_ABORTED Host bridge hasn't this resource type or no resource be adjusted.\r
+\r
**/\r
EFI_STATUS\r
PciHostBridgeAdjustAllocation (\r
/**\r
Summary requests for all resource type, and contruct ACPI resource\r
requestor instance.\r
- \r
- @param Bridge detecting bridge.\r
- @param IoNode Pointer to instance of I/O resource Node.\r
- @param Mem32Node Pointer to instance of 32-bit memory resource Node.\r
- @param PMem32Node Pointer to instance of 32-bit Pmemory resource node.\r
- @param Mem64Node Pointer to instance of 64-bit memory resource node.\r
- @param PMem64Node Pointer to instance of 64-bit Pmemory resource node.\r
- @param Config Output buffer holding new constructed APCI resource requestor.\r
+\r
+ @param Bridge detecting bridge\r
+ @param IoNode Pointer to instance of I/O resource Node\r
+ @param Mem32Node Pointer to instance of 32-bit memory resource Node\r
+ @param PMem32Node Pointer to instance of 32-bit Pmemory resource node\r
+ @param Mem64Node Pointer to instance of 64-bit memory resource node\r
+ @param PMem64Node Pointer to instance of 64-bit Pmemory resource node\r
+ @param Config Output buffer holding new constructed APCI resource requestor\r
+\r
+ @retval EFI_SUCCESS Successfully constructed ACPI resource.\r
+ @retval EFI_OUT_OF_RESOURCES No memory availabe.\r
+\r
**/\r
EFI_STATUS\r
ConstructAcpiResourceRequestor (\r
\r
/**\r
Get resource base from an acpi configuration descriptor.\r
- \r
- @param Config an acpi configuration descriptor.\r
- @param IoBase output of I/O resource base address.\r
- @param Mem32Base output of 32-bit memory base address.\r
- @param PMem32Base output of 32-bit pmemory base address.\r
- @param Mem64Base output of 64-bit memory base address.\r
- @param PMem64Base output of 64-bit pmemory base address.\r
- \r
- @return EFI_SUCCESS Get resource base address successfully.\r
+\r
+ @param Config An acpi configuration descriptor.\r
+ @param IoBase Output of I/O resource base address.\r
+ @param Mem32Base Output of 32-bit memory base address.\r
+ @param PMem32Base Output of 32-bit prefetchable memory base address.\r
+ @param Mem64Base Output of 64-bit memory base address.\r
+ @param PMem64Base Output of 64-bit prefetchable memory base address.\r
\r
**/\r
-EFI_STATUS\r
+VOID\r
GetResourceBase (\r
IN VOID *Config,\r
OUT UINT64 *IoBase,\r
\r
/**\r
Enumerate pci bridge, allocate resource and determine attribute\r
- for devices on this bridge\r
- \r
- @param BridgeDev Pointer to instance of bridge device.\r
- \r
- @retval EFI_SUCCESS Success operation.\r
- @retval Others Fail to enumerate.\r
+ for devices on this bridge.\r
+\r
+ @param BridgeDev Pointer to instance of bridge device.\r
+\r
+ @retval EFI_SUCCESS Successfully enumerated PCI bridge.\r
+ @retval other Failed to enumerate.\r
+\r
**/\r
EFI_STATUS\r
PciBridgeEnumerator (\r
);\r
\r
/**\r
- Allocate all kinds of resource for bridge\r
- \r
- @param Bridge Pointer to bridge instance.\r
- \r
- @retval EFI_SUCCESS Success operation.\r
- @retval Others Fail to allocate resource for bridge.\r
+ Allocate all kinds of resource for PCI bridge.\r
+\r
+ @param Bridge Pointer to bridge instance.\r
+\r
+ @retval EFI_SUCCESS Successfully allocated resource for PCI bridge.\r
+ @retval other Failed to allocate resource for bridge.\r
+\r
**/\r
EFI_STATUS\r
PciBridgeResourceAllocator (\r
);\r
\r
/**\r
- Get resource base address for a pci bridge device\r
- \r
- @param Bridge Given Pci driver instance.\r
- @param IoBase output for base address of I/O type resource.\r
- @param Mem32Base output for base address of 32-bit memory type resource.\r
- @param PMem32Base output for base address of 32-bit Pmemory type resource.\r
- @param Mem64Base output for base address of 64-bit memory type resource.\r
- @param PMem64Base output for base address of 64-bit Pmemory type resource.\r
- \r
- @retval EFI_SUCCESS Succes to get resource base address.\r
+ Get resource base address for a pci bridge device.\r
+\r
+ @param Bridge Given Pci driver instance.\r
+ @param IoBase Output for base address of I/O type resource.\r
+ @param Mem32Base Output for base address of 32-bit memory type resource.\r
+ @param PMem32Base Ooutput for base address of 32-bit Pmemory type resource.\r
+ @param Mem64Base Output for base address of 64-bit memory type resource.\r
+ @param PMem64Base Output for base address of 64-bit Pmemory type resource.\r
+\r
+ @retval EFI_SUCCESS Successfully got resource base address.\r
+ @retval EFI_OUT_OF_RESOURCES PCI bridge is not available.\r
+\r
**/\r
EFI_STATUS\r
GetResourceBaseFromBridge (\r
\r
/**\r
Process Option Rom on this host bridge\r
- \r
+\r
@param PciResAlloc Pointer to instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
- \r
+\r
@retval EFI_NOT_FOUND Can not find the root bridge instance.\r
@retval EFI_SUCCESS Success process.\r
**/\r
);\r
\r
/**\r
- These are the notifications from the PCI bus driver that it is about to enter a certain \r
+ These are the notifications from the PCI bus driver that it is about to enter a certain\r
phase of the PCI enumeration process.\r
\r
This member function can be used to notify the host bridge driver to perform specific actions,\r
including any chipset-specific initialization, so that the chipset is ready to enter the next phase.\r
Eight notification points are defined at this time. See belows:\r
- EfiPciHostBridgeBeginEnumeration - Resets the host bridge PCI apertures and internal data\r
+ EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data\r
structures. The PCI enumerator should issue this notification\r
before starting a fresh enumeration process. Enumeration cannot\r
be restarted after sending any other notification such as\r
EfiPciHostBridgeBeginBusAllocation.\r
- EfiPciHostBridgeBeginBusAllocation - The bus allocation phase is about to begin. No specific action is\r
+ EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is\r
required here. This notification can be used to perform any\r
chipset-specific programming.\r
- EfiPciHostBridgeEndBusAllocation - The bus allocation and bus programming phase is complete. No\r
+ EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No\r
specific action is required here. This notification can be used to\r
perform any chipset-specific programming.\r
- EfiPciHostBridgeBeginResourceAllocation - The resource allocation phase is about to begin. No specific\r
- action is required here. This notification can be used to perform\r
- any chipset-specific programming.\r
- EfiPciHostBridgeAllocateResources - Allocates resources per previously submitted requests for all the PCI\r
+ EfiPciHostBridgeBeginResourceAllocation\r
+ The resource allocation phase is about to begin. No specific\r
+ action is required here. This notification can be used to perform\r
+ any chipset-specific programming.\r
+ EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI\r
root bridges. These resource settings are returned on the next call to\r
GetProposedResources(). Before calling NotifyPhase() with a Phase of\r
- EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible for gathering I/O and memory requests for\r
+ EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible\r
+ for gathering I/O and memory requests for\r
all the PCI root bridges and submitting these requests using\r
SubmitResources(). This function pads the resource amount\r
to suit the root bridge hardware, takes care of dependencies between\r
the PCI root bridges, and calls the Global Coherency Domain (GCD)\r
with the allocation request. In the case of padding, the allocated range\r
could be bigger than what was requested.\r
- EfiPciHostBridgeSetResources - Programs the host bridge hardware to decode previously allocated\r
+ EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated\r
resources (proposed resources) for all the PCI root bridges. After the\r
hardware is programmed, reassigning resources will not be supported.\r
The bus settings are not affected.\r
- EfiPciHostBridgeFreeResources - Deallocates resources that were previously allocated for all the PCI\r
+ EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI\r
root bridges and resets the I/O and memory apertures to their initial\r
state. The bus settings are not affected. If the request to allocate\r
resources fails, the PCI enumerator can use this notification to\r
deallocate previous resources, adjust the requests, and retry\r
allocation.\r
- EfiPciHostBridgeEndResourceAllocation- The resource allocation phase is completed. No specific action is\r
+ EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is\r
required here. This notification can be used to perform any chipsetspecific\r
programming.\r
- \r
+\r
@param[in] PciResAlloc The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
@param[in] Phase The phase during enumeration\r
- \r
+\r
@retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error\r
is valid for a Phase of EfiPciHostBridgeAllocateResources if\r
SubmitResources() has not been called for one or more\r
);\r
\r
/**\r
- Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r
- stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r
- PCI controllers before enumeration.\r
-\r
- This function is called during the PCI enumeration process. No specific action is expected from this\r
- member function. It allows the host bridge driver to preinitialize individual PCI controllers before\r
- enumeration.\r
-\r
- @param Bridge Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
- @param Bus The bus number of the pci device. \r
- @param Device The device number of the pci device. \r
- @param Func The function number of the pci device. \r
- @param Phase The phase of the PCI device enumeration. \r
- \r
- @retval EFI_SUCCESS The requested parameters were returned.\r
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
- @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in\r
- EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should\r
+ Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r
+ stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r
+ PCI controllers before enumeration.\r
+\r
+ This function is called during the PCI enumeration process. No specific action is expected from this\r
+ member function. It allows the host bridge driver to preinitialize individual PCI controllers before\r
+ enumeration.\r
+\r
+ @param Bridge Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
+ @param Bus The bus number of the pci device.\r
+ @param Device The device number of the pci device.\r
+ @param Func The function number of the pci device.\r
+ @param Phase The phase of the PCI device enumeration.\r
+\r
+ @retval EFI_SUCCESS The requested parameters were returned.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in\r
+ EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should\r
not enumerate this device, including its child devices if it is a PCI-to-PCI\r
bridge.\r
\r
);\r
\r
/**\r
- Hot plug request notify.\r
- \r
- @param This - A pointer to the hot plug request protocol.\r
- @param Operation - The operation.\r
- @param Controller - A pointer to the controller.\r
- @param RemainingDevicePath - A pointer to the device path.\r
- @param NumberOfChildren - A the number of child handle in the ChildHandleBuffer.\r
- @param ChildHandleBuffer - A pointer to the array contain the child handle.\r
- \r
- @retval EFI_NOT_FOUND Can not find bridge according to controller handle.\r
- @retval EFI_SUCCESS Success operating.\r
+ This function allows the PCI bus driver to be notified to act as requested when a hot-plug event has\r
+ happened on the hot-plug controller. Currently, the operations include add operation and remove operation..\r
+\r
+ @param This A pointer to the hot plug request protocol.\r
+ @param Operation The operation the PCI bus driver is requested to make.\r
+ @param Controller The handle of the hot-plug controller.\r
+ @param RemainingDevicePath The remaining device path for the PCI-like hot-plug device.\r
+ @param NumberOfChildren The number of child handles.\r
+ For a add operation, it is an output parameter.\r
+ For a remove operation, it?¡¥s an input parameter.\r
+ @param ChildHandleBuffer The buffer which contains the child handles.\r
+\r
+ @retval EFI_INVALID_PARAMETER Operation is not a legal value.\r
+ Controller is NULL or not a valid handle.\r
+ NumberOfChildren is NULL.\r
+ ChildHandleBuffer is NULL while Operation is add.\r
+ @retval EFI_OUT_OF_RESOURCES There are no enough resources to start the devices.\r
+ @retval EFI_NOT_FOUND Can not find bridge according to controller handle.\r
+ @retval EFI_SUCCESS The handles for the specified device have been created or destroyed\r
+ as requested, and for an add operation, the new handles are\r
+ returned in ChildHandleBuffer.\r
**/\r
EFI_STATUS\r
EFIAPI\r
\r
/**\r
Search hostbridge according to given handle\r
- \r
- @param RootBridgeHandle - Host bridge handle.\r
\r
- @return TRUE Found.\r
- @return FALSE Not found.\r
+ @param RootBridgeHandle Host bridge handle.\r
+\r
+ @retval TRUE Found host bridge handle.\r
+ @retval FALSE Not found hot bridge handle.\r
+\r
**/\r
BOOLEAN\r
SearchHostBridgeHandle (\r
);\r
\r
/**\r
- Add host bridge handle to global variable for enumating.\r
- \r
- @param HostBridgeHandle host bridge handle.\r
+ Add host bridge handle to global variable for enumerating.\r
+\r
+ @param HostBridgeHandle Host bridge handle.\r
+\r
+ @retval EFI_SUCCESS Successfully added host bridge.\r
+ @retval EFI_ABORTED Host bridge is NULL, or given host bridge\r
+ has been in host bridge list.\r
+\r
**/\r
EFI_STATUS\r
AddHostBridgeEnumerator (\r
/** @file\r
+ PCI emumeration support functions implementation for PCI Bus module.\r
\r
Copyright (c) 2006 - 2009, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
\r
**/\r
\r
-\r
#include "PciBus.h"\r
-#include "PciEnumeratorSupport.h"\r
-#include "PciCommand.h"\r
-#include "PciIo.h"\r
\r
/**\r
This routine is used to check whether the pci device is present.\r
- \r
+\r
@param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param Pci Output buffer for PCI device structure.\r
+ @param Pci Output buffer for PCI device configuration space.\r
@param Bus PCI bus NO.\r
@param Device PCI device NO.\r
@param Func PCI Func NO.\r
- \r
- @retval EFI_NOT_FOUND device not present.\r
- @retval EFI_SUCCESS device is found.\r
+\r
+ @retval EFI_NOT_FOUND PCI device not present.\r
+ @retval EFI_SUCCESS PCI device is found.\r
+\r
**/\r
EFI_STATUS\r
PciDevicePresent (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
- PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
+ OUT PCI_TYPE00 *Pci,\r
+ IN UINT8 Bus,\r
+ IN UINT8 Device,\r
+ IN UINT8 Func\r
)\r
{\r
UINT64 Address;\r
Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
\r
//\r
- // Read the Vendor Id register\r
+ // Read the Vendor ID register\r
//\r
Status = PciRootBridgeIoRead (\r
- PciRootBridgeIo,\r
- NULL,\r
- EfiPciWidthUint32,\r
- Address,\r
- 1,\r
- Pci\r
- );\r
+ PciRootBridgeIo,\r
+ NULL,\r
+ EfiPciWidthUint32,\r
+ Address,\r
+ 1,\r
+ Pci\r
+ );\r
\r
if (!EFI_ERROR (Status) && (Pci->Hdr).VendorId != 0xffff) {\r
-\r
//\r
// Read the entire config header for the device\r
//\r
-\r
Status = PciRootBridgeIoRead (\r
- PciRootBridgeIo,\r
- NULL,\r
- EfiPciWidthUint32,\r
- Address,\r
- sizeof (PCI_TYPE00) / sizeof (UINT32),\r
- Pci\r
- );\r
+ PciRootBridgeIo,\r
+ NULL,\r
+ EfiPciWidthUint32,\r
+ Address,\r
+ sizeof (PCI_TYPE00) / sizeof (UINT32),\r
+ Pci\r
+ );\r
\r
return EFI_SUCCESS;\r
}\r
}\r
\r
/**\r
- Collect all the resource information under this root bridge\r
+ Collect all the resource information under this root bridge.\r
+\r
A database that records all the information about pci device subject to this\r
root bridge will then be created.\r
- \r
+\r
@param Bridge Parent bridge instance.\r
- @param StartBusNumber Bus number of begining. \r
+ @param StartBusNumber Bus number of begining.\r
+\r
+ @retval EFI_SUCCESS PCI device is found.\r
+ @retval other Some error occurred when reading PCI bridge information.\r
+\r
**/\r
EFI_STATUS\r
PciPciDeviceInfoCollector (\r
IN PCI_IO_DEVICE *Bridge,\r
- UINT8 StartBusNumber\r
+ IN UINT8 StartBusNumber\r
)\r
{\r
EFI_STATUS Status;\r
//\r
// Check to see whether PCI device is present\r
//\r
-\r
Status = PciDevicePresent (\r
- Bridge->PciRootBridgeIo,\r
- &Pci,\r
- (UINT8) StartBusNumber,\r
- (UINT8) Device,\r
- (UINT8) Func\r
- );\r
-\r
+ Bridge->PciRootBridgeIo,\r
+ &Pci,\r
+ (UINT8) StartBusNumber,\r
+ (UINT8) Device,\r
+ (UINT8) Func\r
+ );\r
if (!EFI_ERROR (Status)) {\r
\r
//\r
// Collect all the information about the PCI device discovered\r
//\r
Status = PciSearchDevice (\r
- Bridge,\r
- &Pci,\r
- (UINT8) StartBusNumber,\r
- Device,\r
- Func,\r
- &PciIoDevice\r
- );\r
+ Bridge,\r
+ &Pci,\r
+ (UINT8) StartBusNumber,\r
+ Device,\r
+ Func,\r
+ &PciIoDevice\r
+ );\r
\r
//\r
// Recursively scan PCI busses on the other side of PCI-PCI bridges\r
//\r
//\r
-\r
if (!EFI_ERROR (Status) && (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci))) {\r
\r
//\r
//\r
PciIo = &(PciIoDevice->PciIo);\r
\r
- Status = PciIoRead (PciIo, EfiPciIoWidthUint8, 0x19, 1, &SecBus);\r
+ Status = PciIoRead (PciIo, EfiPciIoWidthUint8, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, 1, &SecBus);\r
\r
if (EFI_ERROR (Status)) {\r
return Status;\r
// Deep enumerate the next level bus\r
//\r
Status = PciPciDeviceInfoCollector (\r
- PciIoDevice,\r
- (UINT8) (SecBus)\r
- );\r
+ PciIoDevice,\r
+ (UINT8) (SecBus)\r
+ );\r
\r
}\r
\r
}\r
\r
/**\r
- Seach required device and get PCI device info block\r
- \r
+ Seach required device and create PCI device instance.\r
+\r
@param Bridge Parent bridge instance.\r
- @param Pci Output of PCI device info block.\r
+ @param Pci Input PCI device information block.\r
@param Bus PCI bus NO.\r
@param Device PCI device NO.\r
@param Func PCI func NO.\r
- @param PciDevice output of searched PCI device instance.\r
+ @param PciDevice Output of searched PCI device instance.\r
+\r
+ @retval EFI_SUCCESS Successfully created PCI device instance.\r
+ @retval EFI_OUT_OF_RESOURCES Cannot get PCI device information.\r
+\r
**/\r
EFI_STATUS\r
PciSearchDevice (\r
}\r
\r
/**\r
- Create PCI private data for PCI device\r
- \r
- @param Bridge Parent bridge instance.\r
- @param Pci PCI bar block\r
- @param Bus PCI device Bus NO.\r
- @param Device PCI device DeviceNO.\r
- @param Func PCI device's func NO.\r
- \r
- @return new PCI device's private date structure.\r
+ Create PCI device instance for PCI device.\r
+\r
+ @param Bridge Parent bridge instance.\r
+ @param Pci Input PCI device information block.\r
+ @param Bus PCI device Bus NO.\r
+ @param Device PCI device Device NO.\r
+ @param Func PCI device's func NO.\r
+\r
+ @return Created PCI device instance.\r
+\r
**/\r
PCI_IO_DEVICE *\r
GatherDeviceInfo (\r
IN PCI_IO_DEVICE *Bridge,\r
IN PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
+ IN UINT8 Bus,\r
+ IN UINT8 Device,\r
+ IN UINT8 Func\r
)\r
{\r
UINTN Offset;\r
}\r
\r
/**\r
- Create private data for bridge device's PPB.\r
- \r
- @param Bridge Parent bridge \r
- @param Pci Pci device block\r
- @param Bus Bridge device's bus NO.\r
- @param Device Bridge device's device NO.\r
- @param Func Bridge device's func NO.\r
- \r
- @return bridge device instance.\r
+ Create PCI device instance for PCI-PCI bridge.\r
+\r
+ @param Bridge Parent bridge instance.\r
+ @param Pci Input PCI device information block.\r
+ @param Bus PCI device Bus NO.\r
+ @param Device PCI device Device NO.\r
+ @param Func PCI device's func NO.\r
+\r
+ @return Created PCI device instance.\r
+\r
**/\r
PCI_IO_DEVICE *\r
GatherPpbInfo (\r
IN PCI_IO_DEVICE *Bridge,\r
IN PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
+ IN UINT8 Bus,\r
+ IN UINT8 Device,\r
+ IN UINT8 Func\r
)\r
{\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
);\r
\r
//\r
- // test if it supports 64 memory or not\r
+ // Test if it supports 64 memory or not\r
//\r
if (!EFI_ERROR (Status)) {\r
\r
return PciIoDevice;\r
}\r
\r
+\r
/**\r
- Create private data for hotplug bridge device\r
- \r
- @param Bridge Parent bridge instance\r
- @param Pci PCI bar block\r
- @param Bus hotplug bridge device's bus NO.\r
- @param Device hotplug bridge device's device NO.\r
- @param Func hotplug bridge device's Func NO.\r
- \r
- @return hotplug bridge device instance.\r
+ Create PCI device instance for PCI Card bridge device.\r
+\r
+ @param Bridge Parent bridge instance.\r
+ @param Pci Input PCI device information block.\r
+ @param Bus PCI device Bus NO.\r
+ @param Device PCI device Device NO.\r
+ @param Func PCI device's func NO.\r
+\r
+ @return Created PCI device instance.\r
+\r
**/\r
PCI_IO_DEVICE *\r
GatherP2CInfo (\r
IN PCI_IO_DEVICE *Bridge,\r
IN PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
+ IN UINT8 Bus,\r
+ IN UINT8 Device,\r
+ IN UINT8 Func\r
)\r
{\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
// Initalize the bridge control register\r
//\r
PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED);\r
-\r
}\r
+\r
//\r
// P2C only has one bar that is in 0x10\r
//\r
}\r
\r
/**\r
- Create device path for pci deivce\r
- \r
+ Create device path for pci deivce.\r
+\r
@param ParentDevicePath Parent bridge's path.\r
@param PciIoDevice Pci device instance.\r
- \r
- @return device path protocol instance for specific pci device.\r
+\r
+ @return Device path protocol instance for specific pci device.\r
+\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
CreatePciDevicePath (\r
}\r
\r
/**\r
- Check the bar is existed or not.\r
+ Check whether the bar is existed or not.\r
\r
- @param PciIoDevice - A pointer to the PCI_IO_DEVICE.\r
- @param Offset - The offset.\r
- @param BarLengthValue - The bar length value.\r
- @param OriginalBarValue - The original bar value.\r
+ @param PciIoDevice A pointer to the PCI_IO_DEVICE.\r
+ @param Offset The offset.\r
+ @param BarLengthValue The bar length value returned.\r
+ @param OriginalBarValue The original bar value returned.\r
\r
- @retval EFI_NOT_FOUND - The bar don't exist.\r
- @retval EFI_SUCCESS - The bar exist.\r
+ @retval EFI_NOT_FOUND The bar doesn't exist.\r
+ @retval EFI_SUCCESS The bar exist.\r
\r
**/\r
EFI_STATUS\r
BarExisted (\r
- IN PCI_IO_DEVICE *PciIoDevice,\r
- IN UINTN Offset,\r
- OUT UINT32 *BarLengthValue,\r
- OUT UINT32 *OriginalBarValue\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN UINTN Offset,\r
+ OUT UINT32 *BarLengthValue,\r
+ OUT UINT32 *OriginalBarValue\r
)\r
-\r
{\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
UINT32 OriginalValue;\r
//\r
// Preserve the original value\r
//\r
-\r
PciIoRead (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);\r
\r
//\r
}\r
\r
/**\r
- Test whether the device can support attributes \r
- \r
- @param PciIoDevice Pci device instance.\r
- @param Command Command register value.\r
- @param BridgeControl Bridge control value for PPB or P2C.\r
- @param OldCommand Old command register offset.\r
- @param OldBridgeControl Old Bridge control value for PPB or P2C.\r
- \r
- @return EFI_SUCCESS.\r
+ Test whether the device can support given attributes.\r
+\r
+ @param PciIoDevice Pci device instance.\r
+ @param Command Input command register value, and\r
+ returned supported register value.\r
+ @param BridgeControl Inout bridge control value for PPB or P2C, and\r
+ returned supported bridge control value.\r
+ @param OldCommand Returned and stored old command register offset.\r
+ @param OldBridgeControl Returned and stored old Bridge control value for PPB or P2C.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
PciTestSupportedAttribute (\r
- IN PCI_IO_DEVICE *PciIoDevice,\r
- IN UINT16 *Command,\r
- IN UINT16 *BridgeControl,\r
- IN UINT16 *OldCommand,\r
- IN UINT16 *OldBridgeControl\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN OUT UINT16 *Command,\r
+ IN OUT UINT16 *BridgeControl,\r
+ OUT UINT16 *OldCommand,\r
+ OUT UINT16 *OldBridgeControl\r
)\r
{\r
EFI_TPL OldTpl;\r
*OldBridgeControl = 0;\r
*BridgeControl = 0;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
- Set the supported or current attributes of a PCI device\r
- \r
- @param PciIoDevice - Structure pointer for PCI device.\r
- @param Command - Command register value.\r
- @param BridgeControl - Bridge control value for PPB or P2C.\r
- @param Option - Make a choice of EFI_SET_SUPPORTS or EFI_SET_ATTRIBUTES.\r
- \r
+ Set the supported or current attributes of a PCI device.\r
+\r
+ @param PciIoDevice Structure pointer for PCI device.\r
+ @param Command Command register value.\r
+ @param BridgeControl Bridge control value for PPB or P2C.\r
+ @param Option Make a choice of EFI_SET_SUPPORTS or EFI_SET_ATTRIBUTES.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
PciSetDeviceAttribute (\r
IN PCI_IO_DEVICE *PciIoDevice,\r
IN UINT16 Command,\r
} else {\r
PciIoDevice->Attributes = Attributes;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
Determine if the device can support Fast Back to Back attribute.\r
- \r
+\r
@param PciIoDevice Pci device instance.\r
@param StatusIndex Status register value.\r
+\r
+ @retval EFI_SUCCESS This device support Fast Back to Back attribute.\r
+ @retval EFI_UNSUPPORTED This device doesn't support Fast Back to Back attribute.\r
+\r
**/\r
EFI_STATUS\r
GetFastBackToBackSupport (\r
} else {\r
return EFI_UNSUPPORTED;\r
}\r
-\r
}\r
\r
/**\r
It can only be used after the first full Option ROM process.\r
\r
@param PciIoDevice Pci device instance.\r
- \r
- @retval EFI_SUCCESS Success Operation.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
ProcessOptionRomLight (\r
IN PCI_IO_DEVICE *PciIoDevice\r
)\r
\r
CurrentLink = CurrentLink->ForwardLink;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
- Determine the related attributes of all devices under a Root Bridge\r
- \r
- @param PciIoDevice PCI device instance.\r
- \r
+ Determine the related attributes of all devices under a Root Bridge.\r
+\r
+ @param PciIoDevice PCI device instance.\r
+\r
**/\r
EFI_STATUS\r
DetermineDeviceAttribute (\r
UINT16 OldCommand;\r
UINT16 OldBridgeControl;\r
BOOLEAN FastB2BSupport;\r
-\r
- /*\r
- UINT8 IdePI;\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
- */\r
PCI_IO_DEVICE *Temp;\r
LIST_ENTRY *CurrentLink;\r
EFI_STATUS Status;\r
// Enable other supported attributes but not defined in PCI_IO_PROTOCOL\r
//\r
PCI_ENABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE);\r
-\r
- //\r
- // Enable IDE native mode\r
- //\r
- /*\r
- if (IS_PCI_IDE(&PciIoDevice->Pci)) {\r
-\r
- PciIo = &PciIoDevice->PciIo;\r
-\r
- PciIoRead (\r
- PciIo,\r
- EfiPciIoWidthUint8,\r
- 0x09,\r
- 1,\r
- &IdePI\r
- );\r
-\r
- //\r
- // Set native mode if it can be supported\r
- //\r
- IdePI |= (((IdePI & 0x0F) >> 1) & 0x05);\r
-\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint8,\r
- 0x09,\r
- 1,\r
- &IdePI\r
- );\r
-\r
- }\r
- */\r
}\r
\r
FastB2BSupport = TRUE;\r
}\r
\r
/**\r
- This routine is used to update the bar information for those incompatible PCI device\r
- \r
+ This routine is used to update the bar information for those incompatible PCI device.\r
+\r
@param PciIoDevice Pci device instance.\r
- @return EFI_UNSUPPORTED failed to update Pci Info.\r
+\r
+ @retval EFI_SUCCESS Successfully updated bar information.\r
+ @retval EFI_UNSUPPORTED Given PCI device doesn't belong to incompatible PCI device list.\r
+ @retval other Failed to check incompatibility device.\r
+\r
**/\r
EFI_STATUS\r
UpdatePciInfo (\r
if (Configuration != NULL) {\r
FreePool (Configuration);\r
}\r
- return Status;\r
\r
+ return EFI_SUCCESS;\r
}\r
\r
/**\r
- This routine will update the alignment with the new alignment\r
- \r
- @param Alignment old alignment.\r
- @param NewAlignment new alignment.\r
- \r
+ This routine will update the alignment with the new alignment.\r
+\r
+ @param Alignment Old alignment.\r
+ @param NewAlignment New alignment.\r
+\r
**/\r
VOID\r
SetNewAlign (\r
- IN UINT64 *Alignment,\r
- IN UINT64 NewAlignment\r
+ IN UINT64 *Alignment,\r
+ IN UINT64 NewAlignment\r
)\r
{\r
UINT64 OldAlignment;\r
}\r
\r
/**\r
- Parse PCI bar bit.\r
- \r
+ Parse PCI bar information and fill them into PCI device instance.\r
+\r
@param PciIoDevice Pci device instance.\r
- @param Offset bar offset.\r
- @param BarIndex bar index.\r
- \r
- @return next bar offset.\r
+ @param Offset Bar offset.\r
+ @param BarIndex Bar index.\r
+\r
+ @return Next bar offset.\r
+\r
**/\r
UINTN\r
PciParseBar (\r
\r
/**\r
This routine is used to initialize the bar of a PCI device.\r
- It can be called typically when a device is going to be rejected.\r
\r
@param PciIoDevice Pci device instance.\r
+\r
+ @note It can be called typically when a device is going to be rejected.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
InitializePciDevice (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
+ IN PCI_IO_DEVICE *PciIoDevice\r
)\r
{\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {\r
PciIoWrite (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne);\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
- Init PPB for bridge device\r
- \r
- @param PciIoDevice Pci device instance.\r
+ This routine is used to initialize the bar of a PCI-PCI Bridge device.\r
+\r
+ @param PciIoDevice PCI-PCI bridge device instance.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
InitializePpb (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
+ IN PCI_IO_DEVICE *PciIoDevice\r
)\r
{\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
// Force Interrupt line to zero for cards that come up randomly\r
//\r
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
- Init private data for Hotplug bridge device\r
- \r
- @param PciIoDevice hotplug bridge device.\r
+ This routine is used to initialize the bar of a PCI Card Bridge device.\r
+\r
+ @param PciIoDevice PCI Card bridge device.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
InitializeP2C (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
+ IN PCI_IO_DEVICE *PciIoDevice\r
)\r
{\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
// Force Interrupt line to zero for cards that come up randomly\r
//\r
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
Create and initiliaze general PCI I/O device instance for\r
PCI device/bridge device/hotplug bridge device.\r
- \r
+\r
@param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param Pci Pci bar block.\r
- @param Bus device Bus NO.\r
- @param Device device device NO.\r
- @param Func device func NO.\r
- \r
- @return instance of PCI device.\r
+ @param Pci Input Pci information block.\r
+ @param Bus Device Bus NO.\r
+ @param Device Device device NO.\r
+ @param Func Device func NO.\r
+\r
+ @return Instance of PCI device. NULL means no instance created.\r
+\r
**/\r
PCI_IO_DEVICE *\r
CreatePciIoDevice (\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
IN PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
+ IN UINT8 Bus,\r
+ IN UINT8 Device,\r
+ IN UINT8 Func\r
)\r
{\r
PCI_IO_DEVICE *PciIoDevice;\r
InitializePciDriverOverrideInstance (PciIoDevice);\r
InitializePciLoadFile2 (PciIoDevice);\r
\r
-\r
//\r
// Initialize the reserved resource list\r
//\r
\r
/**\r
This routine is used to enumerate entire pci bus system\r
- in a given platform\r
+ in a given platform.\r
+\r
It is only called on the second start on the same Root Bridge.\r
\r
- @param Controller Parent bridge handler.\r
- \r
- @return status of operation.\r
+ @param Controller Parent bridge handler.\r
+\r
+ @retval EFI_SUCCESS PCI enumeration finished successfully.\r
+ @retval other Some error occurred when enumerating the pci bus system.\r
+\r
**/\r
EFI_STATUS\r
PciEnumeratorLight (\r
}\r
\r
//\r
- // Record the root bridge io protocol\r
+ // Record the root bridgeio protocol\r
//\r
RootBridgeDev->PciRootBridgeIo = PciRootBridgeIo;\r
\r
}\r
\r
/**\r
- Get bus range.\r
- \r
+ Get bus range from PCI resource descriptor list.\r
+\r
@param Descriptors A pointer to the address space descriptor.\r
- @param MinBus The min bus.\r
- @param MaxBus The max bus.\r
- @param BusRange The bus range.\r
- \r
- @retval EFI_SUCCESS Success operation.\r
- @retval EFI_NOT_FOUND can not find the specific bus.\r
+ @param MinBus The min bus returned.\r
+ @param MaxBus The max bus returned.\r
+ @param BusRange The bus range returned.\r
+\r
+ @retval EFI_SUCCESS Successfully got bus range.\r
+ @retval EFI_NOT_FOUND Can not find the specific bus.\r
+\r
**/\r
EFI_STATUS\r
PciGetBusRange (\r
OUT UINT16 *BusRange\r
)\r
{\r
-\r
while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {\r
if (MinBus != NULL) {\r
@param RootBridgeDev Pci device instance.\r
\r
@retval EFI_SUCCESS This device started.\r
- \r
+ @retval other Failed to get PCI Root Bridge I/O protocol.\r
+\r
**/\r
EFI_STATUS\r
StartManagingRootBridge (\r
//\r
// Get the root bridge handle\r
//\r
- RootBridgeHandle = RootBridgeDev->Handle;\r
- PciRootBridgeIo = NULL;\r
+ RootBridgeHandle = RootBridgeDev->Handle;\r
+ PciRootBridgeIo = NULL;\r
\r
//\r
// Get the pci root bridge io protocol\r
}\r
\r
/**\r
- This routine can be used to check whether a PCI device should be rejected when light enumeration\r
+ This routine can be used to check whether a PCI device should be rejected when light enumeration.\r
\r
@param PciIoDevice Pci device instance.\r
\r
@retval TRUE This device should be rejected.\r
@retval FALSE This device shouldn't be rejected.\r
- \r
+\r
**/\r
BOOLEAN\r
IsPciDeviceRejected (\r
//\r
// IO Bar\r
//\r
-\r
Mask = 0xFFFFFFFC;\r
TestValue = TestValue & Mask;\r
if ((TestValue != 0) && (TestValue == (OldValue & Mask))) {\r
//\r
// Mem Bar\r
//\r
-\r
Mask = 0xFFFFFFF0;\r
TestValue = TestValue & Mask;\r
\r
//\r
// Test its high 32-Bit BAR\r
//\r
-\r
Status = BarExisted (PciIoDevice, BarOffset, &TestValue, &OldValue);\r
if (TestValue == OldValue) {\r
return TRUE;\r
}\r
\r
/**\r
- Reset and all bus number from specific bridge.\r
- \r
+ Reset all bus number from specific bridge.\r
+\r
@param Bridge Parent specific bridge.\r
- @param StartBusNumber start bus number.\r
+ @param StartBusNumber Start bus number.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
ResetAllPpbBusNumber (\r
IN PCI_IO_DEVICE *Bridge,\r
IN UINT8 StartBusNumber\r
}\r
}\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/** @file\r
+ PCI emumeration support functions declaration for PCI Bus module.\r
\r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
\r
-**/\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
+**/\r
\r
#ifndef _EFI_PCI_ENUMERATOR_SUPPORT_H_\r
#define _EFI_PCI_ENUMERATOR_SUPPORT_H_\r
\r
/**\r
This routine is used to check whether the pci device is present.\r
- \r
- @param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
- @param Pci Output buffer for PCI device structure\r
- @param Bus PCI bus NO\r
- @param Device PCI device NO\r
- @param Func PCI Func NO\r
- \r
- @retval EFI_NOT_FOUND device not present\r
- @retval EFI_SUCCESS device is found.\r
+\r
+ @param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param Pci Output buffer for PCI device configuration space.\r
+ @param Bus PCI bus NO.\r
+ @param Device PCI device NO.\r
+ @param Func PCI Func NO.\r
+\r
+ @retval EFI_NOT_FOUND PCI device not present.\r
+ @retval EFI_SUCCESS PCI device is found.\r
+\r
**/\r
EFI_STATUS\r
PciDevicePresent (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
- PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
+ OUT PCI_TYPE00 *Pci,\r
+ IN UINT8 Bus,\r
+ IN UINT8 Device,\r
+ IN UINT8 Func\r
);\r
\r
/**\r
- Collect all the resource information under this root bridge\r
+ Collect all the resource information under this root bridge.\r
+\r
A database that records all the information about pci device subject to this\r
root bridge will then be created.\r
- \r
- @param Bridge Parent bridge instance\r
- @param StartBusNumber Bus number of begining \r
+\r
+ @param Bridge Parent bridge instance.\r
+ @param StartBusNumber Bus number of begining.\r
+\r
+ @retval EFI_SUCCESS PCI device is found.\r
+ @retval other Some error occurred when reading PCI bridge information.\r
+\r
**/\r
EFI_STATUS\r
PciPciDeviceInfoCollector (\r
IN PCI_IO_DEVICE *Bridge,\r
- UINT8 StartBusNumber\r
+ IN UINT8 StartBusNumber\r
);\r
\r
/**\r
- Seach required device and get PCI device info block\r
- \r
- @param Bridge Parent bridge instance\r
- @param Pci Output of PCI device info block\r
+ Seach required device and create PCI device instance.\r
+\r
+ @param Bridge Parent bridge instance.\r
+ @param Pci Input PCI device information block.\r
@param Bus PCI bus NO.\r
@param Device PCI device NO.\r
@param Func PCI func NO.\r
- @param PciDevice output of searched PCI device instance\r
+ @param PciDevice Output of searched PCI device instance.\r
+\r
+ @retval EFI_SUCCESS Successfully created PCI device instance.\r
+ @retval EFI_OUT_OF_RESOURCES Cannot get PCI device information.\r
+\r
**/\r
EFI_STATUS\r
PciSearchDevice (\r
);\r
\r
/**\r
- Create PCI private data for PCI device\r
- \r
- @param Bridge Parent bridge instance\r
- @param Pci PCI bar block\r
- @param Bus PCI device Bus NO.\r
- @param Device PCI device DeviceNO.\r
- @param Func PCI device's func NO.\r
- \r
- @return new PCI device's private date structure.\r
+ Create PCI device instance for PCI device.\r
+\r
+ @param Bridge Parent bridge instance.\r
+ @param Pci Input PCI device information block.\r
+ @param Bus PCI device Bus NO.\r
+ @param Device PCI device Device NO.\r
+ @param Func PCI device's func NO.\r
+\r
+ @return Created PCI device instance.\r
+\r
**/\r
-PCI_IO_DEVICE *\r
+PCI_IO_DEVICE *\r
GatherDeviceInfo (\r
IN PCI_IO_DEVICE *Bridge,\r
IN PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
+ IN UINT8 Bus,\r
+ IN UINT8 Device,\r
+ IN UINT8 Func\r
);\r
\r
/**\r
- Create private data for bridge device's PPB.\r
- \r
- @param Bridge Parent bridge \r
- @param Pci Pci device block\r
- @param Bus Bridge device's bus NO.\r
- @param Device Bridge device's device NO.\r
- @param Func Bridge device's func NO.\r
- \r
- @return bridge device instance.\r
+ Create PCI device instance for PCI-PCI bridge.\r
+\r
+ @param Bridge Parent bridge instance.\r
+ @param Pci Input PCI device information block.\r
+ @param Bus PCI device Bus NO.\r
+ @param Device PCI device Device NO.\r
+ @param Func PCI device's func NO.\r
+\r
+ @return Created PCI device instance.\r
+\r
**/\r
-PCI_IO_DEVICE *\r
+PCI_IO_DEVICE *\r
GatherPpbInfo (\r
IN PCI_IO_DEVICE *Bridge,\r
IN PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
+ IN UINT8 Bus,\r
+ IN UINT8 Device,\r
+ IN UINT8 Func\r
);\r
\r
/**\r
- Create private data for hotplug bridge device\r
- \r
- @param Bridge Parent bridge instance\r
- @param Pci PCI bar block\r
- @param Bus hotplug bridge device's bus NO.\r
- @param Device hotplug bridge device's device NO.\r
- @param Func hotplug bridge device's Func NO.\r
- \r
- @return hotplug bridge device instance\r
+ Create PCI device instance for PCI Card bridge device.\r
+\r
+ @param Bridge Parent bridge instance.\r
+ @param Pci Input PCI device information block.\r
+ @param Bus PCI device Bus NO.\r
+ @param Device PCI device Device NO.\r
+ @param Func PCI device's func NO.\r
+\r
+ @return Created PCI device instance.\r
+\r
**/\r
-PCI_IO_DEVICE *\r
+PCI_IO_DEVICE *\r
GatherP2CInfo (\r
IN PCI_IO_DEVICE *Bridge,\r
IN PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
+ IN UINT8 Bus,\r
+ IN UINT8 Device,\r
+ IN UINT8 Func\r
);\r
\r
/**\r
- Create device path for pci deivce\r
- \r
+ Create device path for pci deivce.\r
+\r
@param ParentDevicePath Parent bridge's path.\r
@param PciIoDevice Pci device instance.\r
- \r
+\r
@return device path protocol instance for specific pci device.\r
+\r
**/\r
-EFI_DEVICE_PATH_PROTOCOL *\r
+EFI_DEVICE_PATH_PROTOCOL *\r
CreatePciDevicePath (\r
IN EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,\r
IN PCI_IO_DEVICE *PciIoDevice\r
);\r
\r
/**\r
- Check the bar is existed or not.\r
+ Check whether the bar is existed or not.\r
\r
- @param PciIoDevice - A pointer to the PCI_IO_DEVICE.\r
- @param Offset - The offset.\r
- @param BarLengthValue - The bar length value.\r
- @param OriginalBarValue - The original bar value.\r
+ @param PciIoDevice A pointer to the PCI_IO_DEVICE.\r
+ @param Offset The offset.\r
+ @param BarLengthValue The bar length value returned.\r
+ @param OriginalBarValue The original bar value returned.\r
\r
- @retval EFI_NOT_FOUND - The bar don't exist.\r
- @retval EFI_SUCCESS - The bar exist.\r
+ @retval EFI_NOT_FOUND The bar doesn't exist.\r
+ @retval EFI_SUCCESS The bar exist.\r
\r
**/\r
EFI_STATUS\r
BarExisted (\r
- IN PCI_IO_DEVICE *PciIoDevice,\r
- IN UINTN Offset,\r
- OUT UINT32 *BarLengthValue,\r
- OUT UINT32 *OriginalBarValue\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN UINTN Offset,\r
+ OUT UINT32 *BarLengthValue,\r
+ OUT UINT32 *OriginalBarValue\r
);\r
\r
/**\r
- Test whether the device can support attributes \r
- \r
- @param PciIoDevice Pci device instance\r
- @param Command Command register value.\r
- @param BridgeControl Bridge control value for PPB or P2C.\r
- @param OldCommand Old command register offset\r
- @param OldBridgeControl Old Bridge control value for PPB or P2C.\r
- \r
- @return EFI_SUCCESS.\r
+ Test whether the device can support given attributes.\r
+\r
+ @param PciIoDevice Pci device instance.\r
+ @param Command Input command register value, and\r
+ returned supported register value.\r
+ @param BridgeControl Inout bridge control value for PPB or P2C, and\r
+ returned supported bridge control value.\r
+ @param OldCommand Returned and stored old command register offset.\r
+ @param OldBridgeControl Returned and stored old Bridge control value for PPB or P2C.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
PciTestSupportedAttribute (\r
- IN PCI_IO_DEVICE *PciIoDevice,\r
- IN UINT16 *Command,\r
- IN UINT16 *BridgeControl,\r
- IN UINT16 *OldCommand,\r
- IN UINT16 *OldBridgeControl\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN OUT UINT16 *Command,\r
+ IN OUT UINT16 *BridgeControl,\r
+ OUT UINT16 *OldCommand,\r
+ OUT UINT16 *OldBridgeControl\r
);\r
\r
/**\r
- Set the supported or current attributes of a PCI device\r
- \r
- @param PciIoDevice - Structure pointer for PCI device.\r
- @param Command - Command register value.\r
- @param BridgeControl - Bridge control value for PPB or P2C.\r
- @param Option - Make a choice of EFI_SET_SUPPORTS or EFI_SET_ATTRIBUTES.\r
- \r
+ Set the supported or current attributes of a PCI device.\r
+\r
+ @param PciIoDevice Structure pointer for PCI device.\r
+ @param Command Command register value.\r
+ @param BridgeControl Bridge control value for PPB or P2C.\r
+ @param Option Make a choice of EFI_SET_SUPPORTS or EFI_SET_ATTRIBUTES.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
PciSetDeviceAttribute (\r
IN PCI_IO_DEVICE *PciIoDevice,\r
IN UINT16 Command,\r
);\r
\r
/**\r
- Determine if the device can support Fast Back to Back attribute\r
- \r
+ Determine if the device can support Fast Back to Back attribute.\r
+\r
@param PciIoDevice Pci device instance.\r
@param StatusIndex Status register value.\r
+\r
+ @retval EFI_SUCCESS This device support Fast Back to Back attribute.\r
+ @retval EFI_UNSUPPORTED This device doesn't support Fast Back to Back attribute.\r
+\r
**/\r
EFI_STATUS\r
GetFastBackToBackSupport (\r
);\r
\r
/**\r
- Determine the related attributes of all devices under a Root Bridge\r
- \r
- @param PciIoDevice PCI device instance.\r
- \r
+ Determine the related attributes of all devices under a Root Bridge.\r
+\r
+ @param PciIoDevice PCI device instance.\r
+\r
**/\r
EFI_STATUS\r
DetermineDeviceAttribute (\r
);\r
\r
/**\r
- This routine is used to update the bar information for those incompatible PCI device\r
- \r
+ This routine is used to update the bar information for those incompatible PCI device.\r
+\r
@param PciIoDevice Pci device instance.\r
- @return EFI_UNSUPPORTED failed to update Pci Info.\r
+\r
+ @retval EFI_SUCCESS Successfully updated bar information.\r
+ @retval EFI_UNSUPPORTED Given PCI device doesn't belong to incompatible PCI device list.\r
+ @retval other Failed to check incompatibility device.\r
+\r
**/\r
EFI_STATUS\r
UpdatePciInfo (\r
);\r
\r
/**\r
- This routine will update the alignment with the new alignment\r
- \r
- @param Alignment old alignment.\r
- @param NewAlignment new alignment.\r
- \r
+ This routine will update the alignment with the new alignment.\r
+\r
+ @param Alignment Old alignment.\r
+ @param NewAlignment New alignment.\r
+\r
**/\r
VOID\r
SetNewAlign (\r
- IN UINT64 *Alignment,\r
- IN UINT64 NewAlignment\r
+ IN UINT64 *Alignment,\r
+ IN UINT64 NewAlignment\r
);\r
\r
/**\r
- Parse PCI bar bit.\r
- \r
+ Parse PCI bar information and fill them into PCI device instance.\r
+\r
@param PciIoDevice Pci device instance.\r
- @param Offset bar offset.\r
- @param BarIndex bar index.\r
- \r
- @return next bar offset.\r
+ @param Offset Bar offset.\r
+ @param BarIndex Bar index.\r
+\r
+ @return Next bar offset.\r
+\r
**/\r
UINTN\r
PciParseBar (\r
);\r
\r
/**\r
- This routine is used to initialize the bar of a PCI device\r
- It can be called typically when a device is going to be rejected.\r
+ This routine is used to initialize the bar of a PCI device.\r
\r
@param PciIoDevice Pci device instance.\r
+\r
+ @note It can be called typically when a device is going to be rejected.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
InitializePciDevice (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
+ IN PCI_IO_DEVICE *PciIoDevice\r
);\r
\r
/**\r
- Init PPB for bridge device\r
- \r
- @param PciIoDevice Pci device instance.\r
+ This routine is used to initialize the bar of a PCI-PCI Bridge device.\r
+\r
+ @param PciIoDevice PCI-PCI bridge device instance.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
InitializePpb (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
+ IN PCI_IO_DEVICE *PciIoDevice\r
);\r
\r
/**\r
- Init private data for Hotplug bridge device\r
- \r
- @param PciIoDevice hotplug bridge device.\r
+ This routine is used to initialize the bar of a PCI Card Bridge device.\r
+\r
+ @param PciIoDevice PCI Card bridge device.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
InitializeP2C (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
+ IN PCI_IO_DEVICE *PciIoDevice\r
);\r
\r
/**\r
Create and initiliaze general PCI I/O device instance for\r
PCI device/bridge device/hotplug bridge device.\r
- \r
+\r
@param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param Pci Pci bar block\r
- @param Bus device Bus NO.\r
- @param Device device device NO.\r
- @param Func device func NO.\r
- \r
- @return instance of PCI device.\r
+ @param Pci Input Pci information block.\r
+ @param Bus Device Bus NO.\r
+ @param Device Device device NO.\r
+ @param Func Device func NO.\r
+\r
+ @return Instance of PCI device. NULL means no instance created.\r
+\r
**/\r
-PCI_IO_DEVICE *\r
+PCI_IO_DEVICE *\r
CreatePciIoDevice (\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
IN PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
+ IN UINT8 Bus,\r
+ IN UINT8 Device,\r
+ IN UINT8 Func\r
);\r
\r
/**\r
This routine is used to enumerate entire pci bus system\r
- in a given platform\r
+ in a given platform.\r
+\r
It is only called on the second start on the same Root Bridge.\r
\r
- @param Controller Parent bridge handler.\r
- \r
- @return status of operation.\r
+ @param Controller Parent bridge handler.\r
+\r
+ @retval EFI_SUCCESS PCI enumeration finished successfully.\r
+ @retval other Some error occurred when enumerating the pci bus system.\r
+\r
**/\r
EFI_STATUS\r
PciEnumeratorLight (\r
);\r
\r
/**\r
- Get bus range.\r
- \r
+ Get bus range from PCI resource descriptor list.\r
+\r
@param Descriptors A pointer to the address space descriptor.\r
- @param MinBus The min bus.\r
- @param MaxBus The max bus.\r
- @param BusRange The bus range.\r
- \r
- @retval EFI_SUCCESS Success operation.\r
- @retval EFI_NOT_FOUND can not find the specific bus.\r
+ @param MinBus The min bus returned.\r
+ @param MaxBus The max bus returned.\r
+ @param BusRange The bus range returned.\r
+\r
+ @retval EFI_SUCCESS Successfully got bus range.\r
+ @retval EFI_NOT_FOUND Can not find the specific bus.\r
+\r
**/\r
EFI_STATUS\r
PciGetBusRange (\r
@param RootBridgeDev Pci device instance.\r
\r
@retval EFI_SUCCESS This device started.\r
- \r
+ @retval other Failed to get PCI Root Bridge I/O protocol.\r
+\r
**/\r
EFI_STATUS\r
StartManagingRootBridge (\r
);\r
\r
/**\r
- This routine can be used to check whether a PCI device should be rejected when light enumeration\r
+ This routine can be used to check whether a PCI device should be rejected when light enumeration.\r
\r
@param PciIoDevice Pci device instance.\r
\r
@retval TRUE This device should be rejected.\r
@retval FALSE This device shouldn't be rejected.\r
- \r
+\r
**/\r
BOOLEAN\r
IsPciDeviceRejected (\r
IN PCI_IO_DEVICE *PciIoDevice\r
);\r
\r
+/**\r
+ Reset all bus number from specific bridge.\r
+\r
+ @param Bridge Parent specific bridge.\r
+ @param StartBusNumber Start bus number.\r
+\r
+**/\r
+VOID\r
+ResetAllPpbBusNumber (\r
+ IN PCI_IO_DEVICE *Bridge,\r
+ IN UINT8 StartBusNumber\r
+ );\r
+\r
#endif\r
/** @file\r
- This module provide support function for hot plug device.\r
- \r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+ PCI Hot Plug support functions implementation for PCI Bus module..\r
\r
-**/\r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
+**/\r
\r
#include "PciBus.h"\r
-#include "PciHotPlugSupport.h"\r
\r
-EFI_PCI_HOT_PLUG_INIT_PROTOCOL *gPciHotPlugInit;\r
-EFI_HPC_LOCATION *gPciRootHpcPool;\r
-UINTN gPciRootHpcCount;\r
-ROOT_HPC_DATA *gPciRootHpcData;\r
+EFI_PCI_HOT_PLUG_INIT_PROTOCOL *gPciHotPlugInit = NULL;\r
+EFI_HPC_LOCATION *gPciRootHpcPool = NULL;\r
+UINTN gPciRootHpcCount = 0;\r
+ROOT_HPC_DATA *gPciRootHpcData = NULL;\r
+\r
\r
/**\r
- Init HPC private data.\r
- \r
- @param Event event object\r
- @param Context HPC private data.\r
+ Event notification function to set Hot Plug controller status.\r
+\r
+ @param Event The event that invoke this function.\r
+ @param Context The calling context, pointer to ROOT_HPC_DATA.\r
+\r
**/\r
VOID\r
EFIAPI\r
IN VOID *Context\r
)\r
{\r
- ROOT_HPC_DATA *HpcData;\r
+ ROOT_HPC_DATA *HpcData;\r
\r
HpcData = (ROOT_HPC_DATA *) Context;\r
HpcData->Initialized = TRUE;\r
-\r
}\r
\r
/**\r
- Compare two device path\r
- \r
- @param DevicePath1 the first device path want to be compared.\r
- @param DevicePath2 the first device path want to be compared.\r
- \r
- @retval TRUE equal.\r
- @retval FALSE different.\r
+ Compare two device pathes to check if they are exactly same.\r
+\r
+ @param DevicePath1 A pointer to the first device path data structure.\r
+ @param DevicePath2 A pointer to the second device path data structure.\r
+\r
+ @retval TRUE They are same.\r
+ @retval FALSE They are not same.\r
+\r
**/\r
BOOLEAN\r
EfiCompareDevicePath (\r
}\r
\r
/**\r
- Init hot plug support and root hot plug private data.\r
- \r
+ Check hot plug support and initialize root hot plug private data.\r
+\r
+ If Hot Plug is supported by the platform, call PCI Hot Plug Init protocol\r
+ to get PCI Hot Plug controller's information and constructor the root hot plug\r
+ private data structure.\r
+\r
+ @retval EFI_SUCCESS They are same.\r
+ @retval EFI_UNSUPPORTED No PCI Hot Plug controler on the platform.\r
+ @retval EFI_OUT_OF_RESOURCES No memory to constructor root hot plug private\r
+ data structure.\r
+\r
**/\r
EFI_STATUS\r
InitializeHotPlugSupport (\r
// hot plug controller supported on the platform\r
// the PCI Bus driver is running on. HotPlug Support\r
// is an optional feature, so absence of the protocol\r
- // won't incur the penalty\r
+ // won't incur the penalty.\r
//\r
- gPciHotPlugInit = NULL;\r
- gPciRootHpcPool = NULL;\r
- gPciRootHpcCount = 0;\r
- gPciRootHpcData = NULL;\r
-\r
Status = gBS->LocateProtocol (\r
&gEfiPciHotPlugInitProtocolGuid,\r
NULL,\r
}\r
\r
/**\r
- Test whether device path is for root pci hot plug bus\r
- \r
- @param HpbDevicePath tested device path.\r
- @param HpIndex Return the index of root hot plug in global array.\r
- \r
- @retval TRUE device path is for root pci hot plug.\r
- @retval FALSE device path is not for root pci hot plug.\r
+ Test whether device path is for root pci hot plug bus.\r
+\r
+ @param HpbDevicePath A pointer to device path data structure to be tested.\r
+ @param HpIndex If HpIndex is not NULL, return the index of root hot\r
+ plug in global array when TRUE is retuned.\r
+\r
+ @retval TRUE The device path is for root pci hot plug bus.\r
+ @retval FALSE The device path is not for root pci hot plug bus.\r
+\r
**/\r
BOOLEAN\r
IsRootPciHotPlugBus (\r
- IN EFI_DEVICE_PATH_PROTOCOL *HpbDevicePath,\r
- OUT UINTN *HpIndex\r
+ IN EFI_DEVICE_PATH_PROTOCOL *HpbDevicePath,\r
+ OUT UINTN *HpIndex OPTIONAL\r
)\r
{\r
UINTN Index;\r
}\r
\r
/**\r
- Test whether device path is for root pci hot plug controller\r
- \r
- @param HpcDevicePath tested device path.\r
- @param HpIndex Return the index of root hot plug in global array.\r
- \r
- @retval TRUE device path is for root pci hot plug controller.\r
- @retval FALSE device path is not for root pci hot plug controller.\r
+ Test whether device path is for root pci hot plug controller.\r
+\r
+ @param HpbDevicePath A pointer to device path data structure to be tested.\r
+ @param HpIndex If HpIndex is not NULL, return the index of root hot\r
+ plug in global array when TRUE is retuned.\r
+\r
+ @retval TRUE The device path is for root pci hot plug controller.\r
+ @retval FALSE The device path is not for root pci hot plug controller.\r
+\r
**/\r
BOOLEAN\r
IsRootPciHotPlugController (\r
}\r
\r
/**\r
- Wrapper for creating event object for HPC \r
- \r
- @param HpIndex index of hot plug device in global array.\r
- @param Event event object.\r
- \r
- @return status of create event invoken.\r
+ Creating event object for PCI Hot Plug controller.\r
+\r
+ @param HpIndex Index of hot plug device in global array.\r
+ @param Event The retuned event that invoke this function.\r
+\r
+ @return Status of create event invoken.\r
+\r
**/\r
EFI_STATUS\r
CreateEventForHpc (\r
- IN UINTN HpIndex,\r
+ IN UINTN HpIndex,\r
OUT EFI_EVENT *Event\r
)\r
{\r
EFI_STATUS Status;\r
\r
Status = gBS->CreateEvent (\r
- EVT_NOTIFY_SIGNAL,\r
+ EVT_NOTIFY_SIGNAL,\r
TPL_CALLBACK,\r
PciHPCInitialized,\r
gPciRootHpcData + HpIndex,\r
}\r
\r
/**\r
- Wait for all root HPC initialized.\r
- \r
- @param TimeoutInMicroSeconds microseconds to wait for all root hpc's initialization.\r
+ Wait for all root PCI Hot Plug controller finished initializing.\r
+\r
+ @param TimeoutInMicroSeconds Microseconds to wait for all root HPCs' initialization.\r
+\r
+ @retval EFI_SUCCESS All HPCs initialization finished.\r
+ @retval EFI_TIMEOUT Not ALL HPCs initialization finished in Microseconds.\r
+\r
**/\r
EFI_STATUS\r
AllRootHPCInitialized (\r
UINTN Index;\r
\r
Delay = (UINT32) ((TimeoutInMicroSeconds / 30) + 1);\r
- do {\r
\r
+ do {\r
for (Index = 0; Index < gPciRootHpcCount; Index++) {\r
\r
if (!gPciRootHpcData[Index].Initialized) {\r
}\r
\r
//\r
- // Stall for 30 us\r
+ // Stall for 30 microseconds..\r
//\r
gBS->Stall (30);\r
\r
}\r
\r
/**\r
- Check HPC capability register block\r
- \r
- @param PciIoDevice PCI device instance.\r
- \r
- @retval EFI_SUCCESS PCI device is HPC.\r
- @retval EFI_NOT_FOUND PCI device is not HPC.\r
+ Check whether PCI-PCI bridge has PCI Hot Plug capability register block.\r
+\r
+ @param PciIoDevice A Pointer to the PCI-PCI bridge.\r
+\r
+ @retval TRUE PCI device is HPC.\r
+ @retval FALSE PCI device is not HPC.\r
+\r
**/\r
-EFI_STATUS\r
+BOOLEAN\r
IsSHPC (\r
- PCI_IO_DEVICE *PciIoDevice\r
+ IN PCI_IO_DEVICE *PciIoDevice\r
)\r
{\r
\r
UINT8 Offset;\r
\r
if (PciIoDevice == NULL) {\r
- return EFI_NOT_FOUND;\r
+ return FALSE;\r
}\r
\r
Offset = 0;\r
);\r
\r
//\r
- // If the PPB has the hot plug controller build-in,\r
+ // If the PCI-PCI bridge has the hot plug controller build-in,\r
// then return TRUE;\r
//\r
if (!EFI_ERROR (Status)) {\r
- return EFI_SUCCESS;\r
+ return TRUE;\r
}\r
\r
- return EFI_NOT_FOUND;\r
+ return FALSE;\r
}\r
\r
/**\r
- Get resource padding for hot plug bus\r
- \r
- @param PciIoDevice PCI device instance\r
- \r
- @retval EFI_SUCCESS success get padding and set it into PCI device instance\r
- @retval EFI_NOT_FOUND PCI device is not a hot plug bus.\r
-**/\r
-EFI_STATUS\r
-GetResourcePaddingForHpb (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
- )\r
-/**\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
+ Get resource padding if the specified PCI bridge is a hot plug bus.\r
\r
-Returns:\r
-\r
- None\r
+ @param PciIoDevice PCI bridge instance.\r
\r
**/\r
-// TODO: PciIoDevice - add argument and description to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
-// TODO: EFI_NOT_FOUND - add return value to function comment\r
+VOID\r
+GetResourcePaddingForHpb (\r
+ IN PCI_IO_DEVICE *PciIoDevice\r
+ )\r
{\r
EFI_STATUS Status;\r
EFI_HPC_STATE State;\r
EFI_HPC_PADDING_ATTRIBUTES Attributes;\r
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
\r
- Status = IsPciHotPlugBus (PciIoDevice);\r
-\r
- if (!EFI_ERROR (Status)) {\r
+ if (IsPciHotPlugBus (PciIoDevice)) {\r
+ //\r
+ // If PCI-PCI bridge device is PCI Hot Plug bus.\r
+ //\r
PciAddress = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, 0);\r
Status = gPciHotPlugInit->GetResourcePadding (\r
gPciHotPlugInit,\r
);\r
\r
if (EFI_ERROR (Status)) {\r
- return Status;\r
+ return;\r
}\r
\r
if ((State & EFI_HPC_STATE_ENABLED) != 0 && (State & EFI_HPC_STATE_INITIALIZED) != 0) {\r
PciIoDevice->PaddingAttributes = Attributes;\r
}\r
\r
- return EFI_SUCCESS;\r
+ return;\r
}\r
-\r
- return EFI_NOT_FOUND;\r
}\r
\r
/**\r
Test whether PCI device is hot plug bus.\r
- \r
+\r
@param PciIoDevice PCI device instance.\r
- \r
- @retval EFI_SUCCESS PCI device is hot plug bus.\r
- @retval EFI_NOT_FOUND PCI device is not hot plug bus.\r
+\r
+ @retval TRUE PCI device is a hot plug bus.\r
+ @retval FALSE PCI device is not a hot plug bus.\r
+\r
**/\r
-EFI_STATUS\r
+BOOLEAN\r
IsPciHotPlugBus (\r
PCI_IO_DEVICE *PciIoDevice\r
)\r
{\r
- BOOLEAN Result;\r
- EFI_STATUS Status;\r
-\r
- Status = IsSHPC (PciIoDevice);\r
-\r
- //\r
- // If the PPB has the hot plug controller build-in,\r
- // then return TRUE;\r
- //\r
- if (!EFI_ERROR (Status)) {\r
- return EFI_SUCCESS;\r
+ if (IsSHPC (PciIoDevice)) {\r
+ //\r
+ // If the PPB has the hot plug controller build-in,\r
+ // then return TRUE;\r
+ //\r
+ return TRUE;\r
}\r
\r
//\r
// Otherwise, see if it is a Root HPC\r
//\r
- Result = IsRootPciHotPlugBus (PciIoDevice->DevicePath, NULL);\r
-\r
- if (Result) {\r
- return EFI_SUCCESS;\r
+ if(IsRootPciHotPlugBus (PciIoDevice->DevicePath, NULL)) {\r
+ return TRUE;\r
}\r
\r
- return EFI_NOT_FOUND;\r
+ return FALSE;\r
}\r
\r
/** @file\r
+ PCI Hot Plug support functions declaration for PCI Bus module.\r
\r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
\r
-**/\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
+**/\r
\r
#ifndef _EFI_PCI_HOT_PLUG_SUPPORT_H_\r
#define _EFI_PCI_HOT_PLUG_SUPPORT_H_\r
\r
-\r
//\r
-// stall 1 second\r
+// stall 1 second, its unit is 100ns\r
//\r
-#define STALL_1_SECOND 1000000 \r
+#define STALL_1_SECOND 1000000\r
\r
+//\r
+// PCI Hot Plug controller private data\r
+//\r
typedef struct {\r
EFI_EVENT Event;\r
BOOLEAN Initialized;\r
VOID *Padding;\r
} ROOT_HPC_DATA;\r
\r
+//\r
+// Reference of some global variabes\r
+//\r
extern EFI_PCI_HOT_PLUG_INIT_PROTOCOL *gPciHotPlugInit;\r
extern EFI_HPC_LOCATION *gPciRootHpcPool;\r
-extern UINTN gPciRootHpcCount;\r
extern ROOT_HPC_DATA *gPciRootHpcData;\r
\r
/**\r
- Init HPC private data.\r
- \r
- @param Event event object\r
- @param Context HPC private data.\r
+ Event notification function to set Hot Plug controller status.\r
+\r
+ @param Event The event that invoke this function.\r
+ @param Context The calling context, pointer to ROOT_HPC_DATA.\r
+\r
**/\r
VOID\r
EFIAPI\r
);\r
\r
/**\r
- Compare two device path\r
- \r
- @param DevicePath1 the first device path want to be compared.\r
- @param DevicePath2 the first device path want to be compared.\r
- \r
- @retval TRUE equal.\r
- @retval FALSE different.\r
+ Compare two device pathes to check if they are exactly same.\r
+\r
+ @param DevicePath1 A pointer to the first device path data structure.\r
+ @param DevicePath2 A pointer to the second device path data structure.\r
+\r
+ @retval TRUE They are same.\r
+ @retval FALSE They are not same.\r
+\r
**/\r
BOOLEAN\r
EfiCompareDevicePath (\r
);\r
\r
/**\r
- Init hot plug support and root hot plug private data.\r
- \r
+ Check hot plug support and initialize root hot plug private data.\r
+\r
+ If Hot Plug is supported by the platform, call PCI Hot Plug Init protocol\r
+ to get PCI Hot Plug controller's information and constructor the root hot plug\r
+ private data structure.\r
+\r
+ @retval EFI_SUCCESS They are same.\r
+ @retval EFI_UNSUPPORTED No PCI Hot Plug controler on the platform.\r
+ @retval EFI_OUT_OF_RESOURCES No memory to constructor root hot plug private\r
+ data structure.\r
+\r
**/\r
EFI_STATUS\r
InitializeHotPlugSupport (\r
\r
/**\r
Test whether PCI device is hot plug bus.\r
- \r
+\r
@param PciIoDevice PCI device instance.\r
- \r
- @retval EFI_SUCCESS PCI device is hot plug bus.\r
- @retval EFI_NOT_FOUND PCI device is not hot plug bus.\r
+\r
+ @retval TRUE PCI device is a hot plug bus.\r
+ @retval FALSE PCI device is not a hot plug bus.\r
+\r
**/\r
-EFI_STATUS\r
+BOOLEAN\r
IsPciHotPlugBus (\r
PCI_IO_DEVICE *PciIoDevice\r
);\r
\r
/**\r
- Test whether device path is for root pci hot plug bus\r
- \r
- @param HpbDevicePath tested device path\r
- @param HpIndex Return the index of root hot plug in global array.\r
- \r
- @retval TRUE device path is for root pci hot plug\r
- @retval FALSE device path is not for root pci hot plug\r
+ Test whether device path is for root pci hot plug bus.\r
+\r
+ @param HpbDevicePath A pointer to device path data structure to be tested.\r
+ @param HpIndex If HpIndex is not NULL, return the index of root hot\r
+ plug in global array when TRUE is retuned.\r
+\r
+ @retval TRUE The device path is for root pci hot plug bus.\r
+ @retval FALSE The device path is not for root pci hot plug bus.\r
+\r
**/\r
BOOLEAN\r
IsRootPciHotPlugBus (\r
- IN EFI_DEVICE_PATH_PROTOCOL *HpbDevicePath,\r
- OUT UINTN *HpIndex\r
+ IN EFI_DEVICE_PATH_PROTOCOL *HpbDevicePath,\r
+ OUT UINTN *HpIndex OPTIONAL\r
);\r
\r
/**\r
- Test whether device path is for root pci hot plug controller\r
- \r
- @param HpcDevicePath tested device path.\r
- @param HpIndex Return the index of root hot plug in global array.\r
- \r
- @retval TRUE device path is for root pci hot plug controller.\r
- @retval FALSE device path is not for root pci hot plug controller.\r
+ Test whether device path is for root pci hot plug controller.\r
+\r
+ @param HpbDevicePath A pointer to device path data structure to be tested.\r
+ @param HpIndex If HpIndex is not NULL, return the index of root hot\r
+ plug in global array when TRUE is retuned.\r
+\r
+ @retval TRUE The device path is for root pci hot plug controller.\r
+ @retval FALSE The device path is not for root pci hot plug controller.\r
+\r
**/\r
BOOLEAN\r
IsRootPciHotPlugController (\r
);\r
\r
/**\r
- Wrapper for creating event object for HPC \r
- \r
- @param HpIndex index of hot plug device in global array.\r
- @param Event event object.\r
- \r
- @return status of create event invoken.\r
+ Creating event object for PCI Hot Plug controller.\r
+\r
+ @param HpIndex Index of hot plug device in global array.\r
+ @param Event The retuned event that invoke this function.\r
+\r
+ @return Status of create event invoken.\r
+\r
**/\r
EFI_STATUS\r
CreateEventForHpc (\r
- IN UINTN HpIndex,\r
+ IN UINTN HpIndex,\r
OUT EFI_EVENT *Event\r
);\r
\r
/**\r
- Wait for all root HPC initialized.\r
- \r
- @param TimeoutInMicroSeconds microseconds to wait for all root hpc's initialization.\r
+ Wait for all root PCI Hot Plug controller finished initializing.\r
+\r
+ @param TimeoutInMicroSeconds Microseconds to wait for all root HPCs' initialization.\r
+\r
+ @retval EFI_SUCCESS All HPCs initialization finished.\r
+ @retval EFI_TIMEOUT Not ALL HPCs initialization finished in Microseconds.\r
+\r
**/\r
EFI_STATUS\r
AllRootHPCInitialized (\r
);\r
\r
/**\r
- Check HPC capability register block\r
- \r
- @param PciIoDevice PCI device instance.\r
- \r
- @retval EFI_SUCCESS PCI device is HPC.\r
- @retval EFI_NOT_FOUND PCI device is not HPC.\r
+ Check whether PCI-PCI bridge has PCI Hot Plug capability register block.\r
+\r
+ @param PciIoDevice A Pointer to the PCI-PCI bridge.\r
+\r
+ @retval TRUE PCI device is HPC.\r
+ @retval FALSE PCI device is not HPC.\r
+\r
**/\r
-EFI_STATUS\r
+BOOLEAN\r
IsSHPC (\r
- PCI_IO_DEVICE *PciIoDevice\r
+ IN PCI_IO_DEVICE *PciIoDevice\r
);\r
\r
/**\r
- Get resource padding for hot plug bus\r
- \r
- @param PciIoDevice PCI device instance.\r
- \r
- @retval EFI_SUCCESS success get padding and set it into PCI device instance.\r
- @retval EFI_NOT_FOUND PCI device is not a hot plug bus.\r
+ Get resource padding if the specified PCI bridge is a hot plug bus.\r
+\r
+ @param PciIoDevice PCI bridge instance.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
GetResourcePaddingForHpb (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
+ IN PCI_IO_DEVICE *PciIoDevice\r
);\r
\r
#endif\r
/** @file\r
- Implements all interfaces for EFI_PCI_IO_PROTOCOL.\r
- \r
-Copyright (c) 2006 - 2008, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+ EFI PCI IO protocol functions implementation for PCI Bus module.\r
\r
-**/\r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
+**/\r
\r
#include "PciBus.h"\r
\r
};\r
\r
/**\r
- report a error Status code of PCI bus driver controller.\r
- \r
- @param PciIoDevice Pci device instance.\r
- @param Code status code.\r
+ Report a error Status code of PCI bus driver controller.\r
\r
-**/\r
-EFI_STATUS\r
-ReportErrorStatusCode (\r
- IN PCI_IO_DEVICE *PciIoDevice,\r
- IN EFI_STATUS_CODE_VALUE Code\r
- );\r
-\r
-//\r
-// PCI I/O Support Function Prototypes\r
-//\r
-//\r
-\r
-/**\r
- report a error Status code of PCI bus driver controller.\r
- \r
@param PciIoDevice Pci device instance.\r
- @param Code status code.\r
+ @param Code Status code value.\r
+\r
**/\r
EFI_STATUS\r
ReportErrorStatusCode (\r
\r
/**\r
Initializes a PCI I/O Instance.\r
- \r
- @param PciIoDevice Pci device instance.\r
- \r
+\r
+ @param PciIoDevice Pci device instance.\r
+\r
**/\r
VOID\r
InitializePciIoInstance (\r
- PCI_IO_DEVICE *PciIoDevice\r
+ IN PCI_IO_DEVICE *PciIoDevice\r
)\r
{\r
CopyMem (&PciIoDevice->PciIo, &mPciIoInterface, sizeof (EFI_PCI_IO_PROTOCOL));\r
}\r
\r
/**\r
- Verifies access to a PCI Base Address Register (BAR)\r
- \r
- @param PciIoDevice Pci device instance\r
+ Verifies access to a PCI Base Address Register (BAR).\r
+\r
+ @param PciIoDevice Pci device instance.\r
@param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
- base address for the memory or I/O operation to perform. \r
- @param Type Operation type could be memory or I/O\r
+ base address for the memory or I/O operation to perform.\r
+ @param Type Operation type could be memory or I/O.\r
@param Width Signifies the width of the memory or I/O operations.\r
@param Count The number of memory or I/O operations to perform.\r
@param Offset The offset within the PCI configuration space for the PCI controller.\r
- \r
+\r
@retval EFI_INVALID_PARAMETER Invalid Width/BarIndex or Bar type.\r
- @retval EFI_SUCCESS Success Operation.\r
+ @retval EFI_SUCCESS Successfully verified.\r
+\r
**/\r
EFI_STATUS\r
PciIoVerifyBarAccess (\r
- PCI_IO_DEVICE *PciIoDevice,\r
- UINT8 BarIndex,\r
- PCI_BAR_TYPE Type,\r
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
- IN UINTN Count,\r
- UINT64 *Offset\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN UINT8 BarIndex,\r
+ IN PCI_BAR_TYPE Type,\r
+ IN IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
+ IN IN UINTN Count,\r
+ IN UINT64 *Offset\r
)\r
{\r
if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
}\r
\r
/**\r
- Verifies access to a PCI Config Header\r
- \r
- @param PciIoDevice Pci device instance\r
+ Verifies access to a PCI Configuration Header.\r
+\r
+ @param PciIoDevice Pci device instance.\r
@param Width Signifies the width of the memory or I/O operations.\r
@param Count The number of memory or I/O operations to perform.\r
@param Offset The offset within the PCI configuration space for the PCI controller.\r
\r
@retval EFI_INVALID_PARAMETER Invalid Width\r
- @retval EFI_UNSUPPORTED Offset overflow\r
- @retval EFI_SUCCESS Success operation\r
+ @retval EFI_UNSUPPORTED Offset overflowed.\r
+ @retval EFI_SUCCESS Successfully verified.\r
+\r
**/\r
EFI_STATUS\r
PciIoVerifyConfigAccess (\r
- PCI_IO_DEVICE *PciIoDevice,\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
IN UINTN Count,\r
IN UINT64 *Offset\r
}\r
\r
/**\r
- Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r
+ Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r
satisfied or after a defined duration.\r
- \r
- @param This Pointer to protocol instance of EFI_PCI_IO_PROTOCOL\r
- @param Width Signifies the width of the memory or I/O operations.\r
- @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
- base address for the memory or I/O operation to perform. \r
- @param Offset The offset within the PCI configuration space for the PCI controller.\r
- @param Mask Mask used for the polling criteria.\r
- @param Value The comparison value used for the polling exit criteria.\r
- @param Delay The number of 100 ns units to poll.\r
- @param Result Pointer to the last value read from the memory location.\r
- \r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param Width Signifies the width of the memory or I/O operations.\r
+ @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
+ base address for the memory operation to perform.\r
+ @param Offset The offset within the selected BAR to start the memory operation.\r
+ @param Mask Mask used for the polling criteria.\r
+ @param Value The comparison value used for the polling exit criteria.\r
+ @param Delay The number of 100 ns units to poll.\r
+ @param Result Pointer to the last value read from the memory location.\r
+\r
@retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
+ @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
+ @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r
@retval EFI_TIMEOUT Delay expired before a match occurred.\r
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
}\r
\r
Status = PciIoDevice->PciRootBridgeIo->PollMem (\r
- PciIoDevice->PciRootBridgeIo,\r
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
- Offset,\r
- Mask,\r
- Value,\r
- Delay,\r
- Result\r
- );\r
+ PciIoDevice->PciRootBridgeIo,\r
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
+ Offset,\r
+ Mask,\r
+ Value,\r
+ Delay,\r
+ Result\r
+ );\r
\r
if (EFI_ERROR (Status)) {\r
ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r
return Status;\r
}\r
\r
-/** \r
- Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r
+/**\r
+ Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r
satisfied or after a defined duration.\r
- \r
- @param This A pointer to the EFI_PCI_IO_PROTOCOL.\r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Width Signifies the width of the memory or I/O operations.\r
@param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
- base address for the memory or I/O operation to perform. \r
- @param Offset The offset within the selected BAR to start the memory or I/O operation. \r
+ base address for the memory operation to perform.\r
+ @param Offset The offset within the selected BAR to start the memory operation.\r
@param Mask Mask used for the polling criteria.\r
@param Value The comparison value used for the polling exit criteria.\r
@param Delay The number of 100 ns units to poll.\r
@param Result Pointer to the last value read from the memory location.\r
- \r
+\r
@retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
+ @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
+ @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r
@retval EFI_TIMEOUT Delay expired before a match occurred.\r
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
}\r
\r
Status = PciIoDevice->PciRootBridgeIo->PollIo (\r
- PciIoDevice->PciRootBridgeIo,\r
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
- Offset,\r
- Mask,\r
- Value,\r
- Delay,\r
- Result\r
- );\r
+ PciIoDevice->PciRootBridgeIo,\r
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
+ Offset,\r
+ Mask,\r
+ Value,\r
+ Delay,\r
+ Result\r
+ );\r
\r
if (EFI_ERROR (Status)) {\r
ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r
return Status;\r
}\r
\r
-/** \r
+/**\r
Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
- \r
+\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Width Signifies the width of the memory or I/O operations.\r
@param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
- base address for the memory or I/O operation to perform. \r
- @param Offset The offset within the selected BAR to start the memory or I/O operation. \r
+ base address for the memory or I/O operation to perform.\r
+ @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
@param Count The number of memory or I/O operations to perform.\r
@param Buffer For read operations, the destination buffer to store the results. For write\r
- operations, the source buffer to write data from. \r
- \r
+ operations, the source buffer to write data from.\r
+\r
@retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
@retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
- valid for the PCI BAR specified by BarIndex. \r
+ valid for the PCI BAR specified by BarIndex.\r
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
return Status;\r
}\r
\r
-/** \r
+/**\r
Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
- \r
+\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Width Signifies the width of the memory or I/O operations.\r
@param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
- base address for the memory or I/O operation to perform. \r
- @param Offset The offset within the selected BAR to start the memory or I/O operation. \r
+ base address for the memory or I/O operation to perform.\r
+ @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
@param Count The number of memory or I/O operations to perform.\r
@param Buffer For read operations, the destination buffer to store the results. For write\r
- operations, the source buffer to write data from. \r
- \r
+ operations, the source buffer to write data from.\r
+\r
@retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
@retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
- valid for the PCI BAR specified by BarIndex. \r
+ valid for the PCI BAR specified by BarIndex.\r
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
return Status;\r
}\r
\r
-/** \r
+/**\r
Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
- \r
+\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Width Signifies the width of the memory or I/O operations.\r
@param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
- base address for the memory or I/O operation to perform. \r
- @param Offset The offset within the selected BAR to start the memory or I/O operation. \r
+ base address for the memory or I/O operation to perform.\r
+ @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
@param Count The number of memory or I/O operations to perform.\r
@param Buffer For read operations, the destination buffer to store the results. For write\r
- operations, the source buffer to write data from. \r
- \r
+ operations, the source buffer to write data from.\r
+\r
@retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
@retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
- valid for the PCI BAR specified by BarIndex. \r
+ valid for the PCI BAR specified by BarIndex.\r
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
return Status;\r
}\r
\r
-/** \r
+/**\r
Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
- \r
+\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Width Signifies the width of the memory or I/O operations.\r
@param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
- base address for the memory or I/O operation to perform. \r
- @param Offset The offset within the selected BAR to start the memory or I/O operation. \r
+ base address for the memory or I/O operation to perform.\r
+ @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
@param Count The number of memory or I/O operations to perform.\r
@param Buffer For read operations, the destination buffer to store the results. For write\r
- operations, the source buffer to write data from. \r
- \r
+ operations, the source buffer to write data from.\r
+\r
@retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
@retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
- valid for the PCI BAR specified by BarIndex. \r
+ valid for the PCI BAR specified by BarIndex.\r
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
return Status;\r
}\r
\r
-/** \r
+/**\r
Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
- \r
- @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Width Signifies the width of the memory operations.\r
@param Offset The offset within the PCI configuration space for the PCI controller.\r
@param Count The number of PCI configuration operations to perform.\r
@param Buffer For read operations, the destination buffer to store the results. For write\r
operations, the source buffer to write data from.\r
- \r
- \r
+\r
+\r
@retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
valid for the PCI configuration header of the PCI controller.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. \r
- @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. \r
- \r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
return Status;\r
}\r
\r
-/** \r
+/**\r
Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
- \r
- @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Width Signifies the width of the memory operations.\r
@param Offset The offset within the PCI configuration space for the PCI controller.\r
@param Count The number of PCI configuration operations to perform.\r
@param Buffer For read operations, the destination buffer to store the results. For write\r
operations, the source buffer to write data from.\r
- \r
- \r
+\r
+\r
@retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
valid for the PCI configuration header of the PCI controller.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. \r
- @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. \r
- \r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
return Status;\r
}\r
\r
-/** \r
+/**\r
Enables a PCI driver to copy one region of PCI memory space to another region of PCI\r
memory space.\r
- \r
+\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Width Signifies the width of the memory operations.\r
@param DestBarIndex The BAR index in the standard PCI Configuration header to use as the\r
- base address for the memory operation to perform. \r
+ base address for the memory operation to perform.\r
@param DestOffset The destination offset within the BAR specified by DestBarIndex to\r
- start the memory writes for the copy operation. \r
+ start the memory writes for the copy operation.\r
@param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the\r
- base address for the memory operation to perform. \r
+ base address for the memory operation to perform.\r
@param SrcOffset The source offset within the BAR specified by SrcBarIndex to start\r
- the memory reads for the copy operation. \r
+ the memory reads for the copy operation.\r
@param Count The number of memory operations to perform. Bytes moved is Width\r
- size * Count, starting at DestOffset and SrcOffset. \r
- \r
+ size * Count, starting at DestOffset and SrcOffset.\r
+\r
@retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r
@retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.\r
@retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.\r
@retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count\r
- is not valid for the PCI BAR specified by DestBarIndex. \r
+ is not valid for the PCI BAR specified by DestBarIndex.\r
@retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is\r
- not valid for the PCI BAR specified by SrcBarIndex. \r
+ not valid for the PCI BAR specified by SrcBarIndex.\r
@retval EFI_INVALID_PARAMETER Width is invalid.\r
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
return Status;\r
}\r
\r
-/** \r
- Provides the PCI controller-Cspecific addresses needed to access system memory.\r
- \r
+/**\r
+ Provides the PCI controller-specific addresses needed to access system memory.\r
+\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Operation Indicates if the bus master is going to read or write to system memory.\r
@param HostAddress The system memory address to map to the PCI controller.\r
@param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r
- that were mapped. \r
+ that were mapped.\r
@param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
- access the hosts HostAddress. \r
+ access the hosts HostAddress.\r
@param Mapping A resulting value to pass to Unmap().\r
- \r
+\r
@retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
- @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer. \r
+ @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
@retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
return Status;\r
}\r
\r
-/** \r
+/**\r
Completes the Map() operation and releases any corresponding resources.\r
- \r
- @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Mapping The mapping value returned from Map().\r
- \r
+\r
@retval EFI_SUCCESS The range was unmapped.\r
@retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
return Status;\r
}\r
\r
-/** \r
+/**\r
Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r
- mapping. \r
- \r
+ mapping.\r
+\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Type This parameter is not used and must be ignored.\r
@param MemoryType The type of memory to allocate, EfiBootServicesData or\r
- EfiRuntimeServicesData. \r
- @param Pages The number of pages to allocate. \r
+ EfiRuntimeServicesData.\r
+ @param Pages The number of pages to allocate.\r
@param HostAddress A pointer to store the base system memory address of the\r
- allocated range. \r
+ allocated range.\r
@param Attributes The requested bit mask of attributes for the allocated range.\r
- \r
+\r
@retval EFI_SUCCESS The requested memory pages were allocated.\r
@retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
- MEMORY_WRITE_COMBINE and MEMORY_CACHED. \r
+ MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
- @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. \r
- \r
+ @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
return Status;\r
}\r
\r
-/** \r
+/**\r
Frees memory that was allocated with AllocateBuffer().\r
- \r
- @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
- @param Pages The number of pages to free. \r
- @param HostAddress The base system memory address of the allocated range. \r
- \r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param Pages The number of pages to free.\r
+ @param HostAddress The base system memory address of the allocated range.\r
+\r
@retval EFI_SUCCESS The requested memory pages were freed.\r
@retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
was not allocated with AllocateBuffer().\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
return Status;\r
}\r
\r
-/** \r
+/**\r
Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
- \r
- @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
- \r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+\r
@retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r
- bridge to system memory. \r
+ bridge to system memory.\r
@retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r
- host bridge due to a hardware error. \r
- \r
+ host bridge due to a hardware error.\r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
return Status;\r
}\r
\r
-/** \r
+/**\r
Retrieves this PCI controller's current PCI bus number, device number, and function number.\r
- \r
- @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param SegmentNumber The PCI controller's current PCI segment number.\r
@param BusNumber The PCI controller's current PCI bus number.\r
@param DeviceNumber The PCI controller's current PCI device number.\r
@param FunctionNumber The PCI controller's current PCI function number.\r
- \r
- @retval EFI_SUCCESS The PCI controller location was returned. \r
- @retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r
- \r
+\r
+ @retval EFI_SUCCESS The PCI controller location was returned.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
\r
/**\r
Check BAR type for PCI resource.\r
- \r
- @param PciIoDevice PCI device instance\r
+\r
+ @param PciIoDevice PCI device instance.\r
@param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
- base address for the memory or I/O operation to perform. \r
- @param BarType Memory or I/O\r
- \r
- @return whether Pci device's bar type is same with input BarType.\r
+ base address for the memory or I/O operation to perform.\r
+ @param BarType Memory or I/O.\r
+\r
+ @retval TRUE Pci device's bar type is same with input BarType.\r
+ @retval TRUE Pci device's bar type is not same with input BarType.\r
+\r
**/\r
BOOLEAN\r
CheckBarType (\r
- IN PCI_IO_DEVICE *PciIoDevice,\r
- UINT8 BarIndex,\r
- PCI_BAR_TYPE BarType\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN UINT8 BarIndex,\r
+ IN PCI_BAR_TYPE BarType\r
)\r
{\r
switch (BarType) {\r
}\r
\r
/**\r
- Set/Disable new attributes to a Root Bridge\r
- \r
- @param PciIoDevice Pci device instance\r
- @param Attributes New attribute want to be set\r
- @param Operation Set or Disable\r
- \r
- @retval EFI_UNSUPPORTED If root bridge does not support change attribute\r
- @retval EFI_SUCCESS Success operation.\r
+ Set/Disable new attributes to a Root Bridge.\r
+\r
+ @param PciIoDevice Pci device instance.\r
+ @param Attributes New attribute want to be set.\r
+ @param Operation Set or Disable.\r
+\r
+ @retval EFI_UNSUPPORTED If root bridge does not support change attribute.\r
+ @retval EFI_SUCCESS Successfully set new attributs.\r
+\r
**/\r
EFI_STATUS\r
ModifyRootBridgeAttributes (\r
if (EFI_ERROR (Status)) {\r
return EFI_UNSUPPORTED;\r
}\r
- \r
+\r
//\r
// Record the new attribute of the Root Bridge\r
//\r
} else {\r
NewPciRootBridgeAttributes = PciRootBridgeAttributes & (~Attributes);\r
}\r
- \r
+\r
//\r
// Call the PCI Root Bridge to attempt to modify the attributes\r
//\r
return EFI_UNSUPPORTED;\r
}\r
}\r
- \r
+\r
//\r
// Also update the attributes for this Root Bridge structure\r
//\r
PciIoDevice->Attributes = NewPciRootBridgeAttributes;\r
- return EFI_SUCCESS;\r
\r
+ return EFI_SUCCESS;\r
}\r
\r
/**\r
- Check whether this device can be enable/disable to snoop\r
- \r
- @param PciIoDevice Pci device instance\r
- @param Operation Enable/Disable\r
- \r
- @retval EFI_UNSUPPORTED Pci device is not GFX device or not support snoop\r
+ Check whether this device can be enable/disable to snoop.\r
+\r
+ @param PciIoDevice Pci device instance.\r
+ @param Operation Enable/Disable.\r
+\r
+ @retval EFI_UNSUPPORTED Pci device is not GFX device or not support snoop.\r
@retval EFI_SUCCESS Snoop can be supported.\r
+\r
**/\r
EFI_STATUS\r
SupportPaletteSnoopAttributes (\r
- IN PCI_IO_DEVICE *PciIoDevice,\r
- IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r
)\r
{\r
PCI_IO_DEVICE *Temp;\r
//\r
return EFI_SUCCESS;\r
}\r
- \r
+\r
//\r
// Check these two agents are on the same path\r
//\r
\r
return EFI_SUCCESS;\r
}\r
- \r
+\r
//\r
// If they are on the same path but on the different bus\r
// The first agent is set to snoop, the second one set to\r
// decode\r
//\r
- \r
+\r
if (Temp->BusNumber < PciIoDevice->BusNumber) {\r
//\r
// GFX should be set to decode\r
return EFI_SUCCESS;\r
}\r
\r
-/** \r
+/**\r
Performs an operation on the attributes that this PCI controller supports. The operations include\r
- getting the set of supported attributes, retrieving the current attributes, setting the current \r
- attributes, enabling attributes, and disabling attributes. \r
- \r
- @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
+ getting the set of supported attributes, retrieving the current attributes, setting the current\r
+ attributes, enabling attributes, and disabling attributes.\r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Operation The operation to perform on the attributes for this PCI controller.\r
@param Attributes The mask of attributes that are used for Set, Enable, and Disable\r
- operations. \r
+ operations.\r
@param Result A pointer to the result mask of attributes that are returned for the Get\r
- and Supported operations. \r
- \r
+ and Supported operations.\r
+\r
@retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r
- @retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r
- @retval EFI_UNSUPPORTED one or more of the bits set in \r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+ @retval EFI_UNSUPPORTED one or more of the bits set in\r
Attributes are not supported by this PCI controller or one of\r
its parent bridges when Operation is Set, Enable or Disable.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
if (Supports != Attributes) {\r
return EFI_UNSUPPORTED;\r
}\r
- \r
+\r
//\r
// For Root Bridge, just call RootBridgeIo to set attributes;\r
//\r
}\r
}\r
}\r
- \r
+\r
//\r
// Do with the attributes on GFX\r
//\r
Status = SupportPaletteSnoopAttributes (PciIoDevice, Operation);\r
\r
if (EFI_ERROR (Status)) {\r
- \r
+\r
//\r
// Enable operation is forbidden, so mask the bit in attributes\r
// so as to keep consistent with the actual Status\r
// The upstream bridge should be also set to revelant attribute\r
// expect for IO, Mem and BusMaster\r
//\r
- UpStreamAttributes = Attributes & \r
+ UpStreamAttributes = Attributes &\r
(~(EFI_PCI_IO_ATTRIBUTE_IO |\r
EFI_PCI_IO_ATTRIBUTE_MEMORY |\r
EFI_PCI_IO_ATTRIBUTE_BUS_MASTER\r
NULL\r
);\r
} else {\r
- \r
+\r
//\r
// Disable relevant attributes to command register and bridge control register\r
//\r
return Status;\r
}\r
\r
-/** \r
+/**\r
Gets the attributes that this PCI controller supports setting on a BAR using\r
SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.\r
- \r
- @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
base address for resource range. The legal range for this field is 0..5.\r
@param Supports A pointer to the mask of attributes that this PCI controller supports\r
- setting for this BAR with SetBarAttributes(). \r
+ setting for this BAR with SetBarAttributes().\r
@param Resources A pointer to the ACPI 2.0 resource descriptors that describe the current\r
- configuration of this BAR of the PCI controller. \r
- \r
- @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI \r
- controller supports are returned in Supports. If Resources \r
+ configuration of this BAR of the PCI controller.\r
+\r
+ @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI\r
+ controller supports are returned in Supports. If Resources\r
is not NULL, then the ACPI 2.0 resource descriptors that the PCI\r
- controller is currently using are returned in Resources. \r
+ controller is currently using are returned in Resources.\r
@retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
@retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
@retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate\r
- Resources. \r
- \r
+ Resources.\r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
\r
Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ((UINT8 *) Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR));\r
}\r
- \r
+\r
//\r
// put the checksum\r
//\r
return EFI_SUCCESS;\r
}\r
\r
-/** \r
+/**\r
Sets the attributes for a range of a BAR on a PCI controller.\r
- \r
- @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Attributes The mask of attributes to set for the resource range specified by\r
- BarIndex, Offset, and Length. \r
+ BarIndex, Offset, and Length.\r
@param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
base address for resource range. The legal range for this field is 0..5.\r
@param Offset A pointer to the BAR relative base address of the resource range to be\r
- modified by the attributes specified by Attributes. \r
+ modified by the attributes specified by Attributes.\r
@param Length A pointer to the length of the resource range to be modified by the\r
- attributes specified by Attributes. \r
- \r
- @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource \r
- range specified by BarIndex, Offset, and Length were \r
+ attributes specified by Attributes.\r
+\r
+ @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource\r
+ range specified by BarIndex, Offset, and Length were\r
set on the PCI controller, and the actual resource range is returned\r
- in Offset and Length. \r
+ in Offset and Length.\r
@retval EFI_INVALID_PARAMETER Offset or Length is NULL.\r
@retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
@retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the\r
- resource range specified by BarIndex, Offset, and \r
- Length. \r
- \r
+ resource range specified by BarIndex, Offset, and\r
+ Length.\r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
\r
/**\r
Program parent bridge's attribute recurrently.\r
- \r
+\r
@param PciIoDevice Child Pci device instance\r
@param Operation The operation to perform on the attributes for this PCI controller.\r
@param Attributes The mask of attributes that are used for Set, Enable, and Disable\r
operations.\r
- \r
+\r
@retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r
- @retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r
- @retval EFI_UNSUPPORTED one or more of the bits set in \r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+ @retval EFI_UNSUPPORTED one or more of the bits set in\r
Attributes are not supported by this PCI controller or one of\r
its parent bridges when Operation is Set, Enable or Disable.\r
- \r
+\r
**/\r
EFI_STATUS\r
UpStreamBridgesAttributes (\r
- IN PCI_IO_DEVICE *PciIoDevice,\r
- IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r
- IN UINT64 Attributes\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r
+ IN UINT64 Attributes\r
)\r
{\r
PCI_IO_DEVICE *Parent;\r
}\r
\r
/**\r
- Test whether two Pci device has same parent bridge.\r
- \r
- @param PciDevice1 the frist pci device for testing\r
- @param PciDevice2 the second pci device for testing\r
- \r
- @return whether two Pci device has same parent bridge.\r
+ Test whether two Pci devices has same parent bridge.\r
+\r
+ @param PciDevice1 The first pci device for testing.\r
+ @param PciDevice2 The second pci device for testing.\r
+\r
+ @retval TRUE Two Pci device has the same parent bridge.\r
+ @retval FALSE Two Pci device has not the same parent bridge.\r
+\r
**/\r
BOOLEAN\r
PciDevicesOnTheSamePath (\r
/** @file\r
- Header file of EFI PCI IO protocol.\r
+ EFI PCI IO protocol functions declaration for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2009, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
\r
-**/\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
+**/\r
\r
#ifndef _EFI_PCI_IO_PROTOCOL_H_\r
#define _EFI_PCI_IO_PROTOCOL_H_\r
\r
/**\r
Initializes a PCI I/O Instance.\r
- \r
- @param PciIoDevice Pci device instance.\r
- \r
+\r
+ @param PciIoDevice Pci device instance.\r
+\r
**/\r
VOID\r
InitializePciIoInstance (\r
- PCI_IO_DEVICE *PciIoDevice\r
+ IN PCI_IO_DEVICE *PciIoDevice\r
);\r
\r
/**\r
- Verifies access to a PCI Base Address Register (BAR)\r
- \r
- @param PciIoDevice Pci device instance\r
+ Verifies access to a PCI Base Address Register (BAR).\r
+\r
+ @param PciIoDevice Pci device instance.\r
@param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
- base address for the memory or I/O operation to perform. \r
- @param Type Operation type could be memory or I/O\r
+ base address for the memory or I/O operation to perform.\r
+ @param Type Operation type could be memory or I/O.\r
@param Width Signifies the width of the memory or I/O operations.\r
@param Count The number of memory or I/O operations to perform.\r
@param Offset The offset within the PCI configuration space for the PCI controller.\r
- \r
+\r
@retval EFI_INVALID_PARAMETER Invalid Width/BarIndex or Bar type.\r
- @retval EFI_SUCCESS Success Operation.\r
+ @retval EFI_SUCCESS Successfully verified.\r
+\r
**/\r
EFI_STATUS\r
PciIoVerifyBarAccess (\r
- PCI_IO_DEVICE *PciIoDevice,\r
- UINT8 BarIndex,\r
- PCI_BAR_TYPE Type,\r
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
- IN UINTN Count,\r
- UINT64 *Offset\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN UINT8 BarIndex,\r
+ IN PCI_BAR_TYPE Type,\r
+ IN IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
+ IN IN UINTN Count,\r
+ IN UINT64 *Offset\r
);\r
\r
/**\r
- Verifies access to a PCI Config Header\r
- \r
- @param PciIoDevice Pci device instance\r
+ Verifies access to a PCI Configuration Header.\r
+\r
+ @param PciIoDevice Pci device instance.\r
@param Width Signifies the width of the memory or I/O operations.\r
@param Count The number of memory or I/O operations to perform.\r
@param Offset The offset within the PCI configuration space for the PCI controller.\r
\r
- @retval EFI_INVALID_PARAMETER Invalid Width.\r
- @retval EFI_UNSUPPORTED Offset overflow.\r
- @retval EFI_SUCCESS Success operation.\r
+ @retval EFI_INVALID_PARAMETER Invalid Width\r
+ @retval EFI_UNSUPPORTED Offset overflowed.\r
+ @retval EFI_SUCCESS Successfully verified.\r
+\r
**/\r
EFI_STATUS\r
PciIoVerifyConfigAccess (\r
- PCI_IO_DEVICE *PciIoDevice,\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
IN UINTN Count,\r
IN UINT64 *Offset\r
);\r
\r
/**\r
- Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r
+ Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r
satisfied or after a defined duration.\r
- \r
- @param This Pointer to protocol instance of EFI_PCI_IO_PROTOCOL\r
- @param Width Signifies the width of the memory or I/O operations.\r
- @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
- base address for the memory or I/O operation to perform. \r
- @param Offset The offset within the PCI configuration space for the PCI controller.\r
- @param Mask Mask used for the polling criteria.\r
- @param Value The comparison value used for the polling exit criteria.\r
- @param Delay The number of 100 ns units to poll.\r
- @param Result Pointer to the last value read from the memory location.\r
- \r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param Width Signifies the width of the memory or I/O operations.\r
+ @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
+ base address for the memory operation to perform.\r
+ @param Offset The offset within the selected BAR to start the memory operation.\r
+ @param Mask Mask used for the polling criteria.\r
+ @param Value The comparison value used for the polling exit criteria.\r
+ @param Delay The number of 100 ns units to poll.\r
+ @param Result Pointer to the last value read from the memory location.\r
+\r
@retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
+ @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
+ @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r
@retval EFI_TIMEOUT Delay expired before a match occurred.\r
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
OUT UINT64 *Result\r
);\r
\r
-/** \r
- Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r
+/**\r
+ Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r
satisfied or after a defined duration.\r
- \r
- @param This A pointer to the EFI_PCI_IO_PROTOCOL.\r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Width Signifies the width of the memory or I/O operations.\r
@param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
- base address for the memory or I/O operation to perform. \r
- @param Offset The offset within the selected BAR to start the memory or I/O operation. \r
+ base address for the memory operation to perform.\r
+ @param Offset The offset within the selected BAR to start the memory operation.\r
@param Mask Mask used for the polling criteria.\r
@param Value The comparison value used for the polling exit criteria.\r
@param Delay The number of 100 ns units to poll.\r
@param Result Pointer to the last value read from the memory location.\r
- \r
+\r
@retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
+ @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
+ @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r
@retval EFI_TIMEOUT Delay expired before a match occurred.\r
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
OUT UINT64 *Result\r
);\r
\r
-/** \r
+/**\r
Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
- \r
+\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Width Signifies the width of the memory or I/O operations.\r
@param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
- base address for the memory or I/O operation to perform. \r
- @param Offset The offset within the selected BAR to start the memory or I/O operation. \r
+ base address for the memory or I/O operation to perform.\r
+ @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
@param Count The number of memory or I/O operations to perform.\r
@param Buffer For read operations, the destination buffer to store the results. For write\r
- operations, the source buffer to write data from. \r
- \r
+ operations, the source buffer to write data from.\r
+\r
@retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
@retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
- valid for the PCI BAR specified by BarIndex. \r
+ valid for the PCI BAR specified by BarIndex.\r
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
IN OUT VOID *Buffer\r
);\r
\r
-/** \r
+/**\r
Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
- \r
+\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Width Signifies the width of the memory or I/O operations.\r
@param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
- base address for the memory or I/O operation to perform. \r
- @param Offset The offset within the selected BAR to start the memory or I/O operation. \r
+ base address for the memory or I/O operation to perform.\r
+ @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
@param Count The number of memory or I/O operations to perform.\r
@param Buffer For read operations, the destination buffer to store the results. For write\r
- operations, the source buffer to write data from. \r
- \r
+ operations, the source buffer to write data from.\r
+\r
@retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
@retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
- valid for the PCI BAR specified by BarIndex. \r
+ valid for the PCI BAR specified by BarIndex.\r
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
IN OUT VOID *Buffer\r
);\r
\r
-/** \r
+/**\r
Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
- \r
+\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Width Signifies the width of the memory or I/O operations.\r
@param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
- base address for the memory or I/O operation to perform. \r
- @param Offset The offset within the selected BAR to start the memory or I/O operation. \r
+ base address for the memory or I/O operation to perform.\r
+ @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
@param Count The number of memory or I/O operations to perform.\r
@param Buffer For read operations, the destination buffer to store the results. For write\r
- operations, the source buffer to write data from. \r
- \r
+ operations, the source buffer to write data from.\r
+\r
@retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
@retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
- valid for the PCI BAR specified by BarIndex. \r
+ valid for the PCI BAR specified by BarIndex.\r
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
IN OUT VOID *Buffer\r
);\r
\r
-/** \r
+/**\r
Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
- \r
+\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Width Signifies the width of the memory or I/O operations.\r
@param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
- base address for the memory or I/O operation to perform. \r
- @param Offset The offset within the selected BAR to start the memory or I/O operation. \r
+ base address for the memory or I/O operation to perform.\r
+ @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
@param Count The number of memory or I/O operations to perform.\r
@param Buffer For read operations, the destination buffer to store the results. For write\r
- operations, the source buffer to write data from. \r
- \r
+ operations, the source buffer to write data from.\r
+\r
@retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
@retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
- valid for the PCI BAR specified by BarIndex. \r
+ valid for the PCI BAR specified by BarIndex.\r
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
IN OUT VOID *Buffer\r
);\r
\r
-/** \r
+/**\r
Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
- \r
- @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Width Signifies the width of the memory operations.\r
@param Offset The offset within the PCI configuration space for the PCI controller.\r
@param Count The number of PCI configuration operations to perform.\r
@param Buffer For read operations, the destination buffer to store the results. For write\r
operations, the source buffer to write data from.\r
- \r
- \r
+\r
+\r
@retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
valid for the PCI configuration header of the PCI controller.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. \r
- @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. \r
- \r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
IN OUT VOID *Buffer\r
);\r
\r
-/** \r
+/**\r
Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
- \r
- @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Width Signifies the width of the memory operations.\r
@param Offset The offset within the PCI configuration space for the PCI controller.\r
@param Count The number of PCI configuration operations to perform.\r
@param Buffer For read operations, the destination buffer to store the results. For write\r
operations, the source buffer to write data from.\r
- \r
- \r
+\r
+\r
@retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
valid for the PCI configuration header of the PCI controller.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. \r
- @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. \r
- \r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
IN OUT VOID *Buffer\r
);\r
\r
-/** \r
+/**\r
Enables a PCI driver to copy one region of PCI memory space to another region of PCI\r
memory space.\r
- \r
+\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Width Signifies the width of the memory operations.\r
@param DestBarIndex The BAR index in the standard PCI Configuration header to use as the\r
- base address for the memory operation to perform. \r
+ base address for the memory operation to perform.\r
@param DestOffset The destination offset within the BAR specified by DestBarIndex to\r
- start the memory writes for the copy operation. \r
+ start the memory writes for the copy operation.\r
@param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the\r
- base address for the memory operation to perform. \r
+ base address for the memory operation to perform.\r
@param SrcOffset The source offset within the BAR specified by SrcBarIndex to start\r
- the memory reads for the copy operation. \r
+ the memory reads for the copy operation.\r
@param Count The number of memory operations to perform. Bytes moved is Width\r
- size * Count, starting at DestOffset and SrcOffset. \r
- \r
+ size * Count, starting at DestOffset and SrcOffset.\r
+\r
@retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r
@retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.\r
@retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.\r
@retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count\r
- is not valid for the PCI BAR specified by DestBarIndex. \r
+ is not valid for the PCI BAR specified by DestBarIndex.\r
@retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is\r
- not valid for the PCI BAR specified by SrcBarIndex. \r
+ not valid for the PCI BAR specified by SrcBarIndex.\r
@retval EFI_INVALID_PARAMETER Width is invalid.\r
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
IN UINTN Count\r
);\r
\r
-/** \r
- Provides the PCI controller-Cspecific addresses needed to access system memory.\r
- \r
+/**\r
+ Provides the PCI controller-specific addresses needed to access system memory.\r
+\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Operation Indicates if the bus master is going to read or write to system memory.\r
@param HostAddress The system memory address to map to the PCI controller.\r
@param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r
- that were mapped. \r
+ that were mapped.\r
@param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
- access the hosts HostAddress. \r
+ access the hosts HostAddress.\r
@param Mapping A resulting value to pass to Unmap().\r
- \r
+\r
@retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
- @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer. \r
+ @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
@retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
OUT VOID **Mapping\r
);\r
\r
-/** \r
+/**\r
Completes the Map() operation and releases any corresponding resources.\r
- \r
- @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Mapping The mapping value returned from Map().\r
- \r
+\r
@retval EFI_SUCCESS The range was unmapped.\r
@retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
IN VOID *Mapping\r
);\r
\r
-/** \r
+/**\r
Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r
- mapping. \r
- \r
+ mapping.\r
+\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Type This parameter is not used and must be ignored.\r
@param MemoryType The type of memory to allocate, EfiBootServicesData or\r
- EfiRuntimeServicesData. \r
- @param Pages The number of pages to allocate. \r
+ EfiRuntimeServicesData.\r
+ @param Pages The number of pages to allocate.\r
@param HostAddress A pointer to store the base system memory address of the\r
- allocated range. \r
+ allocated range.\r
@param Attributes The requested bit mask of attributes for the allocated range.\r
- \r
+\r
@retval EFI_SUCCESS The requested memory pages were allocated.\r
@retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
- MEMORY_WRITE_COMBINE and MEMORY_CACHED. \r
+ MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
- @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. \r
- \r
+ @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
IN UINT64 Attributes\r
);\r
\r
-/** \r
+/**\r
Frees memory that was allocated with AllocateBuffer().\r
- \r
- @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
- @param Pages The number of pages to free. \r
- @param HostAddress The base system memory address of the allocated range. \r
- \r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param Pages The number of pages to free.\r
+ @param HostAddress The base system memory address of the allocated range.\r
+\r
@retval EFI_SUCCESS The requested memory pages were freed.\r
@retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
was not allocated with AllocateBuffer().\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
IN VOID *HostAddress\r
);\r
\r
-/** \r
+/**\r
Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
- \r
- @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
- \r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+\r
@retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r
- bridge to system memory. \r
+ bridge to system memory.\r
@retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r
- host bridge due to a hardware error. \r
- \r
+ host bridge due to a hardware error.\r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
IN EFI_PCI_IO_PROTOCOL *This\r
);\r
\r
-/** \r
+/**\r
Retrieves this PCI controller's current PCI bus number, device number, and function number.\r
- \r
- @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param SegmentNumber The PCI controller's current PCI segment number.\r
@param BusNumber The PCI controller's current PCI bus number.\r
@param DeviceNumber The PCI controller's current PCI device number.\r
@param FunctionNumber The PCI controller's current PCI function number.\r
- \r
- @retval EFI_SUCCESS The PCI controller location was returned. \r
- @retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r
- \r
+\r
+ @retval EFI_SUCCESS The PCI controller location was returned.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
\r
/**\r
Check BAR type for PCI resource.\r
- \r
- @param PciIoDevice PCI device instance\r
+\r
+ @param PciIoDevice PCI device instance.\r
@param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
- base address for the memory or I/O operation to perform. \r
- @param BarType Memory or I/O\r
- \r
- @return whether Pci device's bar type is same with input BarType.\r
+ base address for the memory or I/O operation to perform.\r
+ @param BarType Memory or I/O.\r
+\r
+ @retval TRUE Pci device's bar type is same with input BarType.\r
+ @retval TRUE Pci device's bar type is not same with input BarType.\r
+\r
**/\r
BOOLEAN\r
CheckBarType (\r
- IN PCI_IO_DEVICE *PciIoDevice,\r
- UINT8 BarIndex,\r
- PCI_BAR_TYPE BarType\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN UINT8 BarIndex,\r
+ IN PCI_BAR_TYPE BarType\r
);\r
\r
/**\r
- Set/Disable new attributes to a Root Bridge\r
- \r
- @param PciIoDevice Pci device instance\r
- @param Attributes New attribute want to be set\r
- @param Operation Set or Disable\r
- \r
- @retval EFI_UNSUPPORTED If root bridge does not support change attribute\r
- @retval EFI_SUCCESS Success operation.\r
+ Set/Disable new attributes to a Root Bridge.\r
+\r
+ @param PciIoDevice Pci device instance.\r
+ @param Attributes New attribute want to be set.\r
+ @param Operation Set or Disable.\r
+\r
+ @retval EFI_UNSUPPORTED If root bridge does not support change attribute.\r
+ @retval EFI_SUCCESS Successfully set new attributs.\r
+\r
**/\r
EFI_STATUS\r
ModifyRootBridgeAttributes (\r
);\r
\r
/**\r
- Check whether this device can be enable/disable to snoop\r
- \r
- @param PciIoDevice Pci device instance\r
- @param Operation Enable/Disable\r
- \r
- @retval EFI_UNSUPPORTED Pci device is not GFX device or not support snoop\r
+ Check whether this device can be enable/disable to snoop.\r
+\r
+ @param PciIoDevice Pci device instance.\r
+ @param Operation Enable/Disable.\r
+\r
+ @retval EFI_UNSUPPORTED Pci device is not GFX device or not support snoop.\r
@retval EFI_SUCCESS Snoop can be supported.\r
+\r
**/\r
EFI_STATUS\r
SupportPaletteSnoopAttributes (\r
- IN PCI_IO_DEVICE *PciIoDevice,\r
- IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r
);\r
\r
-/** \r
+/**\r
Performs an operation on the attributes that this PCI controller supports. The operations include\r
- getting the set of supported attributes, retrieving the current attributes, setting the current \r
- attributes, enabling attributes, and disabling attributes. \r
- \r
- @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
+ getting the set of supported attributes, retrieving the current attributes, setting the current\r
+ attributes, enabling attributes, and disabling attributes.\r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Operation The operation to perform on the attributes for this PCI controller.\r
@param Attributes The mask of attributes that are used for Set, Enable, and Disable\r
- operations. \r
+ operations.\r
@param Result A pointer to the result mask of attributes that are returned for the Get\r
- and Supported operations. \r
- \r
+ and Supported operations.\r
+\r
@retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r
- @retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r
- @retval EFI_UNSUPPORTED one or more of the bits set in \r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+ @retval EFI_UNSUPPORTED one or more of the bits set in\r
Attributes are not supported by this PCI controller or one of\r
its parent bridges when Operation is Set, Enable or Disable.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
OUT UINT64 *Result OPTIONAL\r
);\r
\r
-/** \r
+/**\r
Gets the attributes that this PCI controller supports setting on a BAR using\r
SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.\r
- \r
- @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
base address for resource range. The legal range for this field is 0..5.\r
@param Supports A pointer to the mask of attributes that this PCI controller supports\r
- setting for this BAR with SetBarAttributes(). \r
+ setting for this BAR with SetBarAttributes().\r
@param Resources A pointer to the ACPI 2.0 resource descriptors that describe the current\r
- configuration of this BAR of the PCI controller. \r
- \r
- @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI \r
- controller supports are returned in Supports. If Resources \r
+ configuration of this BAR of the PCI controller.\r
+\r
+ @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI\r
+ controller supports are returned in Supports. If Resources\r
is not NULL, then the ACPI 2.0 resource descriptors that the PCI\r
- controller is currently using are returned in Resources. \r
+ controller is currently using are returned in Resources.\r
@retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
@retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
@retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate\r
- Resources. \r
- \r
+ Resources.\r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
OUT VOID **Resources OPTIONAL\r
);\r
\r
-/** \r
+/**\r
Sets the attributes for a range of a BAR on a PCI controller.\r
- \r
- @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Attributes The mask of attributes to set for the resource range specified by\r
- BarIndex, Offset, and Length. \r
+ BarIndex, Offset, and Length.\r
@param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
base address for resource range. The legal range for this field is 0..5.\r
@param Offset A pointer to the BAR relative base address of the resource range to be\r
- modified by the attributes specified by Attributes. \r
+ modified by the attributes specified by Attributes.\r
@param Length A pointer to the length of the resource range to be modified by the\r
- attributes specified by Attributes. \r
- \r
- @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource \r
- range specified by BarIndex, Offset, and Length were \r
+ attributes specified by Attributes.\r
+\r
+ @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource\r
+ range specified by BarIndex, Offset, and Length were\r
set on the PCI controller, and the actual resource range is returned\r
- in Offset and Length. \r
+ in Offset and Length.\r
@retval EFI_INVALID_PARAMETER Offset or Length is NULL.\r
@retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
@retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the\r
- resource range specified by BarIndex, Offset, and \r
- Length. \r
- \r
+ resource range specified by BarIndex, Offset, and\r
+ Length.\r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
\r
/**\r
Program parent bridge's attribute recurrently.\r
- \r
+\r
@param PciIoDevice Child Pci device instance\r
@param Operation The operation to perform on the attributes for this PCI controller.\r
@param Attributes The mask of attributes that are used for Set, Enable, and Disable\r
operations.\r
- \r
+\r
@retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r
- @retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r
- @retval EFI_UNSUPPORTED one or more of the bits set in \r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+ @retval EFI_UNSUPPORTED one or more of the bits set in\r
Attributes are not supported by this PCI controller or one of\r
its parent bridges when Operation is Set, Enable or Disable.\r
- \r
+\r
**/\r
EFI_STATUS\r
UpStreamBridgesAttributes (\r
- IN PCI_IO_DEVICE *PciIoDevice,\r
- IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r
- IN UINT64 Attributes\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r
+ IN UINT64 Attributes\r
);\r
\r
/**\r
- Test whether two Pci device has same parent bridge.\r
- \r
- @param PciDevice1 the frist pci device for testing\r
- @param PciDevice2 the second pci device for testing\r
- \r
- @return whether two Pci device has same parent bridge.\r
+ Test whether two Pci devices has same parent bridge.\r
+\r
+ @param PciDevice1 The first pci device for testing.\r
+ @param PciDevice2 The second pci device for testing.\r
+\r
+ @retval TRUE Two Pci device has the same parent bridge.\r
+ @retval FALSE Two Pci device has not the same parent bridge.\r
+\r
**/\r
BOOLEAN\r
PciDevicesOnTheSamePath (\r
/** @file\r
+ Internal library implementation for PCI Bus module.\r
\r
- PCI Bus Driver Lib file\r
- It abstracts some functions that can be different\r
- between light PCI bus driver and full PCI bus driver\r
-\r
-Copyright (c) 2006 - 2008, Intel Corporation\r
+Copyright (c) 2006 - 2009, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
\r
/**\r
- Retrieve the BAR information via PciIo interface.\r
- \r
- @param PciIoDevice Pci device instance.\r
+ Retrieve the PCI Card device BAR information via PciIo interface.\r
+\r
+ @param PciIoDevice PCI Card device instance.\r
+\r
**/\r
VOID\r
GetBackPcCardBar (\r
// Read PciBar information from the bar register\r
//\r
if (!gFullEnumeration) {\r
-\r
Address = 0;\r
PciIoRead (\r
&(PciIoDevice->PciIo),\r
EfiPciIoWidthUint32,\r
- 0x1c,\r
+ PCI_CARD_MEMORY_BASE_0,\r
1,\r
&Address\r
);\r
PciIoRead (\r
&(PciIoDevice->PciIo),\r
EfiPciIoWidthUint32,\r
- 0x20,\r
+ PCI_CARD_MEMORY_BASE_1,\r
1,\r
&Address\r
);\r
PciIoRead (\r
&(PciIoDevice->PciIo),\r
EfiPciIoWidthUint32,\r
- 0x2c,\r
+ PCI_CARD_IO_BASE_0_LOWER,\r
1,\r
&Address\r
);\r
PciIoRead (\r
&(PciIoDevice->PciIo),\r
EfiPciIoWidthUint32,\r
- 0x34,\r
+ PCI_CARD_IO_BASE_1_LOWER,\r
1,\r
&Address\r
);\r
\r
}\r
\r
- if (gPciHotPlugInit != NULL) {\r
+ if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
GetResourcePaddingForHpb (PciIoDevice);\r
}\r
}\r
/**\r
Remove rejected pci device from specific root bridge\r
handle.\r
- \r
- @param RootBridgeHandle specific parent root bridge handle.\r
+\r
+ @param RootBridgeHandle Specific parent root bridge handle.\r
@param Bridge Bridge device instance.\r
- \r
- @retval EFI_SUCCESS Success operation.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
RemoveRejectedPciDevices (\r
- EFI_HANDLE RootBridgeHandle,\r
- IN PCI_IO_DEVICE *Bridge\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN PCI_IO_DEVICE *Bridge\r
)\r
{\r
PCI_IO_DEVICE *Temp;\r
LIST_ENTRY *LastLink;\r
\r
if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
- return EFI_SUCCESS;\r
+ return;\r
}\r
\r
CurrentLink = Bridge->ChildList.ForwardLink;\r
\r
CurrentLink = CurrentLink->ForwardLink;\r
}\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Wrapper function for allocating resource for pci host bridge.\r
- \r
- @param PciResAlloc Point to protocol instance EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
- \r
-**/\r
-EFI_STATUS\r
-PciHostBridgeResourceAllocator (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
- )\r
-{\r
- if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
- return PciHostBridgeResourceAllocator_WithHotPlugDeviceSupport (\r
- PciResAlloc\r
- );\r
- } else {\r
- return PciHostBridgeResourceAllocator_WithoutHotPlugDeviceSupport (\r
- PciResAlloc\r
- );\r
- }\r
}\r
\r
/**\r
- Submits the I/O and memory resource requirements for the specified PCI Root Bridge.\r
+ Submits the I/O and memory resource requirements for the specified PCI Host Bridge.\r
\r
@param PciResAlloc Point to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
\r
- @retval EFI_SUCCESS Success.\r
-**/\r
-EFI_STATUS\r
-PciHostBridgeResourceAllocator_WithoutHotPlugDeviceSupport (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
- )\r
-{\r
- PCI_IO_DEVICE *RootBridgeDev;\r
- EFI_HANDLE RootBridgeHandle;\r
- VOID *AcpiConfig;\r
- EFI_STATUS Status;\r
- UINT64 IoBase;\r
- UINT64 Mem32Base;\r
- UINT64 PMem32Base;\r
- UINT64 Mem64Base;\r
- UINT64 PMem64Base;\r
- UINT64 MaxOptionRomSize;\r
- PCI_RESOURCE_NODE *IoBridge;\r
- PCI_RESOURCE_NODE *Mem32Bridge;\r
- PCI_RESOURCE_NODE *PMem32Bridge;\r
- PCI_RESOURCE_NODE *Mem64Bridge;\r
- PCI_RESOURCE_NODE *PMem64Bridge;\r
- PCI_RESOURCE_NODE IoPool;\r
- PCI_RESOURCE_NODE Mem32Pool;\r
- PCI_RESOURCE_NODE PMem32Pool;\r
- PCI_RESOURCE_NODE Mem64Pool;\r
- PCI_RESOURCE_NODE PMem64Pool;\r
- EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD ExtendedData;\r
-\r
- //\r
- // Initialize resource pool\r
- //\r
-\r
- InitializeResourcePool (&IoPool, PciBarTypeIo16);\r
- InitializeResourcePool (&Mem32Pool, PciBarTypeMem32);\r
- InitializeResourcePool (&PMem32Pool, PciBarTypePMem32);\r
- InitializeResourcePool (&Mem64Pool, PciBarTypeMem64);\r
- InitializeResourcePool (&PMem64Pool, PciBarTypePMem64);\r
-\r
- RootBridgeDev = NULL;\r
- RootBridgeHandle = 0;\r
-\r
- while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
- //\r
- // Get RootBridg Device by handle\r
- //\r
- RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
-\r
- if (RootBridgeDev == NULL) {\r
- return EFI_NOT_FOUND;\r
- }\r
-\r
- //\r
- // Get host bridge handle for status report\r
- //\r
- ExtendedData.Handle = RootBridgeDev->PciRootBridgeIo->ParentHandle;\r
-\r
- //\r
- // Create the entire system resource map from the information collected by\r
- // enumerator. Several resource tree was created\r
- //\r
-\r
- IoBridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFF,\r
- 0,\r
- PciBarTypeIo16,\r
- PciResUsageTypical\r
- );\r
-\r
- Mem32Bridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypeMem32,\r
- PciResUsageTypical\r
- );\r
-\r
- PMem32Bridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypePMem32,\r
- PciResUsageTypical\r
- );\r
-\r
- Mem64Bridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypeMem64,\r
- PciResUsageTypical\r
- );\r
-\r
- PMem64Bridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypePMem64,\r
- PciResUsageTypical\r
- );\r
-\r
- //\r
- // Create resourcemap by going through all the devices subject to this root bridge\r
- //\r
- Status = CreateResourceMap (\r
- RootBridgeDev,\r
- IoBridge,\r
- Mem32Bridge,\r
- PMem32Bridge,\r
- Mem64Bridge,\r
- PMem64Bridge\r
- );\r
-\r
- //\r
- // Get the max ROM size that the root bridge can process\r
- //\r
- RootBridgeDev->RomSize = Mem32Bridge->Length;\r
-\r
- //\r
- // Get Max Option Rom size for current root bridge\r
- //\r
- MaxOptionRomSize = GetMaxOptionRomSize (RootBridgeDev);\r
-\r
- //\r
- // Enlarger the mem32 resource to accomdate the option rom\r
- // if the mem32 resource is not enough to hold the rom\r
- //\r
- if (MaxOptionRomSize > Mem32Bridge->Length) {\r
-\r
- Mem32Bridge->Length = MaxOptionRomSize;\r
- RootBridgeDev->RomSize = MaxOptionRomSize;\r
-\r
- //\r
- // Alignment should be adjusted as well\r
- //\r
- if (Mem32Bridge->Alignment < MaxOptionRomSize - 1) {\r
- Mem32Bridge->Alignment = MaxOptionRomSize - 1;\r
- }\r
- }\r
-\r
- //\r
- // Based on the all the resource tree, contruct ACPI resource node to\r
- // submit the resource aperture to pci host bridge protocol\r
- //\r
- Status = ConstructAcpiResourceRequestor (\r
- RootBridgeDev,\r
- IoBridge,\r
- Mem32Bridge,\r
- PMem32Bridge,\r
- Mem64Bridge,\r
- PMem64Bridge,\r
- &AcpiConfig\r
- );\r
+ @retval EFI_SUCCESS Successfully finished resource allocation.\r
+ @retval EFI_NOT_FOUND Cannot get root bridge instance.\r
+ @retval EFI_OUT_OF_RESOURCES Platform failed to program the resources if no hot plug supported.\r
+ @retval other Some error occurred when allocating resources for the PCI Host Bridge.\r
\r
- //\r
- // Insert these resource nodes into the database\r
- //\r
- InsertResourceNode (&IoPool, IoBridge);\r
- InsertResourceNode (&Mem32Pool, Mem32Bridge);\r
- InsertResourceNode (&PMem32Pool, PMem32Bridge);\r
- InsertResourceNode (&Mem64Pool, Mem64Bridge);\r
- InsertResourceNode (&PMem64Pool, PMem64Bridge);\r
+ @note Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.\r
\r
- if (Status == EFI_SUCCESS) {\r
- //\r
- // Submit the resource requirement\r
- //\r
- Status = PciResAlloc->SubmitResources (\r
- PciResAlloc,\r
- RootBridgeDev->Handle,\r
- AcpiConfig\r
- );\r
- }\r
- //\r
- // Free acpi resource node\r
- //\r
- if (AcpiConfig != NULL) {\r
- FreePool (AcpiConfig);\r
- }\r
-\r
- if (EFI_ERROR (Status)) {\r
- //\r
- // Destroy all the resource tree\r
- //\r
- DestroyResourceTree (&IoPool);\r
- DestroyResourceTree (&Mem32Pool);\r
- DestroyResourceTree (&PMem32Pool);\r
- DestroyResourceTree (&Mem64Pool);\r
- DestroyResourceTree (&PMem64Pool);\r
- return Status;\r
- }\r
- }\r
- //\r
- // End while\r
- //\r
-\r
- //\r
- // Notify pci bus driver starts to program the resource\r
- //\r
- Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeAllocateResources);\r
-\r
- if (EFI_ERROR (Status)) {\r
- //\r
- // Allocation failed, then return\r
- //\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
- //\r
- // Raise the EFI_IOB_PCI_RES_ALLOC status code\r
- //\r
- REPORT_STATUS_CODE_WITH_EXTENDED_DATA (\r
- EFI_PROGRESS_CODE,\r
- EFI_IO_BUS_PCI | EFI_IOB_PCI_PC_RES_ALLOC,\r
- (VOID *) &ExtendedData,\r
- sizeof (ExtendedData)\r
- );\r
-\r
- //\r
- // Notify pci bus driver starts to program the resource\r
- //\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeSetResources);\r
-\r
- RootBridgeDev = NULL;\r
-\r
- RootBridgeHandle = 0;\r
-\r
- while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
- //\r
- // Get RootBridg Device by handle\r
- //\r
- RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
-\r
- if (RootBridgeDev == NULL) {\r
- return EFI_NOT_FOUND;\r
- }\r
-\r
- //\r
- // Get acpi resource node for all the resource types\r
- //\r
- AcpiConfig = NULL;\r
- Status = PciResAlloc->GetProposedResources (\r
- PciResAlloc,\r
- RootBridgeDev->Handle,\r
- &AcpiConfig\r
- );\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Get the resource base by interpreting acpi resource node\r
- //\r
- //\r
- GetResourceBase (\r
- AcpiConfig,\r
- &IoBase,\r
- &Mem32Base,\r
- &PMem32Base,\r
- &Mem64Base,\r
- &PMem64Base\r
- );\r
-\r
- //\r
- // Process option rom for this root bridge\r
- //\r
- Status = ProcessOptionRom (RootBridgeDev, Mem32Base, RootBridgeDev->RomSize);\r
-\r
- //\r
- // Create the entire system resource map from the information collected by\r
- // enumerator. Several resource tree was created\r
- //\r
- Status = GetResourceMap (\r
- RootBridgeDev,\r
- &IoBridge,\r
- &Mem32Bridge,\r
- &PMem32Bridge,\r
- &Mem64Bridge,\r
- &PMem64Bridge,\r
- &IoPool,\r
- &Mem32Pool,\r
- &PMem32Pool,\r
- &Mem64Pool,\r
- &PMem64Pool\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Program IO resources\r
- //\r
- ProgramResource (\r
- IoBase,\r
- IoBridge\r
- );\r
-\r
- //\r
- // Program Mem32 resources\r
- //\r
- ProgramResource (\r
- Mem32Base,\r
- Mem32Bridge\r
- );\r
-\r
- //\r
- // Program PMem32 resources\r
- //\r
- ProgramResource (\r
- PMem32Base,\r
- PMem32Bridge\r
- );\r
-\r
- //\r
- // Program Mem64 resources\r
- //\r
- ProgramResource (\r
- Mem64Base,\r
- Mem64Bridge\r
- );\r
-\r
- //\r
- // Program PMem64 resources\r
- //\r
- ProgramResource (\r
- PMem64Base,\r
- PMem64Bridge\r
- );\r
-\r
- FreePool (AcpiConfig);\r
- }\r
-\r
- //\r
- // Destroy all the resource tree\r
- //\r
- DestroyResourceTree (&IoPool);\r
- DestroyResourceTree (&Mem32Pool);\r
- DestroyResourceTree (&PMem32Pool);\r
- DestroyResourceTree (&Mem64Pool);\r
- DestroyResourceTree (&PMem64Pool);\r
-\r
- //\r
- // Notify the resource allocation phase is to end\r
- //\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeEndResourceAllocation);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Submits the I/O and memory resource requirements for the specified PCI Root Bridge.\r
-\r
- @param PciResAlloc Point to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
-\r
- @retval EFI_SUCCESS Success.\r
**/\r
EFI_STATUS\r
-PciHostBridgeResourceAllocator_WithHotPlugDeviceSupport (\r
+PciHostBridgeResourceAllocator (\r
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
)\r
{\r
- PCI_IO_DEVICE *RootBridgeDev;\r
- EFI_HANDLE RootBridgeHandle;\r
- VOID *AcpiConfig;\r
- EFI_STATUS Status;\r
- UINT64 IoBase;\r
- UINT64 Mem32Base;\r
- UINT64 PMem32Base;\r
- UINT64 Mem64Base;\r
- UINT64 PMem64Base;\r
- UINT64 IoResStatus;\r
- UINT64 Mem32ResStatus;\r
- UINT64 PMem32ResStatus;\r
- UINT64 Mem64ResStatus;\r
- UINT64 PMem64ResStatus;\r
- UINT64 MaxOptionRomSize;\r
- PCI_RESOURCE_NODE *IoBridge;\r
- PCI_RESOURCE_NODE *Mem32Bridge;\r
- PCI_RESOURCE_NODE *PMem32Bridge;\r
- PCI_RESOURCE_NODE *Mem64Bridge;\r
- PCI_RESOURCE_NODE *PMem64Bridge;\r
- PCI_RESOURCE_NODE IoPool;\r
- PCI_RESOURCE_NODE Mem32Pool;\r
- PCI_RESOURCE_NODE PMem32Pool;\r
- PCI_RESOURCE_NODE Mem64Pool;\r
- PCI_RESOURCE_NODE PMem64Pool;\r
- BOOLEAN ReAllocate;\r
+ PCI_IO_DEVICE *RootBridgeDev;\r
+ EFI_HANDLE RootBridgeHandle;\r
+ VOID *AcpiConfig;\r
+ EFI_STATUS Status;\r
+ UINT64 IoBase;\r
+ UINT64 Mem32Base;\r
+ UINT64 PMem32Base;\r
+ UINT64 Mem64Base;\r
+ UINT64 PMem64Base;\r
+ UINT64 IoResStatus;\r
+ UINT64 Mem32ResStatus;\r
+ UINT64 PMem32ResStatus;\r
+ UINT64 Mem64ResStatus;\r
+ UINT64 PMem64ResStatus;\r
+ UINT64 MaxOptionRomSize;\r
+ PCI_RESOURCE_NODE *IoBridge;\r
+ PCI_RESOURCE_NODE *Mem32Bridge;\r
+ PCI_RESOURCE_NODE *PMem32Bridge;\r
+ PCI_RESOURCE_NODE *Mem64Bridge;\r
+ PCI_RESOURCE_NODE *PMem64Bridge;\r
+ PCI_RESOURCE_NODE IoPool;\r
+ PCI_RESOURCE_NODE Mem32Pool;\r
+ PCI_RESOURCE_NODE PMem32Pool;\r
+ PCI_RESOURCE_NODE Mem64Pool;\r
+ PCI_RESOURCE_NODE PMem64Pool;\r
+ BOOLEAN ReAllocate;\r
EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD HandleExtendedData;\r
EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData;\r
\r
ReAllocate = FALSE;\r
\r
//\r
- // It will try several times if the resource allocation fails\r
+ // It may try several times if the resource allocation fails\r
//\r
while (TRUE) {\r
-\r
//\r
// Initialize resource pool\r
//\r
RootBridgeHandle = 0;\r
\r
while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
-\r
//\r
- // Get RootBridg Device by handle\r
+ // Get Root Bridge Device by handle\r
//\r
RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
\r
PciResUsageTypical\r
);\r
\r
- //\r
- // Create resourcemap by going through all the devices subject to this root bridge\r
- //\r
- Status = CreateResourceMap (\r
- RootBridgeDev,\r
- IoBridge,\r
- Mem32Bridge,\r
- PMem32Bridge,\r
- Mem64Bridge,\r
- PMem64Bridge\r
- );\r
+ //\r
+ // Create resourcemap by going through all the devices subject to this root bridge\r
+ //\r
+ CreateResourceMap (\r
+ RootBridgeDev,\r
+ IoBridge,\r
+ Mem32Bridge,\r
+ PMem32Bridge,\r
+ Mem64Bridge,\r
+ PMem64Bridge\r
+ );\r
\r
//\r
// Get the max ROM size that the root bridge can process\r
return Status;\r
}\r
}\r
-\r
//\r
- // Notify pci bus driver starts to program the resource\r
+ // End while\r
//\r
\r
+ //\r
+ // Notify platform to start to program the resource\r
+ //\r
Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeAllocateResources);\r
-\r
- if (!EFI_ERROR (Status)) {\r
+ if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
//\r
- // Allocation succeed, then continue the following\r
+ // If Hot Plug is not supported\r
//\r
- break;\r
- }\r
-\r
- //\r
- // If the resource allocation is unsuccessful, free resources on bridge\r
- //\r
-\r
- RootBridgeDev = NULL;\r
- RootBridgeHandle = 0;\r
+ if (EFI_ERROR (Status)) {\r
+ //\r
+ // Allocation failed, then return\r
+ //\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+ //\r
+ // Allocation succeed.\r
+ // Get host bridge handle for status report, and then skip the main while\r
+ //\r
+ HandleExtendedData.Handle = RootBridgeDev->PciRootBridgeIo->ParentHandle;\r
\r
- IoResStatus = EFI_RESOURCE_SATISFIED;\r
- Mem32ResStatus = EFI_RESOURCE_SATISFIED;\r
- PMem32ResStatus = EFI_RESOURCE_SATISFIED;\r
- Mem64ResStatus = EFI_RESOURCE_SATISFIED;\r
- PMem64ResStatus = EFI_RESOURCE_SATISFIED;\r
+ break;\r
\r
- while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
+ } else {\r
//\r
- // Get RootBridg Device by handle\r
+ // If Hot Plug is supported\r
//\r
- RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
- if (RootBridgeDev == NULL) {\r
- return EFI_NOT_FOUND;\r
+ if (!EFI_ERROR (Status)) {\r
+ //\r
+ // Allocation succeed, then continue the following\r
+ //\r
+ break;\r
}\r
\r
//\r
- // Get host bridge handle for status report\r
+ // If the resource allocation is unsuccessful, free resources on bridge\r
//\r
- HandleExtendedData.Handle = RootBridgeDev->PciRootBridgeIo->ParentHandle;\r
\r
- //\r
- // Get acpi resource node for all the resource types\r
- //\r
- AcpiConfig = NULL;\r
+ RootBridgeDev = NULL;\r
+ RootBridgeHandle = 0;\r
\r
- Status = PciResAlloc->GetProposedResources (\r
- PciResAlloc,\r
- RootBridgeDev->Handle,\r
- &AcpiConfig\r
- );\r
+ IoResStatus = EFI_RESOURCE_SATISFIED;\r
+ Mem32ResStatus = EFI_RESOURCE_SATISFIED;\r
+ PMem32ResStatus = EFI_RESOURCE_SATISFIED;\r
+ Mem64ResStatus = EFI_RESOURCE_SATISFIED;\r
+ PMem64ResStatus = EFI_RESOURCE_SATISFIED;\r
\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
+ while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
+ //\r
+ // Get RootBridg Device by handle\r
+ //\r
+ RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
+ if (RootBridgeDev == NULL) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
\r
- if (AcpiConfig != NULL) {\r
//\r
- // Adjust resource allocation policy for each RB\r
+ // Get host bridge handle for status report\r
//\r
- GetResourceAllocationStatus (\r
- AcpiConfig,\r
- &IoResStatus,\r
- &Mem32ResStatus,\r
- &PMem32ResStatus,\r
- &Mem64ResStatus,\r
- &PMem64ResStatus\r
- );\r
- FreePool (AcpiConfig);\r
- }\r
- }\r
- //\r
- // End while\r
- //\r
+ HandleExtendedData.Handle = RootBridgeDev->PciRootBridgeIo->ParentHandle;\r
\r
- //\r
- // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code\r
- //\r
- //\r
- // It is very difficult to follow the spec here\r
- // Device path , Bar index can not be get here\r
- //\r
- ZeroMem (&AllocFailExtendedData, sizeof (AllocFailExtendedData));\r
+ //\r
+ // Get acpi resource node for all the resource types\r
+ //\r
+ AcpiConfig = NULL;\r
\r
- REPORT_STATUS_CODE_WITH_EXTENDED_DATA (\r
- EFI_PROGRESS_CODE,\r
- EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT,\r
- (VOID *) &AllocFailExtendedData,\r
- sizeof (AllocFailExtendedData)\r
- );\r
+ Status = PciResAlloc->GetProposedResources (\r
+ PciResAlloc,\r
+ RootBridgeDev->Handle,\r
+ &AcpiConfig\r
+ );\r
\r
- Status = PciHostBridgeAdjustAllocation (\r
- &IoPool,\r
- &Mem32Pool,\r
- &PMem32Pool,\r
- &Mem64Pool,\r
- &PMem64Pool,\r
- IoResStatus,\r
- Mem32ResStatus,\r
- PMem32ResStatus,\r
- Mem64ResStatus,\r
- PMem64ResStatus\r
- );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
- //\r
- // Destroy all the resource tree\r
- //\r
- DestroyResourceTree (&IoPool);\r
- DestroyResourceTree (&Mem32Pool);\r
- DestroyResourceTree (&PMem32Pool);\r
- DestroyResourceTree (&Mem64Pool);\r
- DestroyResourceTree (&PMem64Pool);\r
+ if (AcpiConfig != NULL) {\r
+ //\r
+ // Adjust resource allocation policy for each RB\r
+ //\r
+ GetResourceAllocationStatus (\r
+ AcpiConfig,\r
+ &IoResStatus,\r
+ &Mem32ResStatus,\r
+ &PMem32ResStatus,\r
+ &Mem64ResStatus,\r
+ &PMem64ResStatus\r
+ );\r
+ FreePool (AcpiConfig);\r
+ }\r
+ }\r
+ //\r
+ // End while\r
+ //\r
+\r
+ //\r
+ // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code\r
+ //\r
+ //\r
+ // It is very difficult to follow the spec here\r
+ // Device path , Bar index can not be get here\r
+ //\r
+ ZeroMem (&AllocFailExtendedData, sizeof (AllocFailExtendedData));\r
\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeFreeResources);\r
+ REPORT_STATUS_CODE_WITH_EXTENDED_DATA (\r
+ EFI_PROGRESS_CODE,\r
+ EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT,\r
+ (VOID *) &AllocFailExtendedData,\r
+ sizeof (AllocFailExtendedData)\r
+ );\r
\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
+ Status = PciHostBridgeAdjustAllocation (\r
+ &IoPool,\r
+ &Mem32Pool,\r
+ &PMem32Pool,\r
+ &Mem64Pool,\r
+ &PMem64Pool,\r
+ IoResStatus,\r
+ Mem32ResStatus,\r
+ PMem32ResStatus,\r
+ Mem64ResStatus,\r
+ PMem64ResStatus\r
+ );\r
+\r
+ //\r
+ // Destroy all the resource tree\r
+ //\r
+ DestroyResourceTree (&IoPool);\r
+ DestroyResourceTree (&Mem32Pool);\r
+ DestroyResourceTree (&PMem32Pool);\r
+ DestroyResourceTree (&Mem64Pool);\r
+ DestroyResourceTree (&PMem64Pool);\r
\r
- ReAllocate = TRUE;\r
+ NotifyPhase (PciResAlloc, EfiPciHostBridgeFreeResources);\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
+ ReAllocate = TRUE;\r
+ }\r
}\r
//\r
// End main while\r
RootBridgeHandle = 0;\r
\r
while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
-\r
//\r
// Get RootBridg Device by handle\r
//\r
//\r
// Process option rom for this root bridge\r
//\r
- Status = ProcessOptionRom (RootBridgeDev, Mem32Base, RootBridgeDev->RomSize);\r
+ ProcessOptionRom (RootBridgeDev, Mem32Base, RootBridgeDev->RomSize);\r
\r
//\r
// Create the entire system resource map from the information collected by\r
// enumerator. Several resource tree was created\r
//\r
- Status = GetResourceMap (\r
- RootBridgeDev,\r
- &IoBridge,\r
- &Mem32Bridge,\r
- &PMem32Bridge,\r
- &Mem64Bridge,\r
- &PMem64Bridge,\r
- &IoPool,\r
- &Mem32Pool,\r
- &PMem32Pool,\r
- &Mem64Pool,\r
- &PMem64Pool\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
+ GetResourceMap (\r
+ RootBridgeDev,\r
+ &IoBridge,\r
+ &Mem32Bridge,\r
+ &PMem32Bridge,\r
+ &Mem64Bridge,\r
+ &PMem64Bridge,\r
+ &IoPool,\r
+ &Mem32Pool,\r
+ &PMem32Pool,\r
+ &Mem64Pool,\r
+ &PMem64Pool\r
+ );\r
\r
//\r
// Program IO resources\r
);\r
\r
//\r
- // Program PMem32 resources\r
- //\r
- ProgramResource (\r
- PMem32Base,\r
- PMem32Bridge\r
- );\r
-\r
- //\r
- // Program Mem64 resources\r
- //\r
- ProgramResource (\r
- Mem64Base,\r
- Mem64Bridge\r
- );\r
-\r
- //\r
- // Program PMem64 resources\r
- //\r
- ProgramResource (\r
- PMem64Base,\r
- PMem64Bridge\r
- );\r
-\r
- FreePool (AcpiConfig);\r
- }\r
-\r
- //\r
- // Destroy all the resource tree\r
- //\r
- DestroyResourceTree (&IoPool);\r
- DestroyResourceTree (&Mem32Pool);\r
- DestroyResourceTree (&PMem32Pool);\r
- DestroyResourceTree (&Mem64Pool);\r
- DestroyResourceTree (&PMem64Pool);\r
-\r
- //\r
- // Notify the resource allocation phase is to end\r
- //\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeEndResourceAllocation);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Wapper function of scanning pci bus and assign bus number to the given PCI bus system\r
- Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.\r
- \r
- @param Bridge Bridge device instance.\r
- @param StartBusNumber start point.\r
- @param SubBusNumber Point to sub bus number.\r
- @param PaddedBusRange Customized bus number.\r
- \r
- @retval EFI_SUCCESS Success.\r
- @retval EFI_DEVICE_ERROR Fail to scan bus.\r
-**/\r
-EFI_STATUS\r
-PciScanBus (\r
- IN PCI_IO_DEVICE *Bridge,\r
- IN UINT8 StartBusNumber,\r
- OUT UINT8 *SubBusNumber,\r
- OUT UINT8 *PaddedBusRange\r
- )\r
-{\r
- if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
- return PciScanBus_WithHotPlugDeviceSupport (\r
- Bridge,\r
- StartBusNumber,\r
- SubBusNumber,\r
- PaddedBusRange\r
- );\r
- } else {\r
- return PciScanBus_WithoutHotPlugDeviceSupport (\r
- Bridge,\r
- StartBusNumber,\r
- SubBusNumber,\r
- PaddedBusRange\r
- );\r
- }\r
-}\r
-\r
-/**\r
- Wapper function of scanning pci bus and assign bus number to the given PCI bus system\r
- Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug. \r
- \r
- @param Bridge Bridge device instance.\r
- @param StartBusNumber start point.\r
- @param SubBusNumber Point to sub bus number.\r
- @param PaddedBusRange Customized bus number.\r
- \r
- @retval EFI_SUCCESS Success.\r
- @retval EFI_DEVICE_ERROR Fail to scan bus.\r
-**/\r
-EFI_STATUS\r
-PciScanBus_WithoutHotPlugDeviceSupport (\r
- IN PCI_IO_DEVICE *Bridge,\r
- IN UINT8 StartBusNumber,\r
- OUT UINT8 *SubBusNumber,\r
- OUT UINT8 *PaddedBusRange\r
- )\r
-{\r
- EFI_STATUS Status;\r
- PCI_TYPE00 Pci;\r
- UINT8 Device;\r
- UINT8 Func;\r
- UINT64 Address;\r
- UINTN SecondBus;\r
- UINT16 Register;\r
- PCI_IO_DEVICE *PciDevice;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
-\r
- PciRootBridgeIo = Bridge->PciRootBridgeIo;\r
- SecondBus = 0;\r
- Register = 0;\r
-\r
- for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
- for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
-\r
- //\r
- // Check to see whether a pci device is present\r
- //\r
- Status = PciDevicePresent (\r
- PciRootBridgeIo,\r
- &Pci,\r
- StartBusNumber,\r
- Device,\r
- Func\r
- );\r
-\r
- if (!EFI_ERROR (Status)) {\r
- DEBUG((EFI_D_ERROR, "Found DEV(%02d,%02d,%02d)\n", StartBusNumber, Device, Func));\r
- \r
- if (IS_PCI_BRIDGE (&Pci) ||\r
- IS_CARDBUS_BRIDGE (&Pci)) {\r
-\r
- //\r
- // Get the bridge information\r
- //\r
- Status = PciSearchDevice (\r
- Bridge,\r
- &Pci,\r
- StartBusNumber,\r
- Device,\r
- Func,\r
- &PciDevice\r
- );\r
- \r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- \r
- //\r
- // Add feature to support customized secondary bus number\r
- //\r
- if (*SubBusNumber == 0) {\r
- *SubBusNumber = *PaddedBusRange;\r
- *PaddedBusRange = 0;\r
- }\r
- \r
- (*SubBusNumber)++;\r
- \r
- SecondBus = (*SubBusNumber);\r
- \r
- Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);\r
- \r
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);\r
- \r
- Status = PciRootBridgeIoWrite (\r
- PciRootBridgeIo,\r
- &Pci,\r
- EfiPciWidthUint16,\r
- Address,\r
- 1,\r
- &Register\r
- );\r
- \r
- //\r
- // Initialize SubBusNumber to SecondBus\r
- //\r
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
- Status = PciRootBridgeIoWrite (\r
- PciRootBridgeIo,\r
- &Pci,\r
- EfiPciWidthUint8,\r
- Address,\r
- 1,\r
- SubBusNumber\r
- );\r
- //\r
- // If it is PPB, resursively search down this bridge\r
- //\r
- if (IS_PCI_BRIDGE (&Pci)) {\r
- //\r
- // Temporarily initialize SubBusNumber to maximum bus number to ensure the\r
- // PCI configuration transaction to go through any PPB\r
- //\r
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
- Register = 0xFF;\r
- Status = PciRootBridgeIoWrite (\r
- PciRootBridgeIo,\r
- &Pci,\r
- EfiPciWidthUint8,\r
- Address,\r
- 1,\r
- &Register\r
- );\r
- \r
- PreprocessController (\r
- PciDevice,\r
- PciDevice->BusNumber,\r
- PciDevice->DeviceNumber,\r
- PciDevice->FunctionNumber,\r
- EfiPciBeforeChildBusEnumeration\r
- );\r
- \r
- DEBUG((EFI_D_ERROR, "Scan PPB(%02d,%02d,%02d)\n", PciDevice->BusNumber, PciDevice->DeviceNumber,PciDevice->FunctionNumber ));\r
- Status = PciScanBus (\r
- PciDevice,\r
- (UINT8) (SecondBus),\r
- SubBusNumber,\r
- PaddedBusRange\r
- );\r
- \r
- if (EFI_ERROR (Status)) {\r
- return EFI_DEVICE_ERROR;\r
- }\r
- }\r
- \r
- //\r
- // Set the current maximum bus number under the PPB\r
- //\r
- \r
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
- \r
- Status = PciRootBridgeIoWrite (\r
- PciRootBridgeIo,\r
- &Pci,\r
- EfiPciWidthUint8,\r
- Address,\r
- 1,\r
- SubBusNumber\r
- );\r
- \r
- }\r
- }\r
- if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {\r
+ // Program PMem32 resources\r
+ //\r
+ ProgramResource (\r
+ PMem32Base,\r
+ PMem32Bridge\r
+ );\r
\r
- //\r
- // Skip sub functions, this is not a multi function device\r
- //\r
+ //\r
+ // Program Mem64 resources\r
+ //\r
+ ProgramResource (\r
+ Mem64Base,\r
+ Mem64Bridge\r
+ );\r
\r
- Func = PCI_MAX_FUNC;\r
- }\r
- }\r
+ //\r
+ // Program PMem64 resources\r
+ //\r
+ ProgramResource (\r
+ PMem64Base,\r
+ PMem64Bridge\r
+ );\r
+\r
+ FreePool (AcpiConfig);\r
}\r
\r
+ //\r
+ // Destroy all the resource tree\r
+ //\r
+ DestroyResourceTree (&IoPool);\r
+ DestroyResourceTree (&Mem32Pool);\r
+ DestroyResourceTree (&PMem32Pool);\r
+ DestroyResourceTree (&Mem64Pool);\r
+ DestroyResourceTree (&PMem64Pool);\r
+\r
+ //\r
+ // Notify the resource allocation phase is to end\r
+ //\r
+ NotifyPhase (PciResAlloc, EfiPciHostBridgeEndResourceAllocation);\r
+\r
return EFI_SUCCESS;\r
}\r
\r
/**\r
- Wapper function of scanning pci bus and assign bus number to the given PCI bus system\r
- Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug. \r
- \r
- @param Bridge Bridge device instance.\r
- @param StartBusNumber start point.\r
- @param SubBusNumber Point to sub bus number.\r
- @param PaddedBusRange Customized bus number.\r
- \r
- @retval EFI_SUCCESS Success.\r
- @retval EFI_DEVICE_ERROR Fail to scan bus.\r
+ Scan pci bus and assign bus number to the given PCI bus system.\r
+\r
+ @param Bridge Bridge device instance.\r
+ @param StartBusNumber start point.\r
+ @param SubBusNumber Point to sub bus number.\r
+ @param PaddedBusRange Customized bus number.\r
+\r
+ @retval EFI_SUCCESS Successfully scanned and assigned bus number.\r
+ @retval other Some error occurred when scanning pci bus.\r
+\r
+ @note Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.\r
+\r
**/\r
EFI_STATUS\r
-PciScanBus_WithHotPlugDeviceSupport (\r
+PciScanBus (\r
IN PCI_IO_DEVICE *Bridge,\r
IN UINT8 StartBusNumber,\r
OUT UINT8 *SubBusNumber,\r
State = 0;\r
Attributes = (EFI_HPC_PADDING_ATTRIBUTES) 0;\r
BusRange = 0;\r
+ BusPadding = FALSE;\r
+ PciDevice = NULL;\r
+ PciAddress = 0;\r
\r
for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
\r
DEBUG((EFI_D_ERROR, "Found DEV(%02d,%02d,%02d)\n", StartBusNumber, Device, Func ));\r
\r
- //\r
- // Get the PCI device information\r
- //\r
- Status = PciSearchDevice (\r
- Bridge,\r
- &Pci,\r
- StartBusNumber,\r
- Device,\r
- Func,\r
- &PciDevice\r
- );\r
+ if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
+ //\r
+ // Get the PCI device information\r
+ //\r
+ Status = PciSearchDevice (\r
+ Bridge,\r
+ &Pci,\r
+ StartBusNumber,\r
+ Device,\r
+ Func,\r
+ &PciDevice\r
+ );\r
\r
- ASSERT (!EFI_ERROR (Status));\r
+ ASSERT (!EFI_ERROR (Status));\r
\r
- PciAddress = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0);\r
+ PciAddress = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0);\r
\r
- if (!IS_PCI_BRIDGE (&Pci)) {\r
- //\r
- // PCI bridges will be called later\r
- // Here just need for PCI device or PCI to cardbus controller\r
- // EfiPciBeforeChildBusEnumeration for PCI Device Node\r
- //\r
- PreprocessController (\r
- PciDevice,\r
- PciDevice->BusNumber,\r
- PciDevice->DeviceNumber,\r
- PciDevice->FunctionNumber,\r
- EfiPciBeforeChildBusEnumeration\r
- );\r
- }\r
+ if (!IS_PCI_BRIDGE (&Pci)) {\r
+ //\r
+ // PCI bridges will be called later\r
+ // Here just need for PCI device or PCI to cardbus controller\r
+ // EfiPciBeforeChildBusEnumeration for PCI Device Node\r
+ //\r
+ PreprocessController (\r
+ PciDevice,\r
+ PciDevice->BusNumber,\r
+ PciDevice->DeviceNumber,\r
+ PciDevice->FunctionNumber,\r
+ EfiPciBeforeChildBusEnumeration\r
+ );\r
+ }\r
\r
- //\r
- // For Pci Hotplug controller devcie only\r
- //\r
- if (gPciHotPlugInit != NULL) {\r
//\r
- // Check if it is a Hotplug PCI controller\r
+ // For Pci Hotplug controller devcie only\r
//\r
- if (IsRootPciHotPlugController (PciDevice->DevicePath, &HpIndex)) {\r
+ if (gPciHotPlugInit != NULL) {\r
+ //\r
+ // Check if it is a Hotplug PCI controller\r
+ //\r
+ if (IsRootPciHotPlugController (PciDevice->DevicePath, &HpIndex)) {\r
\r
- if (!gPciRootHpcData[HpIndex].Initialized) {\r
+ if (!gPciRootHpcData[HpIndex].Initialized) {\r
\r
- Status = CreateEventForHpc (HpIndex, &Event);\r
+ Status = CreateEventForHpc (HpIndex, &Event);\r
\r
- ASSERT (!EFI_ERROR (Status));\r
+ ASSERT (!EFI_ERROR (Status));\r
\r
- Status = gPciHotPlugInit->InitializeRootHpc (\r
- gPciHotPlugInit,\r
- gPciRootHpcPool[HpIndex].HpcDevicePath,\r
- PciAddress,\r
- Event,\r
- &State\r
- );\r
+ Status = gPciHotPlugInit->InitializeRootHpc (\r
+ gPciHotPlugInit,\r
+ gPciRootHpcPool[HpIndex].HpcDevicePath,\r
+ PciAddress,\r
+ Event,\r
+ &State\r
+ );\r
\r
- PreprocessController (\r
- PciDevice,\r
- PciDevice->BusNumber,\r
- PciDevice->DeviceNumber,\r
- PciDevice->FunctionNumber,\r
- EfiPciBeforeChildBusEnumeration\r
- );\r
+ PreprocessController (\r
+ PciDevice,\r
+ PciDevice->BusNumber,\r
+ PciDevice->DeviceNumber,\r
+ PciDevice->FunctionNumber,\r
+ EfiPciBeforeChildBusEnumeration\r
+ );\r
+ }\r
}\r
}\r
}\r
if (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci)) {\r
//\r
// For PPB\r
- // Get the bridge information\r
//\r
- BusPadding = FALSE;\r
- if (gPciHotPlugInit != NULL) {\r
+ if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
+ //\r
+ // If Hot Plug is not supported,\r
+ // get the bridge information\r
+ //\r
+ Status = PciSearchDevice (\r
+ Bridge,\r
+ &Pci,\r
+ StartBusNumber,\r
+ Device,\r
+ Func,\r
+ &PciDevice\r
+ );\r
\r
- if (IsRootPciHotPlugBus (PciDevice->DevicePath, &HpIndex)) {\r
-\r
- //\r
- // If it is initialized, get the padded bus range\r
- //\r
- Status = gPciHotPlugInit->GetResourcePadding (\r
- gPciHotPlugInit,\r
- gPciRootHpcPool[HpIndex].HpbDevicePath,\r
- PciAddress,\r
- &State,\r
- (VOID **) &Descriptors,\r
- &Attributes\r
- );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ } else {\r
+ //\r
+ // If Hot Plug is supported,\r
+ // Get the bridge information\r
+ //\r
+ BusPadding = FALSE;\r
+ if (gPciHotPlugInit != NULL) {\r
+\r
+ if (IsRootPciHotPlugBus (PciDevice->DevicePath, &HpIndex)) {\r
+\r
+ //\r
+ // If it is initialized, get the padded bus range\r
+ //\r
+ Status = gPciHotPlugInit->GetResourcePadding (\r
+ gPciHotPlugInit,\r
+ gPciRootHpcPool[HpIndex].HpbDevicePath,\r
+ PciAddress,\r
+ &State,\r
+ (VOID **) &Descriptors,\r
+ &Attributes\r
+ );\r
\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
- BusRange = 0;\r
- Status = PciGetBusRange (\r
- &Descriptors,\r
- NULL,\r
- NULL,\r
- &BusRange\r
- );\r
+ BusRange = 0;\r
+ Status = PciGetBusRange (\r
+ &Descriptors,\r
+ NULL,\r
+ NULL,\r
+ &BusRange\r
+ );\r
\r
- FreePool (Descriptors);\r
+ FreePool (Descriptors);\r
\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
- BusPadding = TRUE;\r
+ BusPadding = TRUE;\r
+ }\r
}\r
}\r
\r
SecondBus = *SubBusNumber;\r
\r
Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);\r
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);\r
+ Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET);\r
\r
Status = PciRootBridgeIoWrite (\r
PciRootBridgeIo,\r
if (IS_PCI_BRIDGE (&Pci)) {\r
\r
//\r
- // Initialize SubBusNumber to Maximum bus number\r
+ // Temporarily initialize SubBusNumber to maximum bus number to ensure the\r
+ // PCI configuration transaction to go through any PPB\r
//\r
Register = 0xFF;\r
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
+ Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);\r
Status = PciRootBridgeIoWrite (\r
PciRootBridgeIo,\r
&Pci,\r
EfiPciBeforeChildBusEnumeration\r
);\r
\r
- DEBUG((EFI_D_ERROR, "Scan PPB(%02d,%02d,%02d)\n", PciDevice->BusNumber, PciDevice->DeviceNumber,PciDevice->FunctionNumber ));\r
+ DEBUG((EFI_D_ERROR, "Scan PPB(%02d,%02d,%02d)\n", PciDevice->BusNumber, PciDevice->DeviceNumber,PciDevice->FunctionNumber));\r
Status = PciScanBus (\r
PciDevice,\r
(UINT8) (SecondBus),\r
SubBusNumber,\r
PaddedBusRange\r
);\r
-\r
if (EFI_ERROR (Status)) {\r
- return EFI_DEVICE_ERROR;\r
+ return Status;\r
}\r
}\r
\r
- if (BusPadding) {\r
+ if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport) && BusPadding) {\r
//\r
// Ensure the device is enabled and initialized\r
//\r
//\r
// Set the current maximum bus number under the PPB\r
//\r
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
+ Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);\r
\r
Status = PciRootBridgeIoWrite (\r
PciRootBridgeIo,\r
//\r
// Skip sub functions, this is not a multi function device\r
//\r
+\r
Func = PCI_MAX_FUNC;\r
}\r
-\r
}\r
}\r
\r
}\r
\r
/**\r
- Process Option Rom on this host bridge.\r
- \r
- @param Bridge Pci bridge device instance.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ Process Option Rom on the specified root bridge.\r
+\r
+ @param Bridge Pci root bridge device instance.\r
+\r
+ @retval EFI_SUCCESS Success process.\r
+ @retval other Some error occurred when processing Option Rom on the root bridge.\r
+\r
**/\r
EFI_STATUS\r
PciRootBridgeP2CProcess (\r
\r
if (IS_CARDBUS_BRIDGE (&Temp->Pci)) {\r
\r
- if (gPciHotPlugInit != NULL && Temp->Allocated) {\r
+ if (gPciHotPlugInit != NULL && Temp->Allocated && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
\r
//\r
// Raise the EFI_IOB_PCI_HPC_INIT status code\r
}\r
\r
/**\r
- Process Option Rom on this host bridge.\r
- \r
- @param PciResAlloc Pointer to instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
- \r
- @retval EFI_NOT_FOUND Can not find the root bridge instance.\r
+ Process Option Rom on the specified host bridge.\r
+\r
+ @param PciResAlloc Pointer to instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
+\r
@retval EFI_SUCCESS Success process.\r
+ @retval EFI_NOT_FOUND Can not find the root bridge instance.\r
+ @retval other Some error occurred when processing Option Rom on the host bridge.\r
+\r
**/\r
EFI_STATUS\r
PciHostBridgeP2CProcess (\r
}\r
\r
Status = PciRootBridgeP2CProcess (RootBridgeDev);\r
-\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
This function is used to enumerate the entire host bridge\r
in a given platform.\r
\r
- @param PciResAlloc A pointer to the resource allocate protocol.\r
+ @param PciResAlloc A pointer to the PCI Host Resource Allocation protocol.\r
\r
- @retval EFI_OUT_OF_RESOURCES no enough resource.\r
- @retval EFI_SUCCESS Success.\r
+ @retval EFI_SUCCESS Successfully enumerated the host bridge.\r
+ @retval EFI_OUT_OF_RESOURCES No enough memory available.\r
+ @retval other Some error occurred when enumerating the host bridge.\r
\r
**/\r
EFI_STATUS\r
LIST_ENTRY RootBridgeList;\r
LIST_ENTRY *Link;\r
\r
- InitializeHotPlugSupport ();\r
+ if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
+ InitializeHotPlugSupport ();\r
+ }\r
\r
InitializeListHead (&RootBridgeList);\r
\r
//\r
// Enumerate all the buses under this root bridge\r
//\r
-\r
Status = PciRootBridgeEnumerator (\r
PciResAlloc,\r
RootBridgeDev\r
);\r
\r
- if (gPciHotPlugInit != NULL) {\r
+ if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
InsertTailList (&RootBridgeList, &(RootBridgeDev->Link));\r
} else {\r
DestroyRootBridge (RootBridgeDev);\r
//\r
NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);\r
\r
- if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
-\r
- if (gPciHotPlugInit != NULL) {\r
- //\r
- // Reset all assigned PCI bus number in all PPB\r
+ if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
+ //\r
+ // Reset all assigned PCI bus number in all PPB\r
+ //\r
+ RootBridgeHandle = NULL;\r
+ Link = GetFirstNode (&RootBridgeList);\r
+ while ((PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) &&\r
+ (!IsNull (&RootBridgeList, Link))) {\r
+ RootBridgeDev = PCI_IO_DEVICE_FROM_LINK (Link);\r
//\r
- RootBridgeHandle = NULL;\r
- Link = GetFirstNode (&RootBridgeList);\r
- while ((PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) &&\r
- (!IsNull (&RootBridgeList, Link))) {\r
- RootBridgeDev = PCI_IO_DEVICE_FROM_LINK (Link);\r
- //\r
- // Get the Bus information\r
- //\r
- Status = PciResAlloc->StartBusEnumeration (\r
- PciResAlloc,\r
- RootBridgeHandle,\r
- (VOID **) &Configuration\r
- );\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Get the bus number to start with\r
- //\r
- StartBusNumber = (UINT8) (Configuration->AddrRangeMin);\r
-\r
- ResetAllPpbBusNumber (\r
- RootBridgeDev,\r
- StartBusNumber\r
- );\r
-\r
- FreePool (Configuration);\r
- Link = GetNextNode (&RootBridgeList, Link);\r
- DestroyRootBridge (RootBridgeDev);\r
- }\r
-\r
+ // Get the Bus information\r
//\r
- // Wait for all HPC initialized\r
- //\r
- Status = AllRootHPCInitialized (STALL_1_SECOND * 15);\r
-\r
+ Status = PciResAlloc->StartBusEnumeration (\r
+ PciResAlloc,\r
+ RootBridgeHandle,\r
+ (VOID **) &Configuration\r
+ );\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
//\r
- // Notify the bus allocation phase is about to start for the 2nd time\r
+ // Get the bus number to start with\r
//\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);\r
+ StartBusNumber = (UINT8) (Configuration->AddrRangeMin);\r
\r
- DEBUG((EFI_D_ERROR, "PCI Bus Second Scanning\n"));\r
- RootBridgeHandle = NULL;\r
- while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
+ ResetAllPpbBusNumber (\r
+ RootBridgeDev,\r
+ StartBusNumber\r
+ );\r
\r
- //\r
- // if a root bridge instance is found, create root bridge device for it\r
- //\r
+ FreePool (Configuration);\r
+ Link = GetNextNode (&RootBridgeList, Link);\r
+ DestroyRootBridge (RootBridgeDev);\r
+ }\r
\r
- RootBridgeDev = CreateRootBridge (RootBridgeHandle);\r
+ //\r
+ // Wait for all HPC initialized\r
+ //\r
+ Status = AllRootHPCInitialized (STALL_1_SECOND * 15);\r
\r
- if (RootBridgeDev == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
- //\r
- // Enumerate all the buses under this root bridge\r
- //\r
+ //\r
+ // Notify the bus allocation phase is about to start for the 2nd time\r
+ //\r
+ NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);\r
\r
- Status = PciRootBridgeEnumerator (\r
- PciResAlloc,\r
- RootBridgeDev\r
- );\r
+ DEBUG((EFI_D_ERROR, "PCI Bus Second Scanning\n"));\r
+ RootBridgeHandle = NULL;\r
+ while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
\r
- DestroyRootBridge (RootBridgeDev);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
+ //\r
+ // if a root bridge instance is found, create root bridge device for it\r
+ //\r
+ RootBridgeDev = CreateRootBridge (RootBridgeHandle);\r
+\r
+ if (RootBridgeDev == NULL) {\r
+ return EFI_OUT_OF_RESOURCES;\r
}\r
\r
//\r
- // Notify the bus allocation phase is to end for the 2nd time\r
+ // Enumerate all the buses under this root bridge\r
//\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);\r
+ Status = PciRootBridgeEnumerator (\r
+ PciResAlloc,\r
+ RootBridgeDev\r
+ );\r
+\r
+ DestroyRootBridge (RootBridgeDev);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
}\r
+\r
+ //\r
+ // Notify the bus allocation phase is to end for the 2nd time\r
+ //\r
+ NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);\r
}\r
\r
//\r
//\r
// if a root bridge instance is found, create root bridge device for it\r
//\r
-\r
RootBridgeDev = CreateRootBridge (RootBridgeHandle);\r
\r
if (RootBridgeDev == NULL) {\r
This function check the incompatiblilites on PCI device. Return the register\r
value.\r
\r
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param PciIo A pointer to EFI_PCI_PROTOCOL.\r
- @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.\r
+ @param PciRootBridgeIo PCI root bridge io protocol instance.\r
+ @param PciIo PCI IO protocol instance.\r
+ @param PciDeviceInfo PCI device information.\r
@param Width Signifies the width of the memory operations.\r
@param Address The address within the PCI configuration space for the PCI controller.\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_UNSUPPORTED Width is invalid for this PCI root bridge.\r
+ @retval other Some error occurred when reading PCI device configuration space\r
+ or checking incompatibility.\r
\r
**/\r
EFI_STATUS\r
UINT8 *Pointer;\r
\r
ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));\r
+ ASSERT (Buffer != NULL);\r
\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT) {\r
+ if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT) != 0) {\r
//\r
- // check access compatibility at first time\r
+ // Check access compatibility at first time\r
//\r
Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_READ, Address & 0xff, Width, &PciRegisterAccessData);\r
\r
if (Status == EFI_SUCCESS) {\r
//\r
- // there exist incompatibility on this operation\r
+ // There exists incompatibility on this operation\r
//\r
AccessWidth = Width;\r
\r
Stride = 0;\r
Pointer = (UINT8 *) &TempBuffer;\r
\r
- while (1) {\r
+ while (TRUE) {\r
\r
if (PciRootBridgeIo != NULL) {\r
Status = PciRootBridgeIo->Pci.Read (\r
AccessAddress += Stride;\r
if (AccessAddress >= (Address + LShiftU64 (1ULL, (UINTN)Width))) {\r
//\r
- // if all datas have been read, exist\r
+ // If all datas have been read, exit\r
//\r
break;\r
}\r
\r
if ((AccessAddress & 0xff) < PciRegisterAccessData->EndOffset) {\r
//\r
- // if current offset doesn't reach the end\r
+ // If current offset doesn't reach the end\r
//\r
continue;\r
}\r
\r
- FreePool (PciRegisterAccessData);\r
-\r
//\r
- // continue checking access incompatibility\r
+ // Continue checking access incompatibility\r
//\r
Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_READ, AccessAddress & 0xff, AccessWidth, &PciRegisterAccessData);\r
if (Status == EFI_SUCCESS) {\r
}\r
}\r
\r
- FreePool (PciRegisterAccessData);\r
-\r
switch (Width) {\r
case EfiPciWidthUint8:\r
* (UINT8 *) Buffer = (UINT8) TempBuffer;\r
@param Buffer Store the register data.\r
\r
@retval EFI_SUCCESS The data has been updated.\r
+ @retval EFI_UNSUPPORTED Width is invalid for this PCI root bridge.\r
+ @retval other Some error occurred when checking incompatibility.\r
\r
**/\r
EFI_STATUS\r
UINT32 OrValue;\r
UINT32 TempValue;\r
\r
+ ASSERT (Buffer != NULL);\r
+\r
//\r
- // check register value incompatibility\r
+ // Check register value incompatibility\r
//\r
Status = PciRegisterUpdateCheck (PciDeviceInfo, AccessType, Address & 0xff, &PciRegisterData);\r
-\r
if (Status == EFI_SUCCESS) {\r
\r
AndValue = ((UINT32) PciRegisterData->AndValue) >> (((UINT8) Address & 0x3) * 8);\r
default:\r
return EFI_UNSUPPORTED;\r
}\r
-\r
- FreePool (PciRegisterData);\r
}\r
\r
return Status;\r
This function check the incompatiblilites on PCI device, and write date\r
into register.\r
\r
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param PciIo A pointer to EFI_PCI_PROTOCOL.\r
- @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.\r
+ @param PciRootBridgeIo PCI root bridge io instance.\r
+ @param PciIo PCI IO protocol instance.\r
+ @param PciDeviceInfo PCI device information.\r
@param Width Signifies the width of the memory operations.\r
@param Address The address within the PCI configuration space for the PCI controller.\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval other Some error occurred when writing PCI device information\r
+ or checking incompatibility.\r
\r
**/\r
EFI_STATUS\r
UINTN Shift;\r
\r
ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));\r
+ ASSERT (Buffer != NULL);\r
\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT) {\r
+ if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT) != 0) {\r
//\r
- // check access compatibility at first time\r
+ // Check access compatibility at first time\r
//\r
Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_WRITE, Address & 0xff, Width, &PciRegisterAccessData);\r
\r
if (Status == EFI_SUCCESS) {\r
//\r
- // there exist incompatibility on this operation\r
+ // There exists incompatibility on this operation\r
//\r
AccessWidth = Width;\r
\r
Pointer = (UINT8 *) &Buffer;\r
Data = * (UINT64 *) Buffer;\r
\r
- while (1) {\r
+ while (TRUE) {\r
\r
if (AccessWidth > Width) {\r
//\r
- // if actual access width is larger than orignal one, additional data need to be read back firstly\r
+ // If actual access width is larger than orignal one, additional data need to be read back firstly\r
//\r
Status = ReadConfigData (PciRootBridgeIo, PciIo, PciDeviceInfo, AccessWidth, AccessAddress, &Data);\r
if (Status != EFI_SUCCESS) {\r
}\r
\r
//\r
- // check data read incompatibility\r
+ // Check data read incompatibility\r
//\r
UpdateConfigData (PciDeviceInfo, PCI_REGISTER_READ, AccessWidth, AccessAddress & 0xff, &Data);\r
\r
}\r
\r
//\r
- // check data write incompatibility\r
+ // Check data write incompatibility\r
//\r
UpdateConfigData (PciDeviceInfo, PCI_REGISTER_WRITE, AccessWidth, MultU64x32 (AccessAddress, 0xff), &Data);\r
}\r
AccessAddress += Stride;\r
if (AccessAddress >= (Address + LShiftU64 (1ULL, (UINTN)Width))) {\r
//\r
- // if all datas have been written, exist\r
+ // If all datas have been written, exit\r
//\r
break;\r
}\r
\r
if ((AccessAddress & 0xff) < PciRegisterAccessData->EndOffset) {\r
//\r
- // if current offset doesn't reach the end\r
+ // If current offset doesn't reach the end\r
//\r
continue;\r
}\r
\r
- FreePool (PciRegisterAccessData);\r
-\r
//\r
- // continue checking access incompatibility\r
+ // Continue checking access incompatibility\r
//\r
Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_WRITE, AccessAddress & 0xff, AccessWidth, &PciRegisterAccessData);\r
if (Status == EFI_SUCCESS) {\r
}\r
};\r
\r
- FreePool (PciRegisterAccessData);\r
-\r
return Status;\r
}\r
\r
\r
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
@param PciIo A pointer to EFI_PCI_PROTOCOL.\r
- @param Pci A pointer to PCI_TYPE00.\r
+ @param Pci PCI device configuration space.\r
@param Address The address within the PCI configuration space for the PCI controller.\r
@param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.\r
\r
@retval EFI_SUCCESS Pci device device information has been abstracted.\r
+ @retval EFI_NOT_FOUND Cannot found the specified PCI device.\r
+ @retval other Some error occurred when reading PCI device information.\r
\r
**/\r
EFI_STATUS\r
PCI_IO_DEVICE *PciIoDevice;\r
\r
ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));\r
+ ASSERT (PciDeviceInfo != NULL);\r
\r
if (PciIo != NULL) {\r
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);\r
\r
//\r
- // get pointer to PCI_TYPE00 from PciIoDevice\r
+ // Get pointer to PCI_TYPE00 from PciIoDevice\r
//\r
Pci = &PciIoDevice->Pci;\r
}\r
\r
if (Pci == NULL) {\r
//\r
- // while PCI_TYPE00 hasn't been gotten, read PCI device device information directly\r
+ // While PCI_TYPE00 hasn't been gotten, read PCI device device information directly\r
//\r
PciAddress = Address & 0xffffffffffffff00ULL;\r
Status = PciRootBridgeIo->Pci.Read (\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_UNSUPPORTED Buffer is NULL.\r
+ @retval other Some error occurred when reading PCI configuration space.\r
\r
**/\r
EFI_STATUS\r
IN UINT64 Address,\r
IN UINTN Count,\r
IN OUT VOID *Buffer\r
-)\r
+ )\r
{\r
EFI_STATUS Status;\r
EFI_PCI_DEVICE_INFO PciDeviceInfo;\r
UINT32 Stride;\r
\r
ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));\r
+ if (Buffer == NULL) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
\r
//\r
// get PCI device device information\r
//\r
// update the data read from configuration register\r
//\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) {\r
+ if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) != 0) {\r
UpdateConfigData (&PciDeviceInfo, PCI_REGISTER_READ, Width, Address & 0xff, Buffer);\r
}\r
}\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
+ valid for the PCI configuration header of the PCI controller.\r
+ Buffer is NULL.\r
+ @retval other Some error occurred when writing PCI configuration space.\r
\r
**/\r
EFI_STATUS\r
IN UINT64 Address,\r
IN UINTN Count,\r
IN OUT VOID *Buffer\r
-)\r
+ )\r
{\r
EFI_STATUS Status;\r
EFI_PCI_DEVICE_INFO PciDeviceInfo;\r
UINT64 Data;\r
\r
ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));\r
+ if (Buffer == NULL) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
\r
//\r
- // get PCI device device information\r
+ // Get PCI device device information\r
//\r
Status = GetPciDeviceDeviceInfo (PciRootBridgeIo, PciIo, Pci, Address, &PciDeviceInfo);\r
if (Status != EFI_SUCCESS) {\r
}\r
\r
//\r
- // update the data writen into configuration register\r
+ // Update the data writen into configuration register\r
//\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) {\r
+ if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) != 0) {\r
UpdateConfigData (&PciDeviceInfo, PCI_REGISTER_WRITE, Width, Address & 0xff, &Data);\r
}\r
\r
//\r
- // write configuration register\r
+ // Write configuration register\r
//\r
Status = WriteConfigData (PciRootBridgeIo, PciIo, &PciDeviceInfo, Width, Address, &Data);\r
\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
\r
**/\r
EFI_STATUS\r
IN OUT VOID *Buffer\r
)\r
{\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_READ_SUPPORT) {\r
+ EFI_STATUS Status;\r
+\r
+ if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_READ_SUPPORT) != 0) {\r
//\r
- // if PCI incompatibility check enabled\r
+ // If PCI incompatibility check enabled\r
//\r
- return PciIncompatibilityCheckRead (\r
- PciRootBridgeIo,\r
- NULL,\r
- Pci,\r
- (UINTN) Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
+ Status = PciIncompatibilityCheckRead (\r
+ PciRootBridgeIo,\r
+ NULL,\r
+ Pci,\r
+ (UINTN) Width,\r
+ Address,\r
+ Count,\r
+ Buffer\r
+ );\r
+ if (Status == EFI_UNSUPPORTED) {\r
+ return EFI_INVALID_PARAMETER;\r
+ } else {\r
+ return Status;\r
+ }\r
} else {\r
return PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo,\r
- Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
+ PciRootBridgeIo,\r
+ Width,\r
+ Address,\r
+ Count,\r
+ Buffer\r
+ );\r
}\r
}\r
\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
\r
**/\r
EFI_STATUS\r
IN OUT VOID *Buffer\r
)\r
{\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_WRITE_SUPPORT) {\r
+ EFI_STATUS Status;\r
+\r
+ if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_WRITE_SUPPORT) != 0) {\r
//\r
- // if PCI incompatibility check enabled\r
+ // If PCI incompatibility check enabled\r
//\r
- return PciIncompatibilityCheckWrite (\r
- PciRootBridgeIo,\r
- NULL,\r
- Pci,\r
- Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
+ Status = PciIncompatibilityCheckWrite (\r
+ PciRootBridgeIo,\r
+ NULL,\r
+ Pci,\r
+ Width,\r
+ Address,\r
+ Count,\r
+ Buffer\r
+ );\r
+ if (Status == EFI_UNSUPPORTED) {\r
+ return EFI_INVALID_PARAMETER;\r
+ } else {\r
+ return Status;\r
+ }\r
\r
} else {\r
return PciRootBridgeIo->Pci.Write (\r
- PciRootBridgeIo,\r
- Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
+ PciRootBridgeIo,\r
+ Width,\r
+ Address,\r
+ Count,\r
+ Buffer\r
+ );\r
}\r
}\r
\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
+ @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
+ valid for the PCI configuration header of the PCI controller.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
\r
**/\r
EFI_STATUS\r
IN OUT VOID *Buffer\r
)\r
{\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_READ_SUPPORT) {\r
+ if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_READ_SUPPORT) != 0) {\r
//\r
- // if PCI incompatibility check enabled\r
+ // If PCI incompatibility check enabled\r
//\r
return PciIncompatibilityCheckRead (\r
- NULL,\r
- PciIo,\r
- NULL,\r
- (UINTN) Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
+ NULL,\r
+ PciIo,\r
+ NULL,\r
+ (UINTN) Width,\r
+ Address,\r
+ Count,\r
+ Buffer\r
+ );\r
} else {\r
return PciIo->Pci.Read (\r
- PciIo,\r
- Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
+ PciIo,\r
+ Width,\r
+ Address,\r
+ Count,\r
+ Buffer\r
+ );\r
}\r
}\r
\r
/**\r
Write PCI configuration space through EFI_PCI_IO_PROTOCOL.\r
\r
- @param PciIo A pointer to the EFI_PCI_O_PROTOCOL.\r
- @param Width Signifies the width of the memory operations.\r
- @param Address The address within the PCI configuration space for the PCI controller.\r
- @param Count The number of unit to be read.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
+ If PCI incompatibility check is enabled, do incompatibility check.\r
\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @param PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param Width Signifies the width of the memory operations.\r
+ @param Offset The offset within the PCI configuration space for the PCI controller.\r
+ @param Count The number of PCI configuration operations to perform.\r
+ @param Buffer For read operations, the destination buffer to store the results. For write\r
+ operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
+ @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
+ valid for the PCI configuration header of the PCI controller.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
\r
**/\r
EFI_STATUS\r
IN OUT VOID *Buffer\r
)\r
{\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_WRITE_SUPPORT) {\r
-\r
+ if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_WRITE_SUPPORT) != 0) {\r
//\r
- // if PCI incompatibility check enabled\r
+ // If PCI incompatibility check enabled\r
//\r
return PciIncompatibilityCheckWrite (\r
- NULL,\r
- PciIo,\r
- NULL,\r
- Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
+ NULL,\r
+ PciIo,\r
+ NULL,\r
+ Width,\r
+ Address,\r
+ Count,\r
+ Buffer\r
+ );\r
\r
} else {\r
return PciIo->Pci.Write (\r
- PciIo,\r
- Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
+ PciIo,\r
+ Width,\r
+ Address,\r
+ Count,\r
+ Buffer\r
+ );\r
}\r
}\r
\r
/** @file\r
+ Internal library declaration for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2007, Intel Corporation\r
+Copyright (c) 2006 - 2009, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
-Module Name:\r
-\r
- PciLib.h\r
-\r
-Abstract:\r
-\r
- PCI Bus Driver Lib header file.\r
- Please use PCD feature flag PcdPciBusHotplugDeviceSupport to enable\r
- support hot plug.\r
-\r
-Revision History\r
-\r
**/\r
\r
#ifndef _EFI_PCI_LIB_H_\r
\r
\r
/**\r
- Retrieve the BAR information via PciIo interface.\r
- \r
- @param PciIoDevice Pci device instance.\r
+ Retrieve the PCI Card device BAR information via PciIo interface.\r
+\r
+ @param PciIoDevice PCI Card device instance.\r
+\r
**/\r
VOID\r
GetBackPcCardBar (\r
/**\r
Remove rejected pci device from specific root bridge\r
handle.\r
- \r
- @param RootBridgeHandle specific parent root bridge handle.\r
+\r
+ @param RootBridgeHandle Specific parent root bridge handle.\r
@param Bridge Bridge device instance.\r
- \r
- @retval EFI_SUCCESS Success operation.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
RemoveRejectedPciDevices (\r
- EFI_HANDLE RootBridgeHandle,\r
- IN PCI_IO_DEVICE *Bridge\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN PCI_IO_DEVICE *Bridge\r
);\r
\r
/**\r
- Wrapper function for allocating resource for pci host bridge.\r
- \r
- @param PciResAlloc Point to protocol instance EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
- \r
+ Submits the I/O and memory resource requirements for the specified PCI Host Bridge.\r
+\r
+ @param PciResAlloc Point to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
+\r
+ @retval EFI_SUCCESS Successfully finished resource allocation.\r
+ @retval EFI_NOT_FOUND Cannot get root bridge instance.\r
+ @retval EFI_OUT_OF_RESOURCES Platform failed to program the resources if no hot plug supported.\r
+ @retval other Some error occurred when allocating resources for the PCI Host Bridge.\r
+\r
+ @note Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.\r
+\r
**/\r
EFI_STATUS\r
PciHostBridgeResourceAllocator (\r
);\r
\r
/**\r
- Wrapper function for allocating resource for pci host bridge without hotplug device support.\r
- \r
- @param PciResAlloc Point to protocol instance EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
- \r
-**/\r
-EFI_STATUS\r
-PciHostBridgeResourceAllocator_WithoutHotPlugDeviceSupport (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
- );\r
+ Scan pci bus and assign bus number to the given PCI bus system.\r
\r
-/**\r
- Wrapper function for allocating resource for pci host bridge with hotplug device support.\r
- \r
- @param PciResAlloc Point to protocol instance EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
- \r
-**/\r
-EFI_STATUS\r
-PciHostBridgeResourceAllocator_WithHotPlugDeviceSupport (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
- );\r
+ @param Bridge Bridge device instance.\r
+ @param StartBusNumber start point.\r
+ @param SubBusNumber Point to sub bus number.\r
+ @param PaddedBusRange Customized bus number.\r
+\r
+ @retval EFI_SUCCESS Successfully scanned and assigned bus number.\r
+ @retval other Some error occurred when scanning pci bus.\r
+\r
+ @note Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.\r
\r
-/**\r
- Wapper function of scanning pci bus and assign bus number to the given PCI bus system\r
- Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug. \r
- \r
- @param Bridge Bridge device instance.\r
- @param StartBusNumber start point.\r
- @param SubBusNumber Point to sub bus number.\r
- @param PaddedBusRange Customized bus number.\r
- \r
- @retval EFI_SUCCESS Success.\r
- @retval EFI_DEVICE_ERROR Fail to scan bus.\r
**/\r
EFI_STATUS\r
PciScanBus (\r
);\r
\r
/**\r
- Wapper function of scanning pci bus and assign bus number to the given PCI bus system\r
- Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug. \r
- \r
- @param Bridge Bridge device instance.\r
- @param StartBusNumber start point.\r
- @param SubBusNumber Point to sub bus number.\r
- @param PaddedBusRange Customized bus number.\r
- \r
- @retval EFI_SUCCESS Success.\r
- @retval EFI_DEVICE_ERROR Fail to scan bus.\r
-**/\r
-EFI_STATUS\r
-PciScanBus_WithHotPlugDeviceSupport (\r
- IN PCI_IO_DEVICE *Bridge,\r
- IN UINT8 StartBusNumber,\r
- OUT UINT8 *SubBusNumber,\r
- OUT UINT8 *PaddedBusRange\r
- );\r
+ Process Option Rom on the specified root bridge.\r
\r
-/**\r
- Wapper function of scanning pci bus and assign bus number to the given PCI bus system\r
- Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug. \r
- \r
- @param Bridge Bridge device instance.\r
- @param StartBusNumber start point.\r
- @param SubBusNumber Point to sub bus number.\r
- @param PaddedBusRange Customized bus number.\r
- \r
- @retval EFI_SUCCESS Success.\r
- @retval EFI_DEVICE_ERROR Fail to scan bus.\r
-**/\r
-EFI_STATUS\r
-PciScanBus_WithoutHotPlugDeviceSupport (\r
- IN PCI_IO_DEVICE *Bridge,\r
- IN UINT8 StartBusNumber,\r
- OUT UINT8 *SubBusNumber,\r
- OUT UINT8 *PaddedBusRange\r
- );\r
+ @param Bridge Pci root bridge device instance.\r
+\r
+ @retval EFI_SUCCESS Success process.\r
+ @retval other Some error occurred when processing Option Rom on the root bridge.\r
\r
-/**\r
- Process Option Rom on this host bridge.\r
- \r
- @param Bridge Pci bridge device instance.\r
- \r
- @retval EFI_SUCCESS Success.\r
**/\r
EFI_STATUS\r
PciRootBridgeP2CProcess (\r
);\r
\r
/**\r
- Process Option Rom on this host bridge.\r
- \r
- @param PciResAlloc Pointer to instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
- \r
- @retval EFI_NOT_FOUND Can not find the root bridge instance.\r
+ Process Option Rom on the specified host bridge.\r
+\r
+ @param PciResAlloc Pointer to instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
+\r
@retval EFI_SUCCESS Success process.\r
+ @retval EFI_NOT_FOUND Can not find the root bridge instance.\r
+ @retval other Some error occurred when processing Option Rom on the host bridge.\r
+\r
**/\r
EFI_STATUS\r
PciHostBridgeP2CProcess (\r
This function is used to enumerate the entire host bridge\r
in a given platform.\r
\r
- @param PciResAlloc A pointer to the resource allocate protocol.\r
+ @param PciResAlloc A pointer to the PCI Host Resource Allocation protocol.\r
\r
- @retval EFI_OUT_OF_RESOURCES no enough resource.\r
- @retval EFI_SUCCESS Success.\r
+ @retval EFI_SUCCESS Successfully enumerated the host bridge.\r
+ @retval EFI_OUT_OF_RESOURCES No enough memory available.\r
+ @retval other Some error occurred when enumerating the host bridge.\r
\r
**/\r
EFI_STATUS\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
+ @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
+ valid for the PCI configuration header of the PCI controller.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
\r
**/\r
EFI_STATUS\r
/**\r
Write PCI configuration space through EFI_PCI_IO_PROTOCOL.\r
\r
- @param PciIo A pointer to the EFI_PCI_O_PROTOCOL.\r
- @param Width Signifies the width of the memory operations.\r
- @param Address The address within the PCI configuration space for the PCI controller.\r
- @param Count The number of unit to be write.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
+ If PCI incompatibility check is enabled, do incompatibility check.\r
+\r
+ @param PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param Width Signifies the width of the memory operations.\r
+ @param Offset The offset within the PCI configuration space for the PCI controller.\r
+ @param Count The number of PCI configuration operations to perform.\r
+ @param Buffer For read operations, the destination buffer to store the results. For write\r
+ operations, the source buffer to write data from.\r
\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
+ @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
+ valid for the PCI configuration header of the PCI controller.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
\r
**/\r
EFI_STATUS\r
@param Pci A pointer to PCI_TYPE00.\r
@param Width Signifies the width of the memory operations.\r
@param Address The address within the PCI configuration space for the PCI controller.\r
- @param Count The number of unit to be write.\r
+ @param Count The number of unit to be read.\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
\r
**/\r
EFI_STATUS\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
\r
**/\r
EFI_STATUS\r
PciRootBridgeIoRead (\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
- IN PCI_TYPE00 *Pci, OPTIONAL\r
+ IN PCI_TYPE00 *Pci, OPTIONAL\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 Address,\r
IN UINTN Count,\r
/** @file\r
+ PCI Rom supporting funtions implementation for PCI Bus module.\r
\r
Copyright (c) 2006 - 2009, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
**/\r
\r
#include "PciBus.h"\r
-#include "PciResourceSupport.h"\r
-\r
-#include <IndustryStandard/Pci23.h>\r
\r
/**\r
Load the EFI Image from Option ROM\r
- \r
- @param PciIoDevice PCI IO Device\r
+\r
+ @param PciIoDevice PCI IO device instance.\r
@param FilePath The file path of the EFI Image\r
- @param BufferSize On input the size of Buffer in bytes. On output with a return \r
- code of EFI_SUCCESS, the amount of data transferred to Buffer. \r
- On output with a return code of EFI_BUFFER_TOO_SMALL, \r
- the size of Buffer required to retrieve the requested file. \r
- @param Buffer The memory buffer to transfer the file to. If Buffer is NULL, \r
+ @param BufferSize On input the size of Buffer in bytes. On output with a return\r
+ code of EFI_SUCCESS, the amount of data transferred to Buffer.\r
+ On output with a return code of EFI_BUFFER_TOO_SMALL,\r
+ the size of Buffer required to retrieve the requested file.\r
+ @param Buffer The memory buffer to transfer the file to. If Buffer is NULL,\r
then no the size of the requested file is returned in BufferSize.\r
\r
- @retval EFI_SUCCESS The file was loaded. \r
- @retval EFI_UNSUPPORTED BootPolicy is TRUE.\r
+ @retval EFI_SUCCESS The file was loaded.\r
+ @retval EFI_INVALID_PARAMETER FilePath is not a valid device path, or\r
+ BufferSize is NULL.\r
+ @retval EFI_NOT_FOUND Not found PCI Option Rom on PCI device.\r
+ @retval EFI_DEVICE_ERROR Failed to decompress PCI Option Rom image.\r
@retval EFI_BUFFER_TOO_SMALL The BufferSize is too small to read the current directory entry.\r
BufferSize has been updated with the size needed to complete the request.\r
**/\r
) {\r
return EFI_INVALID_PARAMETER;\r
}\r
- \r
+\r
EfiRomHeader = (EFI_PCI_EXPANSION_ROM_HEADER *) (\r
(UINT8 *) PciIoDevice->PciIo.RomImage + EfiOpRomImageNode->StartingOffset\r
);\r
return EFI_NOT_FOUND;\r
}\r
\r
- \r
+\r
Pcir = (PCI_DATA_STRUCTURE *) ((UINT8 *) EfiRomHeader + EfiRomHeader->PcirOffset);\r
\r
- \r
- if ((Pcir->CodeType == PCI_CODE_TYPE_EFI_IMAGE) && \r
+\r
+ if ((Pcir->CodeType == PCI_CODE_TYPE_EFI_IMAGE) &&\r
(EfiRomHeader->EfiSignature == EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE) &&\r
((EfiRomHeader->EfiSubsystem == EFI_IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER) ||\r
(EfiRomHeader->EfiSubsystem == EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER)) &&\r
);\r
if (EFI_ERROR (Status)) {\r
return EFI_DEVICE_ERROR;\r
- } \r
- \r
+ }\r
+\r
if (Buffer == NULL || *BufferSize < DestinationSize) {\r
*BufferSize = DestinationSize;\r
return EFI_BUFFER_TOO_SMALL;\r
- } \r
+ }\r
\r
*BufferSize = DestinationSize;\r
Scratch = AllocatePool (ScratchSize);\r
if (Scratch == NULL) {\r
return EFI_DEVICE_ERROR;\r
}\r
- \r
+\r
Status = Decompress->Decompress (\r
Decompress,\r
ImageBuffer,\r
ScratchSize\r
);\r
FreePool (Scratch);\r
- \r
+\r
if (EFI_ERROR (Status)) {\r
return EFI_DEVICE_ERROR;\r
}\r
\r
/**\r
Initialize a PCI LoadFile2 instance.\r
- \r
+\r
@param PciIoDevice PCI IO Device.\r
\r
**/\r
VOID\r
InitializePciLoadFile2 (\r
- PCI_IO_DEVICE *PciIoDevice\r
+ IN PCI_IO_DEVICE *PciIoDevice\r
)\r
{\r
PciIoDevice->LoadFile2.LoadFile = LoadFile2;\r
\r
/**\r
Causes the driver to load a specified file.\r
- \r
+\r
@param This Indicates a pointer to the calling context.\r
@param FilePath The device specific path of the file to load.\r
@param BootPolicy Should always be FALSE.\r
- @param BufferSize On input the size of Buffer in bytes. On output with a return \r
- code of EFI_SUCCESS, the amount of data transferred to Buffer. \r
- On output with a return code of EFI_BUFFER_TOO_SMALL, \r
- the size of Buffer required to retrieve the requested file. \r
- @param Buffer The memory buffer to transfer the file to. If Buffer is NULL, \r
- then no the size of the requested file is returned in BufferSize.\r
-\r
- @retval EFI_SUCCESS The file was loaded. \r
+ @param BufferSize On input the size of Buffer in bytes. On output with a return\r
+ code of EFI_SUCCESS, the amount of data transferred to Buffer.\r
+ On output with a return code of EFI_BUFFER_TOO_SMALL,\r
+ the size of Buffer required to retrieve the requested file.\r
+ @param Buffer The memory buffer to transfer the file to. If Buffer is NULL,\r
+ then no the size of the requested file is returned in BufferSize.\r
+\r
+ @retval EFI_SUCCESS The file was loaded.\r
@retval EFI_UNSUPPORTED BootPolicy is TRUE.\r
+ @retval EFI_INVALID_PARAMETER FilePath is not a valid device path, or\r
+ BufferSize is NULL.\r
+ @retval EFI_NOT_FOUND Not found PCI Option Rom on PCI device.\r
+ @retval EFI_DEVICE_ERROR Failed to decompress PCI Option Rom image.\r
@retval EFI_BUFFER_TOO_SMALL The BufferSize is too small to read the current directory entry.\r
BufferSize has been updated with the size needed to complete the request.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
);\r
}\r
\r
-\r
-//\r
-// Module global for a template of the PCI option ROM Image Device Path Node\r
-//\r
-MEMMAP_DEVICE_PATH mPciOptionRomImageDevicePathNodeTemplate = {\r
- {\r
- HARDWARE_DEVICE_PATH,\r
- HW_MEMMAP_DP,\r
- {\r
- (UINT8) (sizeof (MEMMAP_DEVICE_PATH)),\r
- (UINT8) ((sizeof (MEMMAP_DEVICE_PATH)) >> 8)\r
- }\r
- },\r
- EfiMemoryMappedIO,\r
- 0,\r
- 0\r
-};\r
-\r
/**\r
Get Pci device's oprom infor bits.\r
- \r
- @param PciIoDevice Pci device instance\r
\r
- @retval EFI_NOT_FOUND Pci device has not oprom\r
- @retval EFI_SUCCESS Pci device has oprom\r
+ @param PciIoDevice Pci device instance.\r
+\r
+ @retval EFI_NOT_FOUND Pci device has not Option Rom.\r
+ @retval EFI_SUCCESS Pci device has Option Rom.\r
+\r
**/\r
EFI_STATUS\r
GetOpRomInfo (\r
PciRootBridgeIo = PciIoDevice->PciRootBridgeIo;\r
\r
//\r
- // offset is 0x30 if is not ppb\r
+ // Offset is 0x30 if is not ppb\r
//\r
\r
//\r
\r
if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {\r
//\r
- // if is ppb\r
+ // If is ppb\r
//\r
\r
//\r
RomBarIndex = PCI_BRIDGE_ROMBAR;\r
}\r
//\r
- // the bit0 is 0 to prevent the enabling of the Rom address decoder\r
+ // The bit0 is 0 to prevent the enabling of the Rom address decoder\r
//\r
AllOnes = 0xfffffffe;\r
Address = EFI_PCI_ADDRESS (Bus, Device, Function, RomBarIndex);\r
&AllOnes\r
);\r
if (EFI_ERROR (Status)) {\r
- return Status;\r
+ return EFI_NOT_FOUND;\r
}\r
\r
//\r
- // read back\r
+ // Read back\r
//\r
Status = PciRootBridgeIoRead (\r
PciRootBridgeIo,\r
&AllOnes\r
);\r
if (EFI_ERROR (Status)) {\r
- return Status;\r
+ return EFI_NOT_FOUND;\r
}\r
//\r
// Bits [1, 10] are reserved\r
}\r
\r
/**\r
-\r
Check if the RomImage contains EFI Images.\r
\r
- @param RomImage The ROM address of Image for check. \r
+ @param RomImage The ROM address of Image for check.\r
@param RomSize Size of ROM for check.\r
\r
@retval TRUE ROM contain EFI Image.\r
@retval FALSE ROM not contain EFI Image.\r
- \r
+\r
**/\r
BOOLEAN\r
ContainEfiImage (\r
IN VOID *RomImage,\r
IN UINT64 RomSize\r
- ) \r
+ )\r
{\r
PCI_EXPANSION_ROM_HEADER *RomHeader;\r
PCI_DATA_STRUCTURE *RomPcir;\r
\r
FirstCheck = TRUE;\r
RomHeader = RomImage;\r
- \r
+\r
while ((UINT8 *) RomHeader < (UINT8 *) RomImage + RomSize) {\r
if (RomHeader->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) {\r
if (FirstCheck) {\r
\r
FirstCheck = FALSE;\r
RomPcir = (PCI_DATA_STRUCTURE *) ((UINT8 *) RomHeader + RomHeader->PcirOffset);\r
- \r
+\r
if (RomPcir->CodeType == PCI_CODE_TYPE_EFI_IMAGE) {\r
return TRUE;\r
}\r
\r
\r
/**\r
- Load option rom image for specified PCI device\r
- \r
- @param PciDevice Pci device instance\r
- @param RomBase Base address of oprom.\r
- \r
- @retval EFI_OUT_OF_RESOURCES not enough memory to hold image\r
- @retval EFI_SUCESS Success\r
+ Load Option Rom image for specified PCI device.\r
+\r
+ @param PciDevice Pci device instance.\r
+ @param RomBase Base address of Option Rom.\r
+\r
+ @retval EFI_OUT_OF_RESOURCES No enough memory to hold image.\r
+ @retval EFI_SUCESS Successfully loaded Option Rom.\r
+\r
**/\r
EFI_STATUS\r
LoadOpRomImage (\r
}\r
\r
/**\r
- enable/disable oprom decode\r
- \r
- @param PciDevice pci device instance\r
+ Enable/Disable Option Rom decode.\r
+\r
+ @param PciDevice Pci device instance.\r
@param RomBarIndex The BAR index of the standard PCI Configuration header to use as the\r
base address for resource range. The legal range for this field is 0..5.\r
- @param RomBar Base address of rom\r
+ @param RomBar Base address of Option Rom.\r
@param Enable Flag for enable/disable decode.\r
- \r
- @retval EFI_SUCCESS Success\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
RomDecode (\r
IN PCI_IO_DEVICE *PciDevice,\r
IN UINT8 RomBarIndex,\r
);\r
\r
}\r
-\r
- return EFI_SUCCESS;\r
-\r
}\r
\r
/**\r
- Process the oprom image.\r
- \r
- @param PciDevice Pci device instance\r
+ Load and start the Option Rom image.\r
+\r
+ @param PciDevice Pci device instance.\r
+\r
+ @retval EFI_SUCCESS Successfully loaded and started PCI Option Rom image.\r
+ @retval EFI_NOT_FOUND Failed to process PCI Option Rom image.\r
+\r
**/\r
EFI_STATUS\r
ProcessOpRomImage (\r
- PCI_IO_DEVICE *PciDevice\r
+ IN PCI_IO_DEVICE *PciDevice\r
)\r
{\r
- UINT8 Indicator;\r
- UINT32 ImageSize;\r
- VOID *RomBar;\r
- UINT8 *RomBarOffset;\r
- EFI_HANDLE ImageHandle;\r
- EFI_STATUS Status;\r
- EFI_STATUS RetStatus;\r
- BOOLEAN FirstCheck;\r
- EFI_PCI_EXPANSION_ROM_HEADER *EfiRomHeader;\r
- PCI_DATA_STRUCTURE *Pcir;\r
- EFI_DEVICE_PATH_PROTOCOL *PciOptionRomImageDevicePath;\r
-\r
- MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH EfiOpRomImageNode; \r
- VOID *Buffer;\r
- UINTN BufferSize;\r
+ UINT8 Indicator;\r
+ UINT32 ImageSize;\r
+ VOID *RomBar;\r
+ UINT8 *RomBarOffset;\r
+ EFI_HANDLE ImageHandle;\r
+ EFI_STATUS Status;\r
+ EFI_STATUS RetStatus;\r
+ BOOLEAN FirstCheck;\r
+ EFI_PCI_EXPANSION_ROM_HEADER *EfiRomHeader;\r
+ PCI_DATA_STRUCTURE *Pcir;\r
+ EFI_DEVICE_PATH_PROTOCOL *PciOptionRomImageDevicePath;\r
+ MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH EfiOpRomImageNode;\r
+ VOID *Buffer;\r
+ UINTN BufferSize;\r
\r
Indicator = 0;\r
\r
//\r
- // Get the Address of the Rom image\r
+ // Get the Address of the Option Rom image\r
//\r
RomBar = PciDevice->PciIo.RomImage;\r
RomBarOffset = (UINT8 *) RomBar;\r
//\r
// load image and start image\r
//\r
-\r
BufferSize = 0;\r
Buffer = NULL;\r
Status = EFI_SUCCESS;\r
} while (((Indicator & 0x80) == 0x00) && ((UINTN) (RomBarOffset - (UINT8 *) RomBar) < PciDevice->RomSize));\r
\r
return RetStatus;\r
-\r
}\r
\r
/** @file\r
+ PCI Rom supporting funtions declaration for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2009, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
-#ifndef _EFI_PCI_OP_ROM_SUPPORT_H_\r
-#define _EFI_PCI_OP_ROM_SUPPORT_H_\r
+#ifndef _EFI_PCI_OPTION_ROM_SUPPORT_H_\r
+#define _EFI_PCI_OPTION_ROM_SUPPORT_H_\r
\r
-#include <Protocol/LoadFile2.h>\r
\r
/**\r
Initialize a PCI LoadFile2 instance.\r
- \r
+\r
@param PciIoDevice PCI IO Device.\r
\r
**/\r
VOID\r
InitializePciLoadFile2 (\r
- PCI_IO_DEVICE *PciIoDevice\r
+ IN PCI_IO_DEVICE *PciIoDevice\r
);\r
\r
/**\r
Causes the driver to load a specified file.\r
- \r
+\r
@param This Indicates a pointer to the calling context.\r
@param FilePath The device specific path of the file to load.\r
@param BootPolicy Should always be FALSE.\r
- @param BufferSize On input the size of Buffer in bytes. On output with a return \r
- code of EFI_SUCCESS, the amount of data transferred to Buffer. \r
- On output with a return code of EFI_BUFFER_TOO_SMALL, \r
- the size of Buffer required to retrieve the requested file. \r
- @param Buffer The memory buffer to transfer the file to. If Buffer is NULL, \r
+ @param BufferSize On input the size of Buffer in bytes. On output with a return\r
+ code of EFI_SUCCESS, the amount of data transferred to Buffer.\r
+ On output with a return code of EFI_BUFFER_TOO_SMALL,\r
+ the size of Buffer required to retrieve the requested file.\r
+ @param Buffer The memory buffer to transfer the file to. If Buffer is NULL,\r
then no the size of the requested file is returned in BufferSize.\r
\r
- @retval EFI_SUCCESS The file was loaded. \r
+ @retval EFI_SUCCESS The file was loaded.\r
@retval EFI_UNSUPPORTED BootPolicy is TRUE.\r
+ @retval EFI_INVALID_PARAMETER FilePath is not a valid device path, or\r
+ BufferSize is NULL.\r
+ @retval EFI_NOT_FOUND Not found PCI Option Rom on PCI device.\r
+ @retval EFI_DEVICE_ERROR Failed to decompress PCI Option Rom image.\r
@retval EFI_BUFFER_TOO_SMALL The BufferSize is too small to read the current directory entry.\r
BufferSize has been updated with the size needed to complete the request.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
);\r
\r
/**\r
-\r
Check if the RomImage contains EFI Images.\r
\r
- @param RomImage The ROM address of Image for check. \r
+ @param RomImage The ROM address of Image for check.\r
@param RomSize Size of ROM for check.\r
\r
@retval TRUE ROM contain EFI Image.\r
@retval FALSE ROM not contain EFI Image.\r
- \r
+\r
**/\r
BOOLEAN\r
ContainEfiImage (\r
IN VOID *RomImage,\r
IN UINT64 RomSize\r
- ); \r
+ );\r
\r
\r
/**\r
Get Pci device's oprom infor bits.\r
- \r
- @param PciIoDevice Pci device instance\r
\r
- @retval EFI_NOT_FOUND Pci device has not oprom\r
- @retval EFI_SUCCESS Pci device has oprom\r
+ @param PciIoDevice Pci device instance.\r
+\r
+ @retval EFI_NOT_FOUND Pci device has not Option Rom.\r
+ @retval EFI_SUCCESS Pci device has Option Rom.\r
+\r
**/\r
EFI_STATUS\r
GetOpRomInfo (\r
);\r
\r
/**\r
- Load option rom image for specified PCI device\r
- \r
- @param PciDevice Pci device instance\r
- @param RomBase Base address of oprom.\r
- \r
- @retval EFI_OUT_OF_RESOURCES not enough memory to hold image\r
- @retval EFI_SUCESS Success\r
+ Load Option Rom image for specified PCI device.\r
+\r
+ @param PciDevice Pci device instance.\r
+ @param RomBase Base address of Option Rom.\r
+\r
+ @retval EFI_OUT_OF_RESOURCES No enough memory to hold image.\r
+ @retval EFI_SUCESS Successfully loaded Option Rom.\r
+\r
**/\r
EFI_STATUS\r
LoadOpRomImage (\r
);\r
\r
/**\r
- enable/disable oprom decode\r
- \r
- @param PciDevice pci device instance\r
+ Enable/Disable Option Rom decode.\r
+\r
+ @param PciDevice Pci device instance.\r
@param RomBarIndex The BAR index of the standard PCI Configuration header to use as the\r
base address for resource range. The legal range for this field is 0..5.\r
- @param RomBar Base address of rom\r
+ @param RomBar Base address of Option Rom.\r
@param Enable Flag for enable/disable decode.\r
- \r
- @retval EFI_SUCCESS Success\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
RomDecode (\r
IN PCI_IO_DEVICE *PciDevice,\r
IN UINT8 RomBarIndex,\r
);\r
\r
/**\r
- Process the oprom image.\r
- \r
- @param PciDevice Pci device instance\r
+ Load and start the Option Rom image.\r
+\r
+ @param PciDevice Pci device instance.\r
+\r
+ @retval EFI_SUCCESS Successfully loaded and started PCI Option Rom image.\r
+ @retval EFI_NOT_FOUND Failed to process PCI Option Rom image.\r
+\r
**/\r
EFI_STATUS\r
ProcessOpRomImage (\r
- PCI_IO_DEVICE *PciDevice\r
+ IN PCI_IO_DEVICE *PciDevice\r
);\r
\r
#endif\r
/** @file\r
+ Power management support fucntions implementation for PCI Bus module.\r
\r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
put the device to D0 state if the device supports\r
PCI Power Management.\r
\r
- @param PciIoDevice Pci device instance\r
+ @param PciIoDevice PCI device instance.\r
+\r
+ @retval EFI_UNSUPPORTED PCI Device does not support power management.\r
+ @retval EFI_SUCCESS Turned off PWE successfully.\r
\r
- @retval EFI_UNSUPPORTED Device do not support power management\r
- @retval EFI_SUCCESS Success\r
**/\r
EFI_STATUS\r
ResetPowerManagementFeature (\r
/** @file\r
+ Power management support fucntions delaration for PCI Bus module.\r
\r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
put the device to D0 state if the device supports\r
PCI Power Management.\r
\r
- @param PciIoDevice Pci device instance\r
+ @param PciIoDevice PCI device instance.\r
+\r
+ @retval EFI_UNSUPPORTED PCI Device does not support power management.\r
+ @retval EFI_SUCCESS Turned off PWE successfully.\r
\r
- @retval EFI_UNSUPPORTED Device do not support power management\r
- @retval EFI_SUCCESS Success\r
**/\r
EFI_STATUS\r
ResetPowerManagementFeature (\r
/** @file\r
+ PCI resouces support functions implemntation for PCI Bus module.\r
\r
Copyright (c) 2006 - 2009, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
**/\r
\r
#include "PciBus.h"\r
-#include "PciResourceSupport.h"\r
-#include "PciCommand.h"\r
\r
/**\r
- The function is used to skip VGA range\r
- \r
- @param Start address including VGA range\r
- @param Length length of VGA range.\r
- \r
- @retval EFI_SUCCESS success.\r
+ The function is used to skip VGA range.\r
+\r
+ @param Start Returned start address including VGA range.\r
+ @param Length The length of VGA range.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
SkipVGAAperture (\r
OUT UINT64 *Start,\r
IN UINT64 Length\r
UINT64 StartOffset;\r
UINT64 LimitOffset;\r
\r
+ ASSERT (Start != NULL);\r
//\r
// For legacy VGA, bit 10 to bit 15 is not decoded\r
//\r
if (LimitOffset >= VGABASE1) {\r
*Start = *Start - StartOffset + VGALIMIT2 + 1;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
This function is used to skip ISA aliasing aperture.\r
- \r
- @param Start address including ISA aliasing aperture.\r
- @param Length length of ISA aliasing aperture.\r
- \r
- @retval EFI_SUCCESS success.\r
+\r
+ @param Start Returned start address including ISA aliasing aperture.\r
+ @param Length The length of ISA aliasing aperture.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
SkipIsaAliasAperture (\r
OUT UINT64 *Start,\r
IN UINT64 Length\r
UINT64 StartOffset;\r
UINT64 LimitOffset;\r
\r
+ ASSERT (Start != NULL);\r
+\r
//\r
// For legacy ISA, bit 10 to bit 15 is not decoded\r
//\r
if (LimitOffset >= ISABASE) {\r
*Start = *Start - StartOffset + ISALIMIT + 1;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
\r
@param Bridge PCI resource node for bridge.\r
@param ResNode Resource node want to be inserted.\r
- \r
- @retval EFI_SUCCESS Success.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
InsertResourceNode (\r
- PCI_RESOURCE_NODE *Bridge,\r
- PCI_RESOURCE_NODE *ResNode\r
+ IN PCI_RESOURCE_NODE *Bridge,\r
+ IN PCI_RESOURCE_NODE *ResNode\r
)\r
{\r
LIST_ENTRY *CurrentLink;\r
\r
CurrentLink = ResNode->Link.ForwardLink;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
+ This routine is used to merge two different resource trees in need of\r
+ resoure degradation.\r
\r
-Routine Description:\r
-\r
- This routine is used to merge two different resource tree in need of\r
- resoure degradation. For example, if a upstream PPB doesn't support,\r
+ For example, if an upstream PPB doesn't support,\r
prefetchable memory decoding, the PCI bus driver will choose to call this function\r
to merge prefectchable memory resource list into normal memory list.\r
\r
If the TypeMerge is TRUE, Res resource type is changed to the type of destination resource\r
type.\r
+ If Dst is NULL or Res is NULL, ASSERT ().\r
\r
@param Dst Point to destination resource tree.\r
@param Res Point to source resource tree.\r
- @param TypeMerge If the TypeMerge is TRUE, Res resource type is changed to the type of \r
+ @param TypeMerge If the TypeMerge is TRUE, Res resource type is changed to the type of\r
destination resource type.\r
- \r
- \r
- @retval EFI_SUCCESS Success.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
MergeResourceTree (\r
- PCI_RESOURCE_NODE *Dst,\r
- PCI_RESOURCE_NODE *Res,\r
- BOOLEAN TypeMerge\r
+ IN PCI_RESOURCE_NODE *Dst,\r
+ IN PCI_RESOURCE_NODE *Res,\r
+ IN BOOLEAN TypeMerge\r
)\r
{\r
\r
\r
RemoveEntryList (CurrentLink);\r
InsertResourceNode (Dst, Temp);\r
-\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
This function is used to calculate the IO16 aperture\r
for a bridge.\r
\r
- @param Bridge PCI resource node for bridge.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ @param Bridge PCI resource node for bridge.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
CalculateApertureIo16 (\r
- IN PCI_RESOURCE_NODE *Bridge\r
+ IN PCI_RESOURCE_NODE *Bridge\r
)\r
{\r
EFI_STATUS Status;\r
BOOLEAN IsaEnable;\r
BOOLEAN VGAEnable;\r
EFI_PCI_PLATFORM_POLICY PciPolicy;\r
- \r
\r
//\r
// Always assume there is ISA device and VGA device on the platform\r
&PciPolicy\r
);\r
if (!EFI_ERROR (Status)) {\r
- if (PciPolicy & EFI_RESERVE_ISA_IO_ALIAS) {\r
+ if ((PciPolicy & EFI_RESERVE_ISA_IO_ALIAS) != 0) {\r
IsaEnable = TRUE;\r
}\r
- if (PciPolicy & EFI_RESERVE_VGA_IO_ALIAS) {\r
+ if ((PciPolicy & EFI_RESERVE_VGA_IO_ALIAS) != 0) {\r
VGAEnable = TRUE;\r
}\r
}\r
Aperture = 0;\r
\r
if (Bridge == NULL) {\r
- return EFI_SUCCESS;\r
+ return ;\r
}\r
\r
CurrentLink = Bridge->ChildList.ForwardLink;\r
// If both of them are enabled, then the IO resource would\r
// become too limited to meet the requirement of most of devices.\r
//\r
-\r
if (IsaEnable || VGAEnable) {\r
if (!IS_PCI_BRIDGE (&(Node->PciDev->Pci)) && !IS_CARDBUS_BRIDGE (&(Node->PciDev->Pci))) {\r
//\r
if (IsaEnable) {\r
SkipIsaAliasAperture (\r
&Aperture,\r
- Node->Length \r
+ Node->Length\r
);\r
Offset = Aperture & (Node->Alignment);\r
if (Offset != 0) {\r
Bridge->Alignment = Node->Alignment;\r
}\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
This function is used to calculate the resource aperture\r
for a given bridge device.\r
\r
- @param Bridge Give bridge device.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ @param Bridge PCI resouce node for given bridge device.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
CalculateResourceAperture (\r
- IN PCI_RESOURCE_NODE *Bridge\r
+ IN PCI_RESOURCE_NODE *Bridge\r
)\r
{\r
UINT64 Aperture;\r
Aperture = 0;\r
\r
if (Bridge == NULL) {\r
- return EFI_SUCCESS;\r
+ return ;\r
}\r
\r
if (Bridge->ResType == PciBarTypeIo16) {\r
- return CalculateApertureIo16 (Bridge);\r
+\r
+ CalculateApertureIo16 (Bridge);\r
+ return ;\r
}\r
\r
CurrentLink = Bridge->ChildList.ForwardLink;\r
//\r
// Apply padding resource if available\r
//\r
- \r
+\r
Offset = Aperture & (Node->Alignment);\r
\r
if (Offset != 0) {\r
//\r
// Consider the aperture alignment\r
//\r
- \r
+\r
CurrentLink = CurrentLink->ForwardLink;\r
}\r
\r
if (Bridge->Length < Aperture) {\r
Bridge->Length = Aperture;\r
}\r
- \r
+\r
//\r
// At last, adjust the bridge's alignment to the first child's alignment\r
// if the bridge has at least one child\r
Bridge->Alignment = Node->Alignment;\r
}\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
Get IO/Memory resource infor for given PCI device.\r
- \r
+\r
@param PciDev Pci device instance.\r
@param IoNode Resource info node for IO .\r
@param Mem32Node Resource info node for 32-bit memory.\r
- @param PMem32Node Resource info node for 32-bit PMemory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
@param Mem64Node Resource info node for 64-bit memory.\r
- @param PMem64Node Resource info node for 64-bit PMemory.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
GetResourceFromDevice (\r
- PCI_IO_DEVICE *PciDev,\r
- PCI_RESOURCE_NODE *IoNode,\r
- PCI_RESOURCE_NODE *Mem32Node,\r
- PCI_RESOURCE_NODE *PMem32Node,\r
- PCI_RESOURCE_NODE *Mem64Node,\r
- PCI_RESOURCE_NODE *PMem64Node\r
+ IN PCI_IO_DEVICE *PciDev,\r
+ IN PCI_RESOURCE_NODE *IoNode,\r
+ IN PCI_RESOURCE_NODE *Mem32Node,\r
+ IN PCI_RESOURCE_NODE *PMem32Node,\r
+ IN PCI_RESOURCE_NODE *Mem64Node,\r
+ IN PCI_RESOURCE_NODE *PMem64Node\r
)\r
{\r
\r
if (!ResourceRequested) {\r
PciDev->Allocated = TRUE;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
@param Bar Bar index.\r
@param ResType Type of resource: IO/Memory.\r
@param ResUsage Resource usage.\r
+\r
+ @return PCI resource node created for given PCI device.\r
+ NULL means PCI resource node is not created.\r
+\r
**/\r
PCI_RESOURCE_NODE *\r
CreateResourceNode (\r
Node->Reserved = FALSE;\r
Node->ResourceUsage = ResUsage;\r
InitializeListHead (&Node->ChildList);\r
+\r
return Node;\r
}\r
\r
/**\r
- This routine is used to extract resource request from\r
+ This function is used to extract resource request from\r
device node list.\r
\r
@param Bridge Pci device instance.\r
@param IoNode Resource info node for IO.\r
@param Mem32Node Resource info node for 32-bit memory.\r
- @param PMem32Node Resource info node for 32-bit PMemory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
@param Mem64Node Resource info node for 64-bit memory.\r
- @param PMem64Node Resource info node for 64-bit PMemory.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
\r
- @retval EFI_SUCCESS Success.\r
**/\r
-EFI_STATUS\r
+VOID\r
CreateResourceMap (\r
IN PCI_IO_DEVICE *Bridge,\r
IN PCI_RESOURCE_NODE *IoNode,\r
// Note: For PPB, memory aperture is aligned with 1MB and IO aperture\r
// is aligned with 4KB\r
// This device is typically a bridge device like PPB and P2C\r
+ // Note: 0x1000 aligned\r
//\r
IoBridge = CreateResourceNode (\r
- Temp,\r
- 0,\r
- 0xFFF,\r
- PPB_IO_RANGE,\r
- PciBarTypeIo16,\r
- PciResUsageTypical\r
- ); //0x1000 aligned\r
- \r
+ Temp,\r
+ 0,\r
+ 0xFFF,\r
+ PPB_IO_RANGE,\r
+ PciBarTypeIo16,\r
+ PciResUsageTypical\r
+ );\r
+\r
Mem32Bridge = CreateResourceNode (\r
Temp,\r
0,\r
);\r
\r
PMem32Bridge = CreateResourceNode (\r
- Temp,\r
- 0,\r
- 0xFFFFF,\r
- PPB_PMEM32_RANGE,\r
- PciBarTypePMem32,\r
- PciResUsageTypical\r
- );\r
+ Temp,\r
+ 0,\r
+ 0xFFFFF,\r
+ PPB_PMEM32_RANGE,\r
+ PciBarTypePMem32,\r
+ PciResUsageTypical\r
+ );\r
\r
Mem64Bridge = CreateResourceNode (\r
Temp,\r
);\r
\r
PMem64Bridge = CreateResourceNode (\r
- Temp,\r
- 0,\r
- 0xFFFFF,\r
- PPB_PMEM64_RANGE,\r
- PciBarTypePMem64,\r
- PciResUsageTypical\r
- );\r
+ Temp,\r
+ 0,\r
+ 0xFFFFF,\r
+ PPB_PMEM64_RANGE,\r
+ PciBarTypePMem64,\r
+ PciResUsageTypical\r
+ );\r
\r
//\r
// Recursively create resouce map on this bridge\r
CalculateResourceAperture (Mem64Node);\r
CalculateResourceAperture (PMem64Node);\r
CalculateResourceAperture (IoNode);\r
-\r
- return EFI_SUCCESS;\r
-\r
}\r
\r
/**\r
@param PciDev Pci device instance.\r
@param IoNode Resource info node for IO.\r
@param Mem32Node Resource info node for 32-bit memory.\r
- @param PMem32Node Resource info node for 32-bit PMemory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
@param Mem64Node Resource info node for 64-bit memory.\r
- @param PMem64Node Resource info node for 64-bit PMemory.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
\r
- @retval EFI_SUCCESS Success.\r
**/\r
-EFI_STATUS\r
+VOID\r
ResourcePaddingPolicy (\r
- PCI_IO_DEVICE *PciDev,\r
- PCI_RESOURCE_NODE *IoNode,\r
- PCI_RESOURCE_NODE *Mem32Node,\r
- PCI_RESOURCE_NODE *PMem32Node,\r
- PCI_RESOURCE_NODE *Mem64Node,\r
- PCI_RESOURCE_NODE *PMem64Node\r
+ IN PCI_IO_DEVICE *PciDev,\r
+ IN PCI_RESOURCE_NODE *IoNode,\r
+ IN PCI_RESOURCE_NODE *Mem32Node,\r
+ IN PCI_RESOURCE_NODE *PMem32Node,\r
+ IN PCI_RESOURCE_NODE *Mem64Node,\r
+ IN PCI_RESOURCE_NODE *PMem64Node\r
)\r
{\r
//\r
PMem64Node\r
);\r
}\r
-\r
- return EFI_SUCCESS;\r
-\r
}\r
\r
/**\r
- This function is used to degrade resource if the upstream bridge \r
- doesn't support certain resource. Degradation path is \r
+ This function is used to degrade resource if the upstream bridge\r
+ doesn't support certain resource. Degradation path is\r
PMEM64 -> MEM64 -> MEM32\r
PMEM64 -> PMEM32 -> MEM32\r
IO32 -> IO16.\r
\r
@param Bridge Pci device instance.\r
@param Mem32Node Resource info node for 32-bit memory.\r
- @param PMem32Node Resource info node for 32-bit PMemory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
@param Mem64Node Resource info node for 64-bit memory.\r
- @param PMem64Node Resource info node for 64-bit PMemory.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
\r
- @retval EFI_SUCCESS Success.\r
**/\r
-EFI_STATUS\r
+VOID\r
DegradeResource (\r
IN PCI_IO_DEVICE *Bridge,\r
IN PCI_RESOURCE_NODE *Mem32Node,\r
//\r
// For RootBridge, PPB , P2C, go recursively to traverse all its children\r
// to find if this bridge and downstream has OptionRom.\r
- // \r
+ //\r
HasOprom = FALSE;\r
CurrentLink = Bridge->ChildList.ForwardLink;\r
while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
if (Temp->RomSize != 0) {\r
HasOprom = TRUE;\r
break;\r
- } \r
+ }\r
CurrentLink = CurrentLink->ForwardLink;\r
- } \r
+ }\r
\r
//\r
// If bridge doesn't support Prefetchable\r
//\r
// if no PMem32 request and no OptionRom request, still keep PMem64. Otherwise degrade to PMem32\r
//\r
- if ((PMem32Node != NULL && (PMem32Node->Length != 0 && Bridge->Parent != NULL)) || HasOprom) { \r
+ if ((PMem32Node != NULL && (PMem32Node->Length != 0 && Bridge->Parent != NULL)) || HasOprom) {\r
//\r
// Fixed the issue that there is no resource for 64-bit (above 4G)\r
//\r
FALSE\r
);\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
- Test whether bridge device support decode resource\r
- \r
+ Test whether bridge device support decode resource.\r
+\r
@param Bridge Bridge device instance.\r
@param Decode Decode type according to resource type.\r
- \r
- @return TRUE bridge device support decode resource.\r
- @return FALSE bridge device don't support decode resource.\r
- \r
+\r
+ @return TRUE The bridge device support decode resource.\r
+ @return FALSE The bridge device don't support decode resource.\r
+\r
**/\r
BOOLEAN\r
BridgeSupportResourceDecode (\r
IN UINT32 Decode\r
)\r
{\r
-\r
if (((Bridge->Decodes) & Decode) != 0) {\r
return TRUE;\r
}\r
}\r
\r
/**\r
- This function is used to program the resource allocated \r
- for each resource node.\r
-\r
- \r
- @param Base Base address of resource.\r
- @param Bridge Bridge device instance.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ This function is used to program the resource allocated\r
+ for each resource node under specified bridge.\r
+\r
+ @param Base Base address of resource to be progammed.\r
+ @param Bridge PCI resource node for the bridge device.\r
+\r
+ @retval EFI_SUCCESS Successfully to program all resouces\r
+ on given PCI bridge device.\r
+ @retval EFI_OUT_OF_RESOURCES Base is all one.\r
+\r
**/\r
EFI_STATUS\r
ProgramResource (\r
if (!IS_PCI_BRIDGE (&(Node->PciDev->Pci))) {\r
\r
if (IS_CARDBUS_BRIDGE (&(Node->PciDev->Pci))) {\r
+ //\r
+ // Program the PCI Card Bus device\r
+ //\r
ProgramP2C (Base, Node);\r
} else {\r
+ //\r
+ // Program the PCI device BAR\r
+ //\r
ProgramBar (Base, Node);\r
}\r
} else {\r
+ //\r
+ // Program the PCI devices under this bridge\r
+ //\r
Status = ProgramResource (Base + Node->Offset, Node);\r
-\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
}\r
\r
/**\r
- Program Bar register.\r
- \r
- @param Base Base address for resource.\r
+ Program Bar register for PCI device.\r
+\r
+ @param Base Base address for PCI device resource to be progammed.\r
@param Node Point to resoure node structure.\r
- \r
- @retval EFI_SUCCESS Success.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
ProgramBar (\r
IN UINT64 Base,\r
IN PCI_RESOURCE_NODE *Node\r
default:\r
break;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
- Program PPB apperture.\r
- \r
+ Program PCI-PCI bridge apperture.\r
+\r
@param Base Base address for resource.\r
@param Node Point to resoure node structure.\r
- \r
- @retval EFI_SUCCESS Success.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
ProgramPpbApperture (\r
IN UINT64 Base,\r
IN PCI_RESOURCE_NODE *Node\r
\r
Address = 0;\r
//\r
- // if no device south of this PPB, return anyway\r
+ // If no device resource of this PPB, return anyway\r
// Apperture is set default in the initialization code\r
//\r
if (Node->Length == 0 || Node->ResourceUsage == PciResUsagePadding) {\r
//\r
// For padding resource node, just ignore when programming\r
//\r
- return EFI_SUCCESS;\r
+ return ;\r
}\r
\r
PciIo = &(Node->PciDev->PciIo);\r
default:\r
break;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
- Program parent bridge for oprom.\r
- \r
+ Program parent bridge for Option Rom.\r
+\r
@param PciDevice Pci deivce instance.\r
- @param OptionRomBase Base address for oprom.\r
- @param Enable Enable/Disable.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ @param OptionRomBase Base address for Optiona Rom.\r
+ @param Enable Enable or disable PCI memory.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
ProgrameUpstreamBridgeForRom (\r
IN PCI_IO_DEVICE *PciDevice,\r
IN UINT32 OptionRomBase,\r
Node.Offset = 0;\r
\r
//\r
- // Program PPB to only open a single <= 16<MB apperture\r
+ // Program PPB to only open a single <= 16MB apperture\r
//\r
if (Enable) {\r
ProgramPpbApperture (OptionRomBase, &Node);\r
\r
Parent = Parent->Parent;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
Test whether resource exists for a bridge.\r
- \r
+\r
@param Bridge Point to resource node for a bridge.\r
- \r
- @return whether resource exists.\r
+\r
+ @retval TRUE There is resource on the given bridge.\r
+ @retval FALSE There isn't resource on the given bridge.\r
+\r
**/\r
BOOLEAN\r
ResourceRequestExisted (\r
- IN PCI_RESOURCE_NODE *Bridge\r
+ IN PCI_RESOURCE_NODE *Bridge\r
)\r
{\r
if (Bridge != NULL) {\r
\r
/**\r
Initialize resource pool structure.\r
- \r
- @param ResourcePool Point to resource pool structure.\r
+\r
+ @param ResourcePool Point to resource pool structure. This pool\r
+ is reset to all zero when returned.\r
@param ResourceType Type of resource.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
InitializeResourcePool (\r
- PCI_RESOURCE_NODE *ResourcePool,\r
- PCI_BAR_TYPE ResourceType\r
+ IN OUT PCI_RESOURCE_NODE *ResourcePool,\r
+ IN PCI_BAR_TYPE ResourceType\r
)\r
{\r
-\r
ZeroMem (ResourcePool, sizeof (PCI_RESOURCE_NODE));\r
ResourcePool->ResType = ResourceType;\r
ResourcePool->Signature = PCI_RESOURCE_SIGNATURE;\r
InitializeListHead (&ResourcePool->ChildList);\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
+\r
/**\r
Get all resource information for given Pci device.\r
- \r
+\r
@param PciDev Pci device instance.\r
@param IoBridge Io resource node.\r
@param Mem32Bridge 32-bit memory node.\r
@param PMem64Bridge 64-bit PMemory node.\r
@param IoPool Link list header for Io resource.\r
@param Mem32Pool Link list header for 32-bit memory.\r
- @param PMem32Pool Link list header for 32-bit Pmemory.\r
+ @param PMem32Pool Link list header for 32-bit Prefetchable memory.\r
@param Mem64Pool Link list header for 64-bit memory.\r
- @param PMem64Pool Link list header for 64-bit Pmemory.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ @param PMem64Pool Link list header for 64-bit Prefetchable memory.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
GetResourceMap (\r
- PCI_IO_DEVICE *PciDev,\r
- PCI_RESOURCE_NODE **IoBridge,\r
- PCI_RESOURCE_NODE **Mem32Bridge,\r
- PCI_RESOURCE_NODE **PMem32Bridge,\r
- PCI_RESOURCE_NODE **Mem64Bridge,\r
- PCI_RESOURCE_NODE **PMem64Bridge,\r
- PCI_RESOURCE_NODE *IoPool,\r
- PCI_RESOURCE_NODE *Mem32Pool,\r
- PCI_RESOURCE_NODE *PMem32Pool,\r
- PCI_RESOURCE_NODE *Mem64Pool,\r
- PCI_RESOURCE_NODE *PMem64Pool\r
+ IN PCI_IO_DEVICE *PciDev,\r
+ IN PCI_RESOURCE_NODE **IoBridge,\r
+ IN PCI_RESOURCE_NODE **Mem32Bridge,\r
+ IN PCI_RESOURCE_NODE **PMem32Bridge,\r
+ IN PCI_RESOURCE_NODE **Mem64Bridge,\r
+ IN PCI_RESOURCE_NODE **PMem64Bridge,\r
+ IN PCI_RESOURCE_NODE *IoPool,\r
+ IN PCI_RESOURCE_NODE *Mem32Pool,\r
+ IN PCI_RESOURCE_NODE *PMem32Pool,\r
+ IN PCI_RESOURCE_NODE *Mem64Pool,\r
+ IN PCI_RESOURCE_NODE *PMem64Pool\r
)\r
{\r
\r
\r
CurrentLink = CurrentLink->ForwardLink;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
Destory given resource tree.\r
- \r
- @param Bridge root node of resource tree.\r
- \r
- @retval EFI_SUCCESS Success.\r
+\r
+ @param Bridge PCI resource root node of resource tree.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
DestroyResourceTree (\r
IN PCI_RESOURCE_NODE *Bridge\r
)\r
CurrentLink = Bridge->ChildList.ForwardLink;\r
\r
Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
+ ASSERT (Temp);\r
\r
RemoveEntryList (CurrentLink);\r
\r
DestroyResourceTree (Temp);\r
}\r
\r
- gBS->FreePool (Temp);\r
+ FreePool (Temp);\r
}\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Record the reserved resource and insert to reserved list.\r
- \r
- @param Base Base address of reserved resourse.\r
- @param Length Length of reserved resource. \r
- @param ResType Resource type.\r
- @param Bridge Pci device instance.\r
-**/\r
-EFI_STATUS\r
-RecordReservedResource (\r
- IN UINT64 Base,\r
- IN UINT64 Length,\r
- IN PCI_BAR_TYPE ResType,\r
- IN PCI_IO_DEVICE *Bridge\r
- )\r
-{\r
- PCI_RESERVED_RESOURCE_LIST *ReservedNode;\r
-\r
- ReservedNode = AllocatePool (sizeof (PCI_RESERVED_RESOURCE_LIST));\r
- if (ReservedNode == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
-\r
- ReservedNode->Signature = RESERVED_RESOURCE_SIGNATURE;\r
- ReservedNode->Node.Base = Base;\r
- ReservedNode->Node.Length = Length;\r
- ReservedNode->Node.ResType = ResType;\r
-\r
- InsertTailList (&Bridge->ReservedResourceList, &(ReservedNode->Link));\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
Insert resource padding for P2C.\r
- \r
+\r
@param PciDev Pci device instance.\r
- @param IoNode Resource info node for IO. \r
+ @param IoNode Resource info node for IO.\r
@param Mem32Node Resource info node for 32-bit memory.\r
- @param PMem32Node Resource info node for 32-bit PMemory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
@param Mem64Node Resource info node for 64-bit memory.\r
- @param PMem64Node Resource info node for 64-bit PMemory.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
ResourcePaddingForCardBusBridge (\r
- PCI_IO_DEVICE *PciDev,\r
- PCI_RESOURCE_NODE *IoNode,\r
- PCI_RESOURCE_NODE *Mem32Node,\r
- PCI_RESOURCE_NODE *PMem32Node,\r
- PCI_RESOURCE_NODE *Mem64Node,\r
- PCI_RESOURCE_NODE *PMem64Node\r
+ IN PCI_IO_DEVICE *PciDev,\r
+ IN PCI_RESOURCE_NODE *IoNode,\r
+ IN PCI_RESOURCE_NODE *Mem32Node,\r
+ IN PCI_RESOURCE_NODE *PMem32Node,\r
+ IN PCI_RESOURCE_NODE *Mem64Node,\r
+ IN PCI_RESOURCE_NODE *PMem64Node\r
)\r
{\r
PCI_RESOURCE_NODE *Node;\r
// Bar 1 denodes memory range 0\r
//\r
Node = CreateResourceNode (\r
- PciDev,\r
- 0x2000000,\r
- 0x1ffffff,\r
- 1,\r
- PciBarTypeMem32,\r
- PciResUsagePadding\r
- );\r
+ PciDev,\r
+ 0x2000000,\r
+ 0x1ffffff,\r
+ 1,\r
+ PciBarTypeMem32,\r
+ PciResUsagePadding\r
+ );\r
\r
InsertResourceNode (\r
Mem32Node,\r
// Bar 2 denodes memory range1\r
//\r
Node = CreateResourceNode (\r
- PciDev,\r
- 0x2000000,\r
- 0x1ffffff,\r
- 2,\r
- PciBarTypePMem32,\r
- PciResUsagePadding\r
- );\r
+ PciDev,\r
+ 0x2000000,\r
+ 0x1ffffff,\r
+ 2,\r
+ PciBarTypePMem32,\r
+ PciResUsagePadding\r
+ );\r
\r
InsertResourceNode (\r
PMem32Node,\r
// Bar 3 denodes io range 0\r
//\r
Node = CreateResourceNode (\r
- PciDev,\r
- 0x100,\r
- 0xff,\r
- 3,\r
- PciBarTypeIo16,\r
- PciResUsagePadding\r
- );\r
+ PciDev,\r
+ 0x100,\r
+ 0xff,\r
+ 3,\r
+ PciBarTypeIo16,\r
+ PciResUsagePadding\r
+ );\r
\r
InsertResourceNode (\r
IoNode,\r
// Bar 4 denodes io range 0\r
//\r
Node = CreateResourceNode (\r
- PciDev,\r
- 0x100,\r
- 0xff,\r
- 4,\r
- PciBarTypeIo16,\r
- PciResUsagePadding\r
- );\r
+ PciDev,\r
+ 0x100,\r
+ 0xff,\r
+ 4,\r
+ PciBarTypeIo16,\r
+ PciResUsagePadding\r
+ );\r
\r
InsertResourceNode (\r
IoNode,\r
Node\r
);\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
- Program P2C register for given resource node\r
- \r
- @param Base Base address of P2C device\r
+ Program PCI Card device register for given resource node.\r
+\r
+ @param Base Base address of PCI Card device to be programmed.\r
@param Node Given resource node.\r
- \r
- @retval EFI_SUCCESS Success\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
ProgramP2C (\r
IN UINT64 Base,\r
IN PCI_RESOURCE_NODE *Node\r
\r
case P2C_BAR_0:\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- (Node->PciDev->PciBar[Node->Bar]).Offset,\r
- 1,\r
- &Address\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ (Node->PciDev->PciBar[Node->Bar]).Offset,\r
+ 1,\r
+ &Address\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
\r
case P2C_MEM_1:\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x1c,\r
- 1,\r
- &Address\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_MEMORY_BASE_0,\r
+ 1,\r
+ &Address\r
+ );\r
\r
TempAddress = Address + Node->Length - 1;\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x20,\r
- 1,\r
- &TempAddress\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_MEMORY_LIMIT_0,\r
+ 1,\r
+ &TempAddress\r
+ );\r
\r
if (Node->ResType == PciBarTypeMem32) {\r
-\r
//\r
// Set non-prefetchable bit\r
//\r
PciIoRead (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
-\r
- BridgeControl &= 0xfeff;\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
+\r
+ BridgeControl &= (UINT16) ~PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
\r
} else {\r
-\r
//\r
// Set pre-fetchable bit\r
//\r
PciIoRead (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
-\r
- BridgeControl |= 0x0100;\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
+\r
+ BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
}\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
\r
case P2C_MEM_2:\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x24,\r
- 1,\r
- &Address\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_MEMORY_BASE_1,\r
+ 1,\r
+ &Address\r
+ );\r
\r
TempAddress = Address + Node->Length - 1;\r
\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x28,\r
- 1,\r
- &TempAddress\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_MEMORY_LIMIT_1,\r
+ 1,\r
+ &TempAddress\r
+ );\r
\r
if (Node->ResType == PciBarTypeMem32) {\r
\r
// Set non-prefetchable bit\r
//\r
PciIoRead (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
-\r
- BridgeControl &= 0xfdff;\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
+\r
+ BridgeControl &= (UINT16) ~(PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE);\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
+\r
} else {\r
\r
//\r
// Set pre-fetchable bit\r
//\r
PciIoRead (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
-\r
- BridgeControl |= 0x0200;\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
+\r
+ BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE;\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
}\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
\r
case P2C_IO_1:\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x2c,\r
- 1,\r
- &Address\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_IO_BASE_0_LOWER,\r
+ 1,\r
+ &Address\r
+ );\r
+\r
TempAddress = Address + Node->Length - 1;\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x30,\r
- 1,\r
- &TempAddress\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_IO_LIMIT_0_LOWER,\r
+ 1,\r
+ &TempAddress\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
\r
case P2C_IO_2:\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x34,\r
- 1,\r
- &Address\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_IO_BASE_1_LOWER,\r
+ 1,\r
+ &Address\r
+ );\r
\r
TempAddress = Address + Node->Length - 1;\r
PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x38,\r
- 1,\r
- &TempAddress\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_IO_LIMIT_1_LOWER,\r
+ 1,\r
+ &TempAddress\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
default:\r
break;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
Create padding resource node.\r
- \r
+\r
@param PciDev Pci device instance.\r
- @param IoNode Resource info node for IO. \r
+ @param IoNode Resource info node for IO.\r
@param Mem32Node Resource info node for 32-bit memory.\r
- @param PMem32Node Resource info node for 32-bit PMemory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
@param Mem64Node Resource info node for 64-bit memory.\r
- @param PMem64Node Resource info node for 64-bit PMemory.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
\r
**/\r
-EFI_STATUS\r
+VOID\r
ApplyResourcePadding (\r
- PCI_IO_DEVICE *PciDev,\r
- PCI_RESOURCE_NODE *IoNode,\r
- PCI_RESOURCE_NODE *Mem32Node,\r
- PCI_RESOURCE_NODE *PMem32Node,\r
- PCI_RESOURCE_NODE *Mem64Node,\r
- PCI_RESOURCE_NODE *PMem64Node\r
+ IN PCI_IO_DEVICE *PciDev,\r
+ IN PCI_RESOURCE_NODE *IoNode,\r
+ IN PCI_RESOURCE_NODE *Mem32Node,\r
+ IN PCI_RESOURCE_NODE *PMem32Node,\r
+ IN PCI_RESOURCE_NODE *Mem64Node,\r
+ IN PCI_RESOURCE_NODE *PMem64Node\r
)\r
{\r
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
\r
Ptr++;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
- Get padding resource for PPB.\r
- Light PCI bus driver woundn't support hotplug root device\r
- So no need to pad resource for them.\r
+ Get padding resource for PCI-PCI bridge.\r
+\r
+ @param PciIoDevice PCI-PCI bridge device instance.\r
\r
- @param PciIoDevice Pci device instance.\r
+ @note Feature flag PcdPciBusHotplugDeviceSupport determines\r
+ whether need to pad resource for them.\r
**/\r
VOID\r
GetResourcePaddingPpb (\r
IN PCI_IO_DEVICE *PciIoDevice\r
)\r
{\r
- if (gPciHotPlugInit != NULL) {\r
+ if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
if (PciIoDevice->ResourcePaddingDescriptors == NULL) {\r
GetResourcePaddingForHpb (PciIoDevice);\r
}\r
/** @file\r
+ PCI resouces support functions declaration for PCI Bus module.\r
\r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _EFI_PCI_RESOURCE_SUPPORT_H_\r
#define _EFI_PCI_RESOURCE_SUPPORT_H_\r
\r
-#define RESERVED_RESOURCE_SIGNATURE SIGNATURE_32 ('r', 's', 'v', 'd')\r
-\r
-typedef struct {\r
- UINT64 Base;\r
- UINT64 Length;\r
- PCI_BAR_TYPE ResType;\r
-} PCI_RESERVED_RESOURCE_NODE;\r
-\r
-typedef struct {\r
- UINT32 Signature;\r
- LIST_ENTRY Link;\r
- PCI_RESERVED_RESOURCE_NODE Node;\r
-} PCI_RESERVED_RESOURCE_LIST;\r
-\r
-#define RESOURCED_LIST_FROM_NODE(a) \\r
- CR (a, PCI_RESERVED_RESOURCE_LIST, Node, RESERVED_RESOURCE_SIGNATURE)\r
-\r
-#define RESOURCED_LIST_FROM_LINK(a) \\r
- CR (a, PCI_RESERVED_RESOURCE_LIST, Link, RESERVED_RESOURCE_SIGNATURE)\r
-\r
typedef enum {\r
PciResUsageTypical = 0,\r
PciResUsagePadding,\r
CR (a, PCI_RESOURCE_NODE, Link, PCI_RESOURCE_SIGNATURE)\r
\r
/**\r
- The function is used to skip VGA range\r
- \r
- @param Start address including VGA range\r
- @param Length length of VGA range.\r
- \r
- @retval EFI_SUCCESS success.\r
+ The function is used to skip VGA range.\r
+\r
+ @param Start Returned start address including VGA range.\r
+ @param Length The length of VGA range.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
SkipVGAAperture (\r
OUT UINT64 *Start,\r
IN UINT64 Length\r
\r
/**\r
This function is used to skip ISA aliasing aperture.\r
- \r
- @param Start address including ISA aliasing aperture.\r
- @param Length length of ISA aliasing aperture.\r
- \r
- @retval EFI_SUCCESS success.\r
+\r
+ @param Start Returned start address including ISA aliasing aperture.\r
+ @param Length The length of ISA aliasing aperture.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
SkipIsaAliasAperture (\r
OUT UINT64 *Start,\r
IN UINT64 Length\r
\r
@param Bridge PCI resource node for bridge.\r
@param ResNode Resource node want to be inserted.\r
- \r
- @retval EFI_SUCCESS Success.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
InsertResourceNode (\r
- PCI_RESOURCE_NODE *Bridge,\r
- PCI_RESOURCE_NODE *ResNode\r
+ IN PCI_RESOURCE_NODE *Bridge,\r
+ IN PCI_RESOURCE_NODE *ResNode\r
);\r
\r
/**\r
+ This routine is used to merge two different resource trees in need of\r
+ resoure degradation.\r
\r
-Routine Description:\r
-\r
- This routine is used to merge two different resource tree in need of\r
- resoure degradation. For example, if a upstream PPB doesn't support,\r
+ For example, if an upstream PPB doesn't support,\r
prefetchable memory decoding, the PCI bus driver will choose to call this function\r
to merge prefectchable memory resource list into normal memory list.\r
\r
If the TypeMerge is TRUE, Res resource type is changed to the type of destination resource\r
type.\r
+ If Dst is NULL or Res is NULL, ASSERT ().\r
\r
@param Dst Point to destination resource tree.\r
@param Res Point to source resource tree.\r
- @param TypeMerge If the TypeMerge is TRUE, Res resource type is changed to the type of \r
+ @param TypeMerge If the TypeMerge is TRUE, Res resource type is changed to the type of\r
destination resource type.\r
- \r
- \r
- @retval EFI_SUCCESS Success\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
MergeResourceTree (\r
- PCI_RESOURCE_NODE *Dst,\r
- PCI_RESOURCE_NODE *Res,\r
- BOOLEAN TypeMerge\r
+ IN PCI_RESOURCE_NODE *Dst,\r
+ IN PCI_RESOURCE_NODE *Res,\r
+ IN BOOLEAN TypeMerge\r
);\r
\r
/**\r
This function is used to calculate the IO16 aperture\r
for a bridge.\r
\r
- @param Bridge PCI resource node for bridge.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ @param Bridge PCI resource node for bridge.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
CalculateApertureIo16 (\r
- IN PCI_RESOURCE_NODE *Bridge\r
+ IN PCI_RESOURCE_NODE *Bridge\r
);\r
\r
/**\r
This function is used to calculate the resource aperture\r
for a given bridge device.\r
\r
- @param Bridge Give bridge device.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ @param Bridge PCI resouce node for given bridge device.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
CalculateResourceAperture (\r
- IN PCI_RESOURCE_NODE *Bridge\r
+ IN PCI_RESOURCE_NODE *Bridge\r
);\r
\r
/**\r
Get IO/Memory resource infor for given PCI device.\r
- \r
+\r
@param PciDev Pci device instance.\r
@param IoNode Resource info node for IO .\r
@param Mem32Node Resource info node for 32-bit memory.\r
- @param PMem32Node Resource info node for 32-bit PMemory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
@param Mem64Node Resource info node for 64-bit memory.\r
- @param PMem64Node Resource info node for 64-bit PMemory.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
GetResourceFromDevice (\r
- PCI_IO_DEVICE *PciDev,\r
- PCI_RESOURCE_NODE *IoNode,\r
- PCI_RESOURCE_NODE *Mem32Node,\r
- PCI_RESOURCE_NODE *PMem32Node,\r
- PCI_RESOURCE_NODE *Mem64Node,\r
- PCI_RESOURCE_NODE *PMem64Node\r
+ IN PCI_IO_DEVICE *PciDev,\r
+ IN PCI_RESOURCE_NODE *IoNode,\r
+ IN PCI_RESOURCE_NODE *Mem32Node,\r
+ IN PCI_RESOURCE_NODE *PMem32Node,\r
+ IN PCI_RESOURCE_NODE *Mem64Node,\r
+ IN PCI_RESOURCE_NODE *PMem64Node\r
);\r
\r
/**\r
@param Bar Bar index.\r
@param ResType Type of resource: IO/Memory.\r
@param ResUsage Resource usage.\r
+\r
+ @return PCI resource node created for given PCI device.\r
+ NULL means PCI resource node is not created.\r
+\r
**/\r
PCI_RESOURCE_NODE *\r
CreateResourceNode (\r
);\r
\r
/**\r
- This routine is used to extract resource request from\r
+ This function is used to extract resource request from\r
device node list.\r
\r
@param Bridge Pci device instance.\r
@param IoNode Resource info node for IO.\r
@param Mem32Node Resource info node for 32-bit memory.\r
- @param PMem32Node Resource info node for 32-bit PMemory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
@param Mem64Node Resource info node for 64-bit memory.\r
- @param PMem64Node Resource info node for 64-bit PMemory.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
\r
- @retval EFI_SUCCESS Success.\r
**/\r
-EFI_STATUS\r
+VOID\r
CreateResourceMap (\r
IN PCI_IO_DEVICE *Bridge,\r
IN PCI_RESOURCE_NODE *IoNode,\r
This function is used to do the resource padding for a specific platform.\r
\r
@param PciDev Pci device instance.\r
- @param IoNode Resource info node for IO. \r
+ @param IoNode Resource info node for IO.\r
@param Mem32Node Resource info node for 32-bit memory.\r
- @param PMem32Node Resource info node for 32-bit PMemory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
@param Mem64Node Resource info node for 64-bit memory.\r
- @param PMem64Node Resource info node for 64-bit PMemory.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
\r
- @retval EFI_SUCCESS Success.\r
**/\r
-EFI_STATUS\r
+VOID\r
ResourcePaddingPolicy (\r
- PCI_IO_DEVICE *PciDev,\r
- PCI_RESOURCE_NODE *IoNode,\r
- PCI_RESOURCE_NODE *Mem32Node,\r
- PCI_RESOURCE_NODE *PMem32Node,\r
- PCI_RESOURCE_NODE *Mem64Node,\r
- PCI_RESOURCE_NODE *PMem64Node\r
+ IN PCI_IO_DEVICE *PciDev,\r
+ IN PCI_RESOURCE_NODE *IoNode,\r
+ IN PCI_RESOURCE_NODE *Mem32Node,\r
+ IN PCI_RESOURCE_NODE *PMem32Node,\r
+ IN PCI_RESOURCE_NODE *Mem64Node,\r
+ IN PCI_RESOURCE_NODE *PMem64Node\r
);\r
\r
/**\r
- This function is used to degrade resource if the upstream bridge \r
- doesn't support certain resource. Degradation path is \r
+ This function is used to degrade resource if the upstream bridge\r
+ doesn't support certain resource. Degradation path is\r
PMEM64 -> MEM64 -> MEM32\r
PMEM64 -> PMEM32 -> MEM32\r
- IO32 -> IO16\r
+ IO32 -> IO16.\r
\r
@param Bridge Pci device instance.\r
@param Mem32Node Resource info node for 32-bit memory.\r
- @param PMem32Node Resource info node for 32-bit PMemory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
@param Mem64Node Resource info node for 64-bit memory.\r
- @param PMem64Node Resource info node for 64-bit PMemory.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
\r
- @retval EFI_SUCCESS Success.\r
**/\r
-EFI_STATUS\r
+VOID\r
DegradeResource (\r
IN PCI_IO_DEVICE *Bridge,\r
IN PCI_RESOURCE_NODE *Mem32Node,\r
\r
/**\r
Test whether bridge device support decode resource.\r
- \r
+\r
@param Bridge Bridge device instance.\r
@param Decode Decode type according to resource type.\r
- \r
- @return whether bridge device support decode resource.\r
- \r
+\r
+ @return TRUE The bridge device support decode resource.\r
+ @return FALSE The bridge device don't support decode resource.\r
+\r
**/\r
BOOLEAN\r
BridgeSupportResourceDecode (\r
);\r
\r
/**\r
- This function is used to program the resource allocated \r
- for each resource node.\r
-\r
- \r
- @param Base Base address of resource.\r
- @param Bridge Bridge device instance.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ This function is used to program the resource allocated\r
+ for each resource node under specified bridge.\r
+\r
+ @param Base Base address of resource to be progammed.\r
+ @param Bridge PCI resource node for the bridge device.\r
+\r
+ @retval EFI_SUCCESS Successfully to program all resouces\r
+ on given PCI bridge device.\r
+ @retval EFI_OUT_OF_RESOURCES Base is all one.\r
+\r
**/\r
EFI_STATUS\r
ProgramResource (\r
);\r
\r
/**\r
- Program Bar register.\r
- \r
- @param Base Base address for resource.\r
+ Program Bar register for PCI device.\r
+\r
+ @param Base Base address for PCI device resource to be progammed.\r
@param Node Point to resoure node structure.\r
- \r
- @retval EFI_SUCCESS Success.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
ProgramBar (\r
IN UINT64 Base,\r
IN PCI_RESOURCE_NODE *Node\r
);\r
\r
/**\r
- Program PPB apperture.\r
- \r
+ Program PCI-PCI bridge apperture.\r
+\r
@param Base Base address for resource.\r
@param Node Point to resoure node structure.\r
- \r
- @retval EFI_SUCCESS Success.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
ProgramPpbApperture (\r
IN UINT64 Base,\r
IN PCI_RESOURCE_NODE *Node\r
);\r
\r
/**\r
- Program parent bridge for oprom.\r
- \r
+ Program parent bridge for Option Rom.\r
+\r
@param PciDevice Pci deivce instance.\r
- @param OptionRomBase Base address for oprom.\r
- @param Enable Enable/Disable.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ @param OptionRomBase Base address for Optiona Rom.\r
+ @param Enable Enable or disable PCI memory.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
ProgrameUpstreamBridgeForRom (\r
IN PCI_IO_DEVICE *PciDevice,\r
IN UINT32 OptionRomBase,\r
\r
/**\r
Test whether resource exists for a bridge.\r
- \r
+\r
@param Bridge Point to resource node for a bridge.\r
- \r
- @return whether resource exists.\r
+\r
+ @retval TRUE There is resource on the given bridge.\r
+ @retval FALSE There isn't resource on the given bridge.\r
+\r
**/\r
BOOLEAN\r
ResourceRequestExisted (\r
- IN PCI_RESOURCE_NODE *Bridge\r
+ IN PCI_RESOURCE_NODE *Bridge\r
);\r
\r
/**\r
Initialize resource pool structure.\r
- \r
- @param ResourcePool Point to resource pool structure.\r
+\r
+ @param ResourcePool Point to resource pool structure. This pool\r
+ is reset to all zero when returned.\r
@param ResourceType Type of resource.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
InitializeResourcePool (\r
- PCI_RESOURCE_NODE *ResourcePool,\r
- PCI_BAR_TYPE ResourceType\r
+ IN OUT PCI_RESOURCE_NODE *ResourcePool,\r
+ IN PCI_BAR_TYPE ResourceType\r
);\r
\r
/**\r
Get all resource information for given Pci device.\r
- \r
+\r
@param PciDev Pci device instance.\r
@param IoBridge Io resource node.\r
@param Mem32Bridge 32-bit memory node.\r
@param PMem64Bridge 64-bit PMemory node.\r
@param IoPool Link list header for Io resource.\r
@param Mem32Pool Link list header for 32-bit memory.\r
- @param PMem32Pool Link list header for 32-bit Pmemory.\r
+ @param PMem32Pool Link list header for 32-bit Prefetchable memory.\r
@param Mem64Pool Link list header for 64-bit memory.\r
- @param PMem64Pool Link list header for 64-bit Pmemory.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ @param PMem64Pool Link list header for 64-bit Prefetchable memory.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
GetResourceMap (\r
- PCI_IO_DEVICE *PciDev,\r
- PCI_RESOURCE_NODE **IoBridge,\r
- PCI_RESOURCE_NODE **Mem32Bridge,\r
- PCI_RESOURCE_NODE **PMem32Bridge,\r
- PCI_RESOURCE_NODE **Mem64Bridge,\r
- PCI_RESOURCE_NODE **PMem64Bridge,\r
- PCI_RESOURCE_NODE *IoPool,\r
- PCI_RESOURCE_NODE *Mem32Pool,\r
- PCI_RESOURCE_NODE *PMem32Pool,\r
- PCI_RESOURCE_NODE *Mem64Pool,\r
- PCI_RESOURCE_NODE *PMem64Pool\r
+ IN PCI_IO_DEVICE *PciDev,\r
+ IN PCI_RESOURCE_NODE **IoBridge,\r
+ IN PCI_RESOURCE_NODE **Mem32Bridge,\r
+ IN PCI_RESOURCE_NODE **PMem32Bridge,\r
+ IN PCI_RESOURCE_NODE **Mem64Bridge,\r
+ IN PCI_RESOURCE_NODE **PMem64Bridge,\r
+ IN PCI_RESOURCE_NODE *IoPool,\r
+ IN PCI_RESOURCE_NODE *Mem32Pool,\r
+ IN PCI_RESOURCE_NODE *PMem32Pool,\r
+ IN PCI_RESOURCE_NODE *Mem64Pool,\r
+ IN PCI_RESOURCE_NODE *PMem64Pool\r
);\r
\r
/**\r
Destory given resource tree.\r
- \r
- @param Bridge root node of resource tree.\r
- \r
- @retval EFI_SUCCESS Success.\r
+\r
+ @param Bridge PCI resource root node of resource tree.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
DestroyResourceTree (\r
IN PCI_RESOURCE_NODE *Bridge\r
);\r
\r
-/**\r
- Record the reserved resource and insert to reserved list.\r
- \r
- @param Base Base address of reserved resourse.\r
- @param Length Length of reserved resource.\r
- @param ResType Resource type.\r
- @param Bridge Pci device instance.\r
-**/\r
-EFI_STATUS\r
-RecordReservedResource (\r
- IN UINT64 Base,\r
- IN UINT64 Length,\r
- IN PCI_BAR_TYPE ResType,\r
- IN PCI_IO_DEVICE *Bridge\r
- );\r
-\r
/**\r
Insert resource padding for P2C.\r
- \r
+\r
@param PciDev Pci device instance.\r
- @param IoNode Resource info node for IO. \r
+ @param IoNode Resource info node for IO.\r
@param Mem32Node Resource info node for 32-bit memory.\r
- @param PMem32Node Resource info node for 32-bit PMemory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
@param Mem64Node Resource info node for 64-bit memory.\r
- @param PMem64Node Resource info node for 64-bit PMemory.\r
- \r
- @retval EFI_SUCCESS Success.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
ResourcePaddingForCardBusBridge (\r
- PCI_IO_DEVICE *PciDev,\r
- PCI_RESOURCE_NODE *IoNode,\r
- PCI_RESOURCE_NODE *Mem32Node,\r
- PCI_RESOURCE_NODE *PMem32Node,\r
- PCI_RESOURCE_NODE *Mem64Node,\r
- PCI_RESOURCE_NODE *PMem64Node\r
+ IN PCI_IO_DEVICE *PciDev,\r
+ IN PCI_RESOURCE_NODE *IoNode,\r
+ IN PCI_RESOURCE_NODE *Mem32Node,\r
+ IN PCI_RESOURCE_NODE *PMem32Node,\r
+ IN PCI_RESOURCE_NODE *Mem64Node,\r
+ IN PCI_RESOURCE_NODE *PMem64Node\r
);\r
\r
/**\r
- Program P2C register for given resource node.\r
- \r
- @param Base Base address of P2C device.\r
+ Program PCI Card device register for given resource node.\r
+\r
+ @param Base Base address of PCI Card device to be programmed.\r
@param Node Given resource node.\r
- \r
- @retval EFI_SUCCESS Success.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
ProgramP2C (\r
IN UINT64 Base,\r
IN PCI_RESOURCE_NODE *Node\r
\r
/**\r
Create padding resource node.\r
- \r
+\r
@param PciDev Pci device instance.\r
- @param IoNode Resource info node for IO. \r
+ @param IoNode Resource info node for IO.\r
@param Mem32Node Resource info node for 32-bit memory.\r
- @param PMem32Node Resource info node for 32-bit PMemory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
@param Mem64Node Resource info node for 64-bit memory.\r
- @param PMem64Node Resource info node for 64-bit PMemory.\r
- \r
- @retval EFI_SUCCESS Success\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
\r
**/\r
-EFI_STATUS\r
+VOID\r
ApplyResourcePadding (\r
- PCI_IO_DEVICE *PciDev,\r
- PCI_RESOURCE_NODE *IoNode,\r
- PCI_RESOURCE_NODE *Mem32Node,\r
- PCI_RESOURCE_NODE *PMem32Node,\r
- PCI_RESOURCE_NODE *Mem64Node,\r
- PCI_RESOURCE_NODE *PMem64Node\r
+ IN PCI_IO_DEVICE *PciDev,\r
+ IN PCI_RESOURCE_NODE *IoNode,\r
+ IN PCI_RESOURCE_NODE *Mem32Node,\r
+ IN PCI_RESOURCE_NODE *PMem32Node,\r
+ IN PCI_RESOURCE_NODE *Mem64Node,\r
+ IN PCI_RESOURCE_NODE *PMem64Node\r
);\r
\r
/**\r
- Get padding resource for PPB\r
- Light PCI bus driver woundn't support hotplug root device\r
- So no need to pad resource for them.\r
+ Get padding resource for PCI-PCI bridge.\r
+\r
+ @param PciIoDevice PCI-PCI bridge device instance.\r
\r
- @param PciIoDevice Pci device instance.\r
+ @note Feature flag PcdPciBusHotplugDeviceSupport determines\r
+ whether need to pad resource for them.\r
**/\r
VOID\r
GetResourcePaddingPpb (\r
IN PCI_IO_DEVICE *PciIoDevice\r
);\r
\r
-/**\r
- Reset and all bus number from specific bridge.\r
- \r
- @param Bridge Parent specific bridge.\r
- @param StartBusNumber start bus number.\r
-**/\r
-EFI_STATUS\r
-ResetAllPpbBusNumber (\r
- IN PCI_IO_DEVICE *Bridge,\r
- IN UINT8 StartBusNumber\r
- );\r
-\r
#endif\r
/** @file\r
- Option Rom Support for PCI Bus Driver\r
+ Set up ROM Table for PCI Bus module.\r
\r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "PciBus.h"\r
-#include "PciRomTable.h"\r
\r
+//\r
+// PCI ROM image information\r
+//\r
typedef struct {\r
EFI_HANDLE ImageHandle;\r
UINTN Seg;\r
\r
/**\r
Add the Rom Image to internal database for later PCI light enumeration.\r
- \r
+\r
@param ImageHandle Option Rom image handle.\r
@param Seg Segment of PCI space.\r
@param Bus Bus NO of PCI space.\r
@param Func Func NO of PCI space.\r
@param RomAddress Base address of OptionRom.\r
@param RomLength Length of rom image.\r
+\r
**/\r
VOID\r
PciRomAddImageMapping (\r
- IN EFI_HANDLE ImageHandle,\r
- IN UINTN Seg,\r
- IN UINT8 Bus,\r
- IN UINT8 Dev,\r
- IN UINT8 Func,\r
- IN UINT64 RomAddress,\r
- IN UINT64 RomLength\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN UINTN Seg,\r
+ IN UINT8 Bus,\r
+ IN UINT8 Dev,\r
+ IN UINT8 Func,\r
+ IN UINT64 RomAddress,\r
+ IN UINT64 RomLength\r
)\r
{\r
EFI_PCI_ROM_IMAGE_MAPPING *TempMapping;\r
\r
/**\r
Get Option rom driver's mapping for PCI device.\r
- \r
+\r
@param PciIoDevice Device instance.\r
\r
@retval TRUE Found Image mapping.\r
- @retval FALSE\r
+ @retval FALSE Cannot found image mapping.\r
\r
**/\r
BOOLEAN\r
PciRomGetImageMapping (\r
- PCI_IO_DEVICE *PciIoDevice\r
+ IN PCI_IO_DEVICE *PciIoDevice\r
)\r
{\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
/** @file\r
- Option Rom Support for PCI Bus Driver\r
+ Set up ROM Table for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2009, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
\r
/**\r
Add the Rom Image to internal database for later PCI light enumeration.\r
- \r
+\r
@param ImageHandle Option Rom image handle.\r
@param Seg Segment of PCI space.\r
@param Bus Bus NO of PCI space.\r
@param Func Func NO of PCI space.\r
@param RomAddress Base address of OptionRom.\r
@param RomLength Length of rom image.\r
+\r
**/\r
VOID\r
PciRomAddImageMapping (\r
- IN EFI_HANDLE ImageHandle,\r
- IN UINTN Seg,\r
- IN UINT8 Bus,\r
- IN UINT8 Dev,\r
- IN UINT8 Func,\r
- IN UINT64 RomAddress,\r
- IN UINT64 RomLength\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN UINTN Seg,\r
+ IN UINT8 Bus,\r
+ IN UINT8 Dev,\r
+ IN UINT8 Func,\r
+ IN UINT64 RomAddress,\r
+ IN UINT64 RomLength\r
);\r
\r
/**\r
Get Option rom driver's mapping for PCI device.\r
- \r
+\r
@param PciIoDevice Device instance.\r
\r
@retval TRUE Found Image mapping.\r
- @retval FALSE\r
+ @retval FALSE Cannot found image mapping.\r
\r
**/\r
BOOLEAN\r
PciRomGetImageMapping (\r
- PCI_IO_DEVICE *PciIoDevice\r
+ IN PCI_IO_DEVICE *PciIoDevice\r
);\r
\r
#endif\r
/** @file\r
- PCI Incompatible device support Libary. Platform can implement an \r
+ PCI Incompatible device support Libary. Platform can implement an\r
instance to support the incompatible PCI devices.\r
\r
-Copyright (c) 2006 - 2009, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
} EFI_PCI_RESOUCE_DESCRIPTOR;\r
\r
/**\r
- Checks the incompatible device list for ACPI resource update and return\r
+ Check the incompatible device list for ACPI resource update and return\r
the configuration.\r
\r
This function searches the incompatible device list according to request\r
information. If the PCI device belongs to the devices list, corresponding\r
configuration informtion will be returned, in the meantime return EFI_SUCCESS.\r
\r
- @param PciDeviceInfo A pointer to PCI device information.\r
- @param Configuration Returned information.\r
+ @param PciDeviceInfo A pointer to PCI device information.\r
+ @param Configuration Returned information.\r
+\r
+ @retval EFI_SUCCESS If check incompatible device successfully.\r
+ @retval EFI_ABORTED No any resource type.\r
+ @retval EFI_OUT_OF_RESOURCES No memory available.\r
+ @retval EFI_UNSUPPORTED Invalid Tag encounted.\r
\r
- @retval EFI_SUCCESS The incompatible device is supported.\r
- @retval EFI_UNSUPPORTED The incompatible device is not supported.\r
**/\r
-RETURN_STATUS\r
+EFI_STATUS\r
EFIAPI\r
PciResourceUpdateCheck (\r
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
);\r
\r
/**\r
- Checks the incompatible device list and return configuration register mask values.\r
+ Check the incompatible device list and return configuraton register mask values.\r
\r
This function searches the incompatible device list according to request\r
information. If the PCI device belongs to the devices list, corresponding\r
@param Offset The address within the PCI configuration space.\r
@param Configuration Returned information.\r
\r
- @retval EFI_SUCCESS The incompatible device is supported.\r
- @retval EFI_UNSUPPORTED The incompatible device is not supported.\r
+ @retval EFI_SUCCESS If check incompatible device successfully.\r
+ @retval EFI_UNSUPPORTED Failed to check incompatibility device.\r
+\r
**/\r
-RETURN_STATUS\r
+EFI_STATUS\r
EFIAPI\r
PciRegisterUpdateCheck (\r
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
);\r
\r
/**\r
- Checks the incompatible device list for access width incompatibility and\r
+ Check the incompatible device list for access width incompatibility and\r
return the configuration\r
\r
This function searches the incompatible device list for access width\r
@param AccessWidth Access width needs to check incompatibility.\r
@param Configuration Returned information.\r
\r
- @retval EFI_SUCCESS The incompatible device is supported.\r
- @retval EFI_UNSUPPORTED The incompatible device is not supported.\r
+ @retval EFI_SUCCESS If check incompatible device successfully.\r
+ @retval EFI_UNSUPPORTED Failed to check incompatibility device.\r
+\r
**/\r
-RETURN_STATUS\r
+EFI_STATUS\r
EFIAPI\r
PciRegisterAccessCheck (\r
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
/** @file\r
- The incompatible PCI device list\r
+ The incompatible PCI device list template.\r
\r
-Copyright (c) 2006 - 2007, Intel Corporation \r
+Copyright (c) 2006 - 2009, Intel Corporation \r
All rights reserved. This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution. The full text of the license may be found at \r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/DebugLib.h>\r
\r
-#include <IndustryStandard/Pci22.h>\r
+#include <IndustryStandard/Pci.h>\r
#include <IndustryStandard/Acpi.h>\r
\r
\r
EFI_PCI_REGISTER_VALUE_DATA PciRegisterValueData;\r
} EFI_PCI_REGISTER_VALUE_DESCRIPTOR;\r
\r
-\r
//\r
// the incompatible PCI devices list for ACPI resource\r
//\r
-GLOBAL_REMOVE_IF_UNREFERENCED UINT64 IncompatiblePciDeviceListForResource[] = {\r
+GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gIncompatiblePciDeviceListForResource[] = {\r
//\r
// DEVICE_INF_TAG,\r
// PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),\r
// ResType, GFlag , SFlag, Granularity, RangeMin,\r
// RangeMax, Offset, AddrLen\r
//\r
+\r
+ //\r
+ // Sample Device 1\r
+ //\r
+ //DEVICE_INF_TAG,\r
+ //PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
+ //DEVICE_RES_TAG,\r
+ //PCI_BAR_TYPE_IO,\r
+ //PCI_ACPI_UNUSED,\r
+ //PCI_ACPI_UNUSED,\r
+ //PCI_ACPI_UNUSED,\r
+ //PCI_ACPI_UNUSED,\r
+ //PCI_BAR_EVEN_ALIGN,\r
+ //PCI_BAR_ALL,\r
+ //PCI_BAR_NOCHANGE,\r
+\r
//\r
- // Device Adaptec 9004\r
- //\r
- DEVICE_INF_TAG,\r
- PCI_DEVICE_ID(0x9004, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
- DEVICE_RES_TAG,\r
- PCI_BAR_TYPE_IO,\r
- PCI_ACPI_UNUSED,\r
- PCI_ACPI_UNUSED,\r
- PCI_ACPI_UNUSED,\r
- PCI_ACPI_UNUSED,\r
- PCI_BAR_EVEN_ALIGN,\r
- PCI_BAR_ALL,\r
- PCI_BAR_NOCHANGE,\r
- //\r
- // Device Adaptec 9005\r
- //\r
- DEVICE_INF_TAG,\r
- PCI_DEVICE_ID(0x9005, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
- DEVICE_RES_TAG,\r
- PCI_BAR_TYPE_IO,\r
- PCI_ACPI_UNUSED,\r
- PCI_ACPI_UNUSED,\r
- PCI_ACPI_UNUSED,\r
- PCI_ACPI_UNUSED,\r
- PCI_BAR_EVEN_ALIGN,\r
- PCI_BAR_ALL,\r
- PCI_BAR_NOCHANGE,\r
- //\r
- // Device QLogic 1007\r
- //\r
- DEVICE_INF_TAG,\r
- PCI_DEVICE_ID(0x1077, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
- DEVICE_RES_TAG,\r
- PCI_BAR_TYPE_IO,\r
- PCI_ACPI_UNUSED,\r
- PCI_ACPI_UNUSED,\r
- PCI_ACPI_UNUSED,\r
- PCI_ACPI_UNUSED,\r
- PCI_BAR_EVEN_ALIGN,\r
- PCI_BAR_ALL,\r
- PCI_BAR_NOCHANGE,\r
- //\r
- // Device Agilent 103C\r
- //\r
- DEVICE_INF_TAG,\r
- PCI_DEVICE_ID(0x103C, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
- DEVICE_RES_TAG,\r
- PCI_BAR_TYPE_IO,\r
- PCI_ACPI_UNUSED,\r
- PCI_ACPI_UNUSED,\r
- PCI_ACPI_UNUSED,\r
- PCI_ACPI_UNUSED,\r
- PCI_BAR_EVEN_ALIGN,\r
- PCI_BAR_ALL,\r
- PCI_BAR_NOCHANGE,\r
- //\r
- // Device Agilent 15BC\r
- //\r
- DEVICE_INF_TAG,\r
- PCI_DEVICE_ID(0x15BC, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
- DEVICE_RES_TAG,\r
- PCI_BAR_TYPE_IO,\r
- PCI_ACPI_UNUSED,\r
- PCI_ACPI_UNUSED,\r
- PCI_ACPI_UNUSED,\r
- PCI_ACPI_UNUSED,\r
- PCI_BAR_EVEN_ALIGN,\r
- PCI_BAR_ALL,\r
- PCI_BAR_NOCHANGE,\r
+ // Sample Device 2\r
+ //\r
+ //DEVICE_INF_TAG,\r
+ //PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
+ //DEVICE_RES_TAG,\r
+ //PCI_BAR_TYPE_IO,\r
+ //PCI_ACPI_UNUSED,\r
+ //PCI_ACPI_UNUSED,\r
+ //PCI_ACPI_UNUSED,\r
+ //PCI_ACPI_UNUSED,\r
+ //PCI_BAR_EVEN_ALIGN,\r
+ //PCI_BAR_ALL,\r
+ //PCI_BAR_NOCHANGE,\r
+\r
//\r
// The end of the list\r
//\r
//\r
// the incompatible PCI devices list for the values of configuration registers\r
//\r
-GLOBAL_REMOVE_IF_UNREFERENCED UINT64 IncompatiblePciDeviceListForRegister[] = {\r
+GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gIncompatiblePciDeviceListForRegister[] = {\r
//\r
// DEVICE_INF_TAG,\r
// PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),\r
// AND_VALUE, OR_VALUE\r
\r
//\r
- // Device Lava 0x1407, DeviceId 0x0110\r
+ // Sample Device 1\r
//\r
- DEVICE_INF_TAG,\r
- PCI_DEVICE_ID(0x1407, 0x0110, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
- DEVICE_RES_TAG,\r
- PCI_REGISTER_READ,\r
- PCI_CAPBILITY_POINTER_OFFSET,\r
- 0xffffff00,\r
- VALUE_NOCARE,\r
+ //DEVICE_INF_TAG,\r
+ //PCI_DEVICE_ID(0xXXXX, 0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
+ //DEVICE_RES_TAG,\r
+ //PCI_REGISTER_READ,\r
+ //PCI_CAPBILITY_POINTER_OFFSET,\r
+ //0xffffff00,\r
+ //VALUE_NOCARE,\r
\r
//\r
- // Device Lava 0x1407, DeviceId 0x0111\r
+ // Sample Device 2\r
//\r
- DEVICE_INF_TAG,\r
- PCI_DEVICE_ID(0x1407, 0x0111, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
- DEVICE_RES_TAG,\r
- PCI_REGISTER_READ,\r
- PCI_CAPBILITY_POINTER_OFFSET,\r
- 0xffffff00,\r
- VALUE_NOCARE,\r
+ //DEVICE_INF_TAG,\r
+ //PCI_DEVICE_ID(0xXXXX, 0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
+ //DEVICE_RES_TAG,\r
+ //PCI_REGISTER_READ,\r
+ //PCI_CAPBILITY_POINTER_OFFSET,\r
+ //0xffffff00,\r
+ //VALUE_NOCARE,\r
\r
//\r
// The end of the list\r
//\r
// the incompatible PCI devices list for the access width of configuration registers\r
//\r
-GLOBAL_REMOVE_IF_UNREFERENCED UINT64 DeviceListForAccessWidth[] = {\r
+GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gDeviceListForAccessWidth[] = {\r
//\r
// DEVICE_INF_TAG,\r
// PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),\r
/** @file\r
- The implementation of PCI incompatible device support libary.\r
+ The template of PCI incompatible device support libary.\r
\r
-Copyright (c) 2006 - 2007, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "IncompatiblePciDeviceList.h"\r
\r
+EFI_PCI_REGISTER_ACCESS_DATA mPciRegisterAccessData = {0, 0, 0}; \r
+EFI_PCI_REGISTER_VALUE_DATA mPciRegisterValueData = {0, 0};\r
+ \r
+\r
/**\r
- Check whether two PCI devices matched\r
+ Check whether two PCI devices matched.\r
\r
- @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.\r
- @param Header A pointer to EFI_PCI_DEVICE_INFO.\r
+ @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.\r
+ @param Header A pointer to EFI_PCI_DEVICE_INFO.\r
+\r
+ @retval EFI_SUCCESS Two PCI devices matched.\r
+ @retval EFI_UNSUPPORTED Two PCI devices don't match.\r
\r
- @retval returns EFI_SUCCESS if two PCI device matched.\r
**/\r
EFI_STATUS\r
DeviceCheck (\r
\r
/**\r
Check the incompatible device list for ACPI resource update and return\r
- the configuration\r
+ the configuration.\r
\r
This function searches the incompatible device list according to request\r
information. If the PCI device belongs to the devices list, corresponding\r
configuration informtion will be returned, in the meantime return EFI_SUCCESS.\r
\r
- @param PciDeviceInfo A pointer to PCI device information.\r
- @param Configuration Returned information.\r
+ @param PciDeviceInfo A pointer to PCI device information.\r
+ @param Configuration Returned information.\r
+\r
+ @retval EFI_SUCCESS If check incompatible device successfully.\r
+ @retval EFI_ABORTED No any resource type.\r
+ @retval EFI_OUT_OF_RESOURCES No memory available.\r
+ @retval EFI_UNSUPPORTED Invalid Tag encounted.\r
\r
- @retval returns EFI_SUCCESS if check incompatible device ok.\r
- Otherwise return EFI_UNSUPPORTED.\r
**/\r
-RETURN_STATUS\r
+EFI_STATUS\r
EFIAPI\r
PciResourceUpdateCheck (\r
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
//\r
* (VOID **) Configuration = NULL;\r
\r
- ListPtr = IncompatiblePciDeviceListForResource;\r
+ ListPtr = gIncompatiblePciDeviceListForResource;\r
while (*ListPtr != LIST_END_TAG) {\r
\r
Tag = *ListPtr;\r
\r
AcpiPtr = AllocateZeroPool (\r
sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * Index + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)\r
- );\r
+ );\r
if (AcpiPtr == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
@param Offset The address within the PCI configuration space.\r
@param Configuration Returned information.\r
\r
- @retval returns EFI_SUCCESS if check incompatible device ok.\r
- Otherwise return EFI_UNSUPPORTED.\r
+ @retval EFI_SUCCESS If check incompatible device successfully.\r
+ @retval EFI_UNSUPPORTED Failed to check incompatibility device.\r
+\r
**/\r
-RETURN_STATUS\r
+EFI_STATUS\r
EFIAPI\r
PciRegisterUpdateCheck (\r
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
\r
ASSERT (PciDeviceInfo != NULL);\r
\r
- ListPtr = IncompatiblePciDeviceListForRegister;\r
+ ListPtr = gIncompatiblePciDeviceListForRegister;\r
\r
//\r
// Initialize the return value to NULL\r
if (((EFI_PCI_REGISTER_VALUE_DESCRIPTOR *)ListPtr)->AccessType == AccessType) {\r
\r
Dsc = (EFI_PCI_REGISTER_VALUE_DATA *) (ListPtr + 2);\r
- RegisterPtr = AllocateZeroPool (sizeof (EFI_PCI_REGISTER_VALUE_DATA));\r
- if (RegisterPtr == NULL) {\r
- return EFI_SUCCESS;\r
- }\r
+ \r
+ RegisterPtr = &mPciRegisterValueData;\r
\r
RegisterPtr->AndValue = Dsc->AndValue;\r
RegisterPtr->OrValue = Dsc->OrValue;\r
@param AccessWidth Access width needs to check incompatibility.\r
@param Configuration Returned information.\r
\r
- @retval returns EFI_SUCCESS if check incompatible device ok.\r
- Otherwise return EFI_UNSUPPORTED.\r
+ @retval EFI_SUCCESS If check incompatible device successfully.\r
+ @retval EFI_UNSUPPORTED Failed to check incompatibility device.\r
+\r
**/\r
-RETURN_STATUS\r
+EFI_STATUS\r
EFIAPI\r
PciRegisterAccessCheck (\r
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
\r
ASSERT (PciDeviceInfo != NULL);\r
\r
- ListPtr = DeviceListForAccessWidth;\r
+ ListPtr = gDeviceListForAccessWidth;\r
\r
//\r
// Initialize the return value to NULL\r
\r
if((Dsc->StartOffset <= Offset) && (Dsc->EndOffset > Offset)) {\r
\r
- RegisterPtr = AllocateZeroPool (sizeof (EFI_PCI_REGISTER_ACCESS_DATA));\r
- if (RegisterPtr == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
+ RegisterPtr = &mPciRegisterAccessData;\r
\r
RegisterPtr->StartOffset = Dsc->StartOffset;\r
RegisterPtr->EndOffset = Dsc->EndOffset;\r
#/** @file\r
-# PCI Incompatible device support Library\r
+# PCI Incompatible device support Library template.\r
#\r
-# Check PCI incompatible devices and set necessary configuration\r
+# Check PCI incompatible devices and set necessary configuration.\r
# Copyright (c) 2007 - 2009, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
projects / mirror_edk2.git / commitdiff